JP2008508747A5 - - Google Patents

Download PDF

Info

Publication number
JP2008508747A5
JP2008508747A5 JP2007509443A JP2007509443A JP2008508747A5 JP 2008508747 A5 JP2008508747 A5 JP 2008508747A5 JP 2007509443 A JP2007509443 A JP 2007509443A JP 2007509443 A JP2007509443 A JP 2007509443A JP 2008508747 A5 JP2008508747 A5 JP 2008508747A5
Authority
JP
Japan
Prior art keywords
vector
bit
vectors
coded
encoded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2007509443A
Other languages
English (en)
Japanese (ja)
Other versions
JP2008508747A (ja
Filing date
Publication date
Priority claimed from US10/799,054 external-priority patent/US6876315B1/en
Application filed filed Critical
Publication of JP2008508747A publication Critical patent/JP2008508747A/ja
Publication of JP2008508747A5 publication Critical patent/JP2008508747A5/ja
Pending legal-status Critical Current

Links

JP2007509443A 2004-03-12 2004-06-10 ローカル・パリティを伴うｄｃバランス６ｂ／８ｂ送信コード Pending JP2008508747A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/799,054 US6876315B1 (en) 2004-03-12 2004-03-12 DC-balanced 6B/8B transmission code with local parity
PCT/US2004/018619 WO2005096506A1 (en) 2004-03-12 2004-06-10 Dc-balanced 6b/8b transmission code with local parity

Publications (2)

Publication Number Publication Date
JP2008508747A JP2008508747A (ja) 2008-03-21
JP2008508747A5 true JP2008508747A5 (enExample) 2009-06-18

Family

ID=34377790

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007509443A Pending JP2008508747A (ja) 2004-03-12 2004-06-10 ローカル・パリティを伴うｄｃバランス６ｂ／８ｂ送信コード

Country Status (6)

Country Link
US (1) US6876315B1 (enExample)
EP (1) EP1723724A1 (enExample)
JP (1) JP2008508747A (enExample)
KR (1) KR20060129398A (enExample)
CN (1) CN101076945A (enExample)
WO (1) WO2005096506A1 (enExample)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6459331B1 (en) 1997-09-02 2002-10-01 Kabushiki Kaisha Toshiba Noise suppression circuit, ASIC, navigation apparatus communication circuit, and communication apparatus having the same
JP4351156B2 (ja) * 2002-06-20 2009-10-28 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Ｄｃ制御のためのバランスがとられたディスパリティチャネルコード
US7307554B2 (en) * 2004-12-20 2007-12-11 Kawasaki Microelectronics, Inc. Parallel data transmission method and parallel data transmission system
US7292161B2 (en) * 2005-05-31 2007-11-06 International Business Machines Corporation NB/MB coding apparatus and method using both disparity independent and disparity dependent encoded vectors
US7327293B2 (en) * 2006-03-03 2008-02-05 Honeywell International Inc. Compression and data encoding for transmission over a character-based protocol
AU2006204634B2 (en) * 2006-08-31 2009-10-29 Canon Kabushiki Kaisha Runlength encoding of leading ones and zeros
US7405679B1 (en) 2007-01-30 2008-07-29 International Business Machines Corporation Techniques for 9B10B and 7B8B coding and decoding
AU2007214319A1 (en) * 2007-08-30 2009-03-19 Canon Kabushiki Kaisha Improvements for Spatial Wyner Ziv Coding
DE102007053811A1 (de) * 2007-11-12 2009-05-14 Robert Bosch Gmbh Verfahren zum Übertragen von Daten
WO2009104154A1 (en) * 2008-02-19 2009-08-27 Nxp B.V. Modified coding with an additional control symbol
US8228911B2 (en) 2008-09-19 2012-07-24 Honeywell International Inc. Enhanced data link communication over iridium
EP2239852A1 (en) * 2009-04-09 2010-10-13 Thomson Licensing Method and device for encoding an input bit sequence and corresponding decoding method and device
JP2012525627A (ja) 2009-04-29 2012-10-22 ヒューレット−パッカード デベロップメント カンパニー エル．ピー． 光学メモリ拡張
JP5657242B2 (ja) * 2009-12-09 2015-01-21 株式会社東芝 半導体装置及びメモリシステム
US9513907B2 (en) * 2013-08-06 2016-12-06 Intel Corporation Methods, apparatus, instructions and logic to provide vector population count functionality
US9495155B2 (en) 2013-08-06 2016-11-15 Intel Corporation Methods, apparatus, instructions and logic to provide population count functionality for genome sequencing and alignment
US9197368B2 (en) * 2013-09-24 2015-11-24 Broadcom Corporation Inband management of ethernet links
US9270411B2 (en) * 2014-02-03 2016-02-23 Valens Semiconductor Ltd. Indicating end of idle sequence by replacing certain code words with alternative code words
US9270403B2 (en) * 2014-02-03 2016-02-23 Valens Semiconductor Ltd. Indicating end of idle sequence by replacing expected code words while maintaining running disparity
US9154156B2 (en) * 2014-02-25 2015-10-06 Qualcomm Incorporated Ternary line code design for controlled decision feedback equalizer error propagation
CN111178008A (zh) * 2019-12-19 2020-05-19 清华大学 一种面向数字字符的数据编码方法、解析方法及系统
CN112838868B (zh) * 2020-12-30 2022-09-09 天津瑞发科半导体技术有限公司 一种9b/10b编解码方法
CN114598579B (zh) * 2022-03-03 2023-07-07 天津瑞发科半导体技术有限公司 一种适用于低通和带通信道的9b/10b编解码方法
EP4236219B1 (de) * 2022-09-27 2025-08-27 INOVA Semiconductors GmbH Effizient übertragbare bitfolge mit eingeschränkter disparität

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4486739A (en) * 1982-06-30 1984-12-04 International Business Machines Corporation Byte oriented DC balanced (0,4) 8B/10B partitioned block transmission code
US5304996A (en) * 1992-02-21 1994-04-19 Advanced Micro Devices, Inc. 8B/10B encoder providing one of pair of noncomplementary, opposite disparity codes responsive to running disparity and selected commands
US5387911A (en) * 1992-02-21 1995-02-07 Gleichert; Marc C. Method and apparatus for transmitting and receiving both 8B/10B code and 10B/12B code in a switchable 8B/10B transmitter and receiver
JP3541439B2 (ja) * 1994-07-08 2004-07-14 ソニー株式会社 信号変調方法及び装置、並びに信号復調装置及び方法
US5784387A (en) 1994-10-31 1998-07-21 International Business Machines Corporation Method for detecting start-of-frame, end of frame and idle words in a data stream
US5606317A (en) * 1994-12-09 1997-02-25 Lucent Technologies Inc. Bandwidth efficiency MBNB coding and decoding method and apparatus
US5699062A (en) 1995-02-01 1997-12-16 International Business Machines Corporation Transmission code having local parity
CN1150871A (zh) * 1995-04-12 1997-05-28 株式会社东芝 代码变换和译码装置及方法以及记录媒体

Similar Documents

Publication Publication Date Title
JP2008508747A5 (enExample)
US4463344A (en) Method and apparatus for generating a noiseless sliding block code for a (2,7) channel with rate 1/2
CN110768785B (zh) 一种编、解码方法、相关装置及计算机设备
JPH01256251A (ja) コード化方法
US20090146851A1 (en) N-State Ripple Adder Scheme Coding with Corresponding N-State Ripple Adder Scheme Decoding
JP2008508747A (ja) ローカル・パリティを伴うｄｃバランス６ｂ／８ｂ送信コード
CN104038233B (zh) 基于相邻位异或运算的测试数据压缩与解压缩方法
KR100281738B1 (ko) 니블 반전 및 블록 반전 부호의 부호화 및 복호화 방법, 그 부호 및 복호장치
CN107124251A (zh) 一种基于任意内核的极化码编码方法
CN101582866A (zh) 编码数据封包的方法及编码系统
US7683810B2 (en) Code design with decreased transition density and reduced running digital sum
CN113268219B (zh) 一种带二进制补码转换的加法器电路
US7855665B1 (en) Enumerative DC-RLL constrained coding
US6691275B1 (en) Encoder with vector-calculated disparity logic
CN106951212B (zh) 一种极化码解码器中f、g运算单元的硬件架构
Bian et al. A low-latency SC polar decoder based on the sequential logic optimization
CN102118225A (zh) 基于多索引表的任意位多项式除法类型编码的编解码方法
Armand et al. Low power design of binary signed digit residue number system adder
JP2002014804A (ja) 三値ディジタル回路
US7123173B1 (en) Method and system for a feed-forward encoder
CN115658007A (zh) 一种高带宽可配流水级的并行乘法器运算方法
CN113792511A (zh) 一种高计算准确度、低硬件开销单变量随机电路及其配置方法
JP2009503927A (ja) ４レベル論理デコーダ
JP6293125B2 (ja) ５ｂ／６ｂ符号化のための回路装置、デバイス及び方法
CN101346884A (zh) 卷积编码器、通信装置以及卷积编码方法