JP2008503138A - 性能調整のための閉ループ制御 - Google Patents
性能調整のための閉ループ制御 Download PDFInfo
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- JP2008503138A JP2008503138A JP2007516107A JP2007516107A JP2008503138A JP 2008503138 A JP2008503138 A JP 2008503138A JP 2007516107 A JP2007516107 A JP 2007516107A JP 2007516107 A JP2007516107 A JP 2007516107A JP 2008503138 A JP2008503138 A JP 2008503138A
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- 238000000034 method Methods 0.000 claims abstract description 16
- 230000004044 response Effects 0.000 claims abstract description 8
- 238000012544 monitoring process Methods 0.000 claims description 26
- 230000001276 controlling effect Effects 0.000 claims description 11
- 238000012545 processing Methods 0.000 claims description 10
- 238000002955 isolation Methods 0.000 claims description 9
- 230000007704 transition Effects 0.000 claims description 7
- 230000001105 regulatory effect Effects 0.000 claims description 6
- 230000007423 decrease Effects 0.000 claims description 5
- 230000001360 synchronised effect Effects 0.000 claims description 3
- 230000001629 suppression Effects 0.000 claims description 2
- 230000008569 process Effects 0.000 abstract description 4
- 230000006978 adaptation Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 19
- 230000006870 function Effects 0.000 description 18
- 238000005516 engineering process Methods 0.000 description 10
- 230000008859 change Effects 0.000 description 8
- 230000000875 corresponding effect Effects 0.000 description 8
- 238000013459 approach Methods 0.000 description 7
- 230000008901 benefit Effects 0.000 description 5
- 230000003044 adaptive effect Effects 0.000 description 3
- 239000000872 buffer Substances 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 230000006399 behavior Effects 0.000 description 2
- 230000001627 detrimental effect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000007493 shaping process Methods 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 230000003190 augmentative effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000007717 exclusion Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 230000002123 temporal effect Effects 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/28—Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3296—Power saving characterised by the action undertaken by lowering the supply or operating voltage
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
- Power Sources (AREA)
- Testing, Inspecting, Measuring Of Stereoscopic Televisions And Televisions (AREA)
- Power Conversion In General (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Description
Claims (18)
- 監視される性能指標に応答して集積回路の性能を制御するための回路構成であって、
a)前記性能指標を受け取り、前記性能指標に基づいて前記集積回路の電力供給を制御するための性能制御手段と、
b)前記制御された電力供給の少なくとも雑音レベルをチェックし、チェック結果が所定の範囲内にない場合、前記性能制御手段にそれぞれの制御信号を通知するための監視手段であって、電力供給電圧上の前記雑音が所定の最大値を超過したかどうかをチェックするための電力供給雑音監視手段を備える監視手段と、を備える、回路構成。 - 前記性能制御手段が、前記電力供給を制御するための電圧制御手段に接続される、請求項1に記載の回路構成。
- 前記電圧制御手段が、可変抵抗手段と電圧レギュレータ手段の少なくとも一方を備える、請求項2に記載の回路構成。
- 前記監視手段が、クロック・パルスを所定遅延のクロック・パルスと同期した基準パルスと比較するためのクロック比較手段をさらに備える、前記請求項のいずれか1項に記載の回路構成。
- 前記監視手段が、最悪ケース経路遅延に関連する所定の時間間隔だけ前記クロック・パルスを遅延させるための遅延手段をさらに備える、請求項4に記載の回路構成。
- 前記性能制御手段が、現在のシステム状態についての情報を保存し、前記受け取った性能指標に対応する状態への遷移を制御する有限ステートマシンを備える、前記請求項のいずれか1項に記載の回路構成。
- 前記性能制御手段が、前記それぞれの制御信号の受け取りに応答して状態遷移を抑制するための抑制手段を備える、請求項6に記載の回路構成。
- 前記性能制御手段が、公称電力供給で動作し、前記監視手段が、前記制御された電力供給で動作する、前記請求項のいずれか1項に記載の回路構成。
- 前記それぞれの制御信号のレベルをシフトするため、およびレベル・シフトされた制御信号を前記性能監視手段に供給するためのシフティング手段をさらに備える、請求項8に記載の回路構成。
- 前記性能制御手段が、前記集積回路のバック・バイアス電圧を制御するように構成される、前記請求項のいずれか1項に記載の回路構成。
- 少なくとも2つの絶縁回路領域を有し、前記性能制御手段が、前記少なくとも2つの絶縁回路領域の処理パイプラインの少なくとも1つのレジスタ手段をスキップするためのバイパス手段を制御するように構成される、請求項1から10のいずれか1項に記載の回路構成。
- 少なくとも2つの絶縁回路領域を有し、前記可変抵抗手段と、調整されたクロック信号を前記絶縁回路領域に供給するためのクロック発生器手段とに接続されるシフト・レジスタ手段をさらに備え、前記シフト・レジスタ手段が、前記性能制御手段から供給される2進制御信号に基づいて制御され、前記2進制御信号が、前記集積回路の性能を引き上げるまたは引き下げるために、前記シフト・レジスタ手段に移される2進値を定義する、請求項3に記載の回路構成。
- 前記シフト・レジスタ手段のビット値が、前記クロック発生器手段の遅延セクションを個別にバイパスするために使用される、請求項12に記載の回路構成。
- 前記性能制御手段が、複数のプロファイル・モードの中から所定のプロファイル・モードを選択するように構成され、各プロファイル・モードが、前記集積回路の1組の性能パラメータの間の所定の関係を定義する、請求項1〜13のいずれか1項に記載の回路構成。
- 前記性能パラメータは、クロック周波数と、電力供給電圧と、閾値電圧とを備える、請求項14に記載の回路構成。
- 前記所定のプロファイル・モードおよび前記性能パラメータが、検索テーブル内に保存される、請求項14または15に記載の回路構成。
- 前記複数のプロファイル・モードが、前記電力供給電圧と前記クロック周波数が一定の関係に維持されるプロファイル・モードを備える、請求項14から16のいずれか1項に記載の回路構成。
- 監視される性能指標に応答して集積回路の性能を制御するための方法であって、
a)前記性能指標に基づいて前記集積回路の電力供給を制御するステップと、
b)前記制御された電力供給の少なくとも雑音レベルをチェックするステップと、
c)チェック結果が所定の範囲内にない場合、前記制御ステップにそれぞれの制御信号をフィードバックするステップと、を備える、方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP04102719A EP1607835A1 (en) | 2004-06-15 | 2004-06-15 | Closed-loop control for performance tuning |
EP04102719.4 | 2004-06-15 | ||
PCT/IB2005/051894 WO2005124516A2 (en) | 2004-06-15 | 2005-06-09 | Closed-loop control for performance tuning |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008503138A true JP2008503138A (ja) | 2008-01-31 |
JP5051582B2 JP5051582B2 (ja) | 2012-10-17 |
Family
ID=34929201
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007516107A Active JP5051582B2 (ja) | 2004-06-15 | 2005-06-09 | 性能調整のための閉ループ制御 |
Country Status (5)
Country | Link |
---|---|
US (1) | US7930577B2 (ja) |
EP (2) | EP1607835A1 (ja) |
JP (1) | JP5051582B2 (ja) |
CN (1) | CN100576146C (ja) |
WO (1) | WO2005124516A2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2009110290A1 (ja) * | 2008-03-04 | 2009-09-11 | 日本電気株式会社 | 半導体デバイス |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
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WO2007091129A1 (en) * | 2006-02-09 | 2007-08-16 | Freescale Semiconductor, Inc. | Device and method for testing a noise immunity characteristic of analog circuits |
CN101467116B (zh) | 2006-06-15 | 2010-10-13 | Nxp股份有限公司 | 为处理器提供时钟频率的方法及电子设备 |
US7721119B2 (en) * | 2006-08-24 | 2010-05-18 | International Business Machines Corporation | System and method to optimize multi-core microprocessor performance using voltage offsets |
USRE46782E1 (en) * | 2006-12-21 | 2018-04-10 | Marvell International Ltd. | Closed loop voltage control using adjustable delay lines |
KR100862113B1 (ko) * | 2007-01-22 | 2008-10-09 | 삼성전자주식회사 | 공정 변화에 대한 정보를 이용하여 공급전압/공급주파수를제어할 수 있는 장치와 방법 |
JP2008263723A (ja) * | 2007-04-12 | 2008-10-30 | Funai Electric Co Ltd | 保護回路及び電子機器 |
WO2009094709A1 (en) * | 2008-02-01 | 2009-08-06 | Cochlear Limited | An apparatus and method for optimising power consumption of a digital circuit |
US8020138B2 (en) * | 2008-06-02 | 2011-09-13 | International Business Machines Corporation | Voltage island performance/leakage screen monitor for IP characterization |
GB2476606B (en) | 2008-09-08 | 2012-08-08 | Virginia Tech Intell Prop | Systems, devices, and methods for managing energy usage |
WO2010055462A1 (en) * | 2008-11-13 | 2010-05-20 | Nxp B.V. | Testable integrated circuit and test method therefor |
US8661274B2 (en) * | 2009-07-02 | 2014-02-25 | Qualcomm Incorporated | Temperature compensating adaptive voltage scalers (AVSs), systems, and methods |
US8423802B2 (en) * | 2010-04-07 | 2013-04-16 | Andes Technology Corporation | Power scaling module and power scaling unit of an electronic system having a function unit in a standby state which is insensitive to change in frequency or voltage during synchronization |
DE102010044924B4 (de) | 2010-09-10 | 2021-09-16 | Texas Instruments Deutschland Gmbh | Elektronische Vorrichtung und Verfahren für diskrete lastadaptive Spannungsregelung |
US9048831B2 (en) * | 2012-07-13 | 2015-06-02 | General Electric Company | Systems and methods for regulating semiconductor devices |
CN104035018B (zh) * | 2014-06-12 | 2017-04-19 | 华为技术有限公司 | 电压自适应调整电路和芯片 |
CN105095592B (zh) * | 2015-08-13 | 2017-11-21 | 北京航空航天大学 | 一种新型集成电路芯片的片上电源噪声自主调节系统及其调节方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH04160519A (ja) * | 1990-10-24 | 1992-06-03 | Nec Corp | 電源制御回路 |
WO1998006022A2 (en) * | 1996-08-07 | 1998-02-12 | Motorola Semiconducteurs S.A. | Methods and circuits for dynamically adjusting a supply voltage and/or a frequency of a clock signal in a digital circuit |
JPH11296243A (ja) * | 1998-04-13 | 1999-10-29 | Fujitsu Ltd | 電源電圧調整回路及び半導体装置並びに半導体装置の電源電圧調整方法 |
US20040070464A1 (en) * | 2002-05-02 | 2004-04-15 | Wong Keng L. | Voltage control for clock generating circuit |
Family Cites Families (9)
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JP2000020183A (ja) * | 1998-07-03 | 2000-01-21 | Fujitsu Ltd | 電源供給装置 |
US6873926B1 (en) * | 2001-02-27 | 2005-03-29 | Cisco Technology, Inc. | Methods and apparatus for testing a clock signal |
US7159134B2 (en) * | 2001-08-29 | 2007-01-02 | Analog Devices, Inc. | Method and apparatus for clock and power control in wireless systems |
US6700390B2 (en) * | 2002-05-31 | 2004-03-02 | Sun Microsystems, Inc. | Adjustment and calibration system to store resistance settings to control chip/package resonance |
US6785161B2 (en) * | 2002-06-28 | 2004-08-31 | Micron Technology, Inc. | High voltage regulator for low voltage integrated circuit processes |
US7024568B2 (en) * | 2002-09-06 | 2006-04-04 | National Semiconductor Corporation | Method and system for providing self-calibration for adaptively adjusting a power supply voltage in a digital processing system |
US6842027B2 (en) * | 2002-10-07 | 2005-01-11 | Intel Corporation | Method and apparatus for detection and quantification of on-die voltage noise in microcircuits |
US7392411B2 (en) * | 2003-04-25 | 2008-06-24 | Ati Technologies, Inc. | Systems and methods for dynamic voltage scaling of communication bus to provide bandwidth based on whether an application is active |
US7447919B2 (en) * | 2004-04-06 | 2008-11-04 | Hewlett-Packard Development Company, L.P. | Voltage modulation for increased reliability in an integrated circuit |
-
2004
- 2004-06-15 EP EP04102719A patent/EP1607835A1/en not_active Withdrawn
-
2005
- 2005-06-09 WO PCT/IB2005/051894 patent/WO2005124516A2/en active Application Filing
- 2005-06-09 CN CN200580027651A patent/CN100576146C/zh active Active
- 2005-06-09 EP EP05745513.1A patent/EP1769314B1/en not_active Not-in-force
- 2005-06-09 JP JP2007516107A patent/JP5051582B2/ja active Active
- 2005-06-09 US US11/629,716 patent/US7930577B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04160519A (ja) * | 1990-10-24 | 1992-06-03 | Nec Corp | 電源制御回路 |
WO1998006022A2 (en) * | 1996-08-07 | 1998-02-12 | Motorola Semiconducteurs S.A. | Methods and circuits for dynamically adjusting a supply voltage and/or a frequency of a clock signal in a digital circuit |
JPH11296243A (ja) * | 1998-04-13 | 1999-10-29 | Fujitsu Ltd | 電源電圧調整回路及び半導体装置並びに半導体装置の電源電圧調整方法 |
US20040070464A1 (en) * | 2002-05-02 | 2004-04-15 | Wong Keng L. | Voltage control for clock generating circuit |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2009110290A1 (ja) * | 2008-03-04 | 2009-09-11 | 日本電気株式会社 | 半導体デバイス |
JP5344190B2 (ja) * | 2008-03-04 | 2013-11-20 | 日本電気株式会社 | 半導体デバイス |
Also Published As
Publication number | Publication date |
---|---|
EP1607835A1 (en) | 2005-12-21 |
WO2005124516A2 (en) | 2005-12-29 |
US7930577B2 (en) | 2011-04-19 |
CN100576146C (zh) | 2009-12-30 |
EP1769314B1 (en) | 2019-03-13 |
EP1769314A2 (en) | 2007-04-04 |
WO2005124516A3 (en) | 2006-08-03 |
JP5051582B2 (ja) | 2012-10-17 |
CN101006411A (zh) | 2007-07-25 |
US20080106327A1 (en) | 2008-05-08 |
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