JP2008283240A - Charge transfer section and solid-state imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging apparatus that improves horizontal transfer of signal charges while achieving an increase in the amount of electric charges that a horizontal transfer register handles. <P>SOLUTION: The solid-state imaging apparatus has an imaging section and the horizontal transfer register transferring signal charges transferred by the imaging section, wherein transfer electrodes are divided into three H1a, H1b, and H1c (H2a, H2b, and H2c) and the falling timing of a transfer clock applied to the transfer electrode H1c (H2c) is made earlier than the falling timings of transfer clocks applied to the transfer electrodes H1a and H2b (H2a and H2b). <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a charge transfer unit and a solid-state imaging device. Specifically, the present invention relates to a charge transfer unit suitable for use in a horizontal transfer register of a CCD area sensor, a transfer register of a CCD linear sensor, a transfer register of a CCD delay element, and a solid-state imaging device using such a charge transfer unit.

  FIG. 6 is a schematic plan view for explaining a conventional CCD (Charge Coupled Device) solid-state imaging device, and FIG. 7A shows a horizontal transfer register (reference A- in FIG. 6) of the conventional CCD solid-state imaging device. It is a schematic diagram for demonstrating the potential of the area | region shown by A '.

  A conventional CCD solid-state imaging device includes a plurality of light receiving portions 101 arranged in a matrix in a silicon substrate, a read gate (not shown) that is provided adjacent to the light receiving portions and reads signal charges taken in by the light receiving portions. A vertical transfer register 103 which is provided adjacent to the read gate and transfers the signal charge read by the read gate in the vertical direction; a horizontal transfer register 104 which transfers the signal charge transferred by the vertical transfer register in the horizontal direction; A channel stop region (not shown) that is provided on the side opposite to the readout gate of the light receiving portion and suppresses color mixing is formed (for example, see Patent Document 1). In addition, the horizontal transfer register has a plurality of charge storage units that store the signal charges obtained from the light receiving unit, and changes the potential of the charge storage unit by applying a transfer clock to the transfer electrode on the horizontal transfer register. The signal charges are horizontally transferred between the charge storage units.

Each charge storage unit includes a storage unit (St) that performs charge retention and a transfer unit (Tr) that performs charge transfer.
Furthermore, a potential difference is also formed in the transfer portion by impurity ion implantation in order to improve the transfer of signal charges. Specifically, in the transfer part (1) indicated by reference numeral Tr1 in FIG. 7A and the transfer part (2) indicated by reference sign Tr2 in FIG. 7A, the transfer located on the transfer direction side of the signal charge. Impurity ion implantation is performed so that the potential of the portion (1) is deeper than the potential of the transfer portion (2).

  Here, in general, horizontal transfer of a horizontal transfer register is a two-phase drive, that is, a structure in which signal charges are transferred by applying transfer clocks (φH1, φH2) to transfer electrodes (H1, H2) on the horizontal transfer register. Adopted. Specifically, a transfer clock indicated by reference sign φH1 in FIG. 7B is applied to the transfer electrode indicated by reference sign H1 in FIG. 7A, and the transfer electrode indicated by reference sign H2 in FIG. b) A transfer clock indicated by a middle symbol φH2 is applied (in general, the amplitude of φH1 / φH2 is about 3 to 5 V, and φH1 and φH2 are transfer clocks in opposite phases), and the potential of the horizontal transfer register. The signal charge is transferred in the output direction (in the case of FIG. 7A, from the right direction to the left direction).

Incidentally, the amount of charge handled by the horizontal transfer register is determined by the potential of the shallowest region in the charge storage unit.
Specifically, as shown in FIG. 8A, the amount of signal charge that can be accumulated in each charge accumulating portion is that both φH1 and φH2 are at a middle level (hereinafter referred to as “M level”). The amount of signal charge that can be accumulated in each charge storage unit (the amount of signal charge indicated by symbol a in FIG. 8A) is It is determined by the potential of the transfer portion (2) (the potential in the region where the potential in the charge storage portion is the shallowest). Therefore, the amount of charge handled by the horizontal transfer register is also determined by the potential of the transfer unit (2) (the potential of the region where the potential in the charge storage unit is the shallowest).
Therefore, in order to increase the amount of charge handled by the horizontal transfer register, it is necessary to reduce the potential of the region where the potential in the charge storage portion is the shallowest. That is, the amount of charge handled by the horizontal transfer register can be increased by reducing the potential of the transfer portion (2), which is the shallowest region of the charge storage portion.

  On the other hand, the signal charge transfer from the H1 electrode lower region (region to which φH1 is applied) to the H2 electrode lower region (region to which φH2 is applied) is improved and the signal charge from the H2 electrode lower region to the H1 electrode lower region is improved. For the purpose of improving the transfer, if the potential of the transfer portion (2) is deepened, the transfer of the signal charge from the H1 electrode lower region to the H2 electrode lower region and the transfer of the signal charge from the H2 electrode lower region to the H1 electrode lower region are performed. Although improved, the amount of charge handled by the charge storage portion is reduced. Specifically, as shown in FIG. 8B, when the potential of the transfer part (2) is deepened, the transfer electric field from the region under the H1 electrode to the region under the H2 electrode (indicated by the symbol b in FIG. 8B). Although the transfer electric field is increased, the amount of charge handled by the charge storage unit (the amount of signal charge indicated by the symbol c in FIG. 8B) is reduced.

Note that the transfer of signal charges in the entire horizontal transfer register is performed by transferring from under the H1 electrode to under the H2 electrode or from under the H2 electrode to under the H1 electrode rather than from under the H1 electrode or from under the H2 electrode. It is known that the impact on
Specifically, the potential difference between the transfer part (2) and the transfer part (1), the potential difference between the transfer part (1) and the storage part (the potential difference indicated by the symbol d in FIG. b) The potential difference between the storage portion and the transfer portion (2) (the potential difference indicated by the symbol b in FIG. 8B) has a greater influence on the overall signal charge than the potential difference indicated by the symbol e in the middle). It is known.

  Here, when the amount of charge handled by the charge storage unit decreases, when a high-luminance subject is photographed, all of the signal charges photoelectrically converted by the light receiving unit cannot be stored in each charge storage unit, Part of the signal charge may leak into the adjacent charge storage portion. When a part of the signal charge leaks into the adjacent charge storage part, color mixing is caused as a result.

  Also, if the potential difference from the H1 electrode lower region to the H2 electrode lower region or the potential difference from the H2 electrode lower region to the H1 electrode lower region is reduced, the signal charge is not completely transferred and a part of the signal charge is In some cases, the signal charges are left behind and transferred together with the signal charges transferred immediately afterward. When a part of the signal charge is transferred together with the signal charge transferred immediately afterward, color mixing is caused as a result.

JP-A-10-144907

  As described above, the amount of charge handled by the horizontal transfer register and the improvement in signal charge transfer are in a trade-off relationship, and it is very difficult to achieve both, but the amount of charge handled by the horizontal transfer register is increasing. However, it has been strongly desired to improve signal charge transfer.

  The present invention has been made in view of the above points, and provides a charge transfer unit and a solid-state imaging device capable of improving the transfer of signal charges while increasing the amount of charge handled by a transfer register. It is intended.

  In order to achieve the above object, a charge transfer unit according to the present invention has a plurality of charge storage units that store signal charges, and a signal is transferred between the charge storage units by changing the potential of the charge storage unit. In the charge transfer unit for transferring charges, the charge storage unit includes a first region and a second region adjacent to the signal charge transfer direction side of the first region, and the first region The fall timing of the transfer clock applied to is earlier than the fall timing of the transfer clock applied to the second area.

  Here, since the falling timing of the transfer clock applied to the first area is earlier than the falling timing of the transfer clock applied to the second area, it is handled without adversely affecting the transfer of the signal charge. The amount of charge can be increased.

  In order to achieve the above object, the solid-state imaging device according to the present invention includes an imaging unit and a charge transfer unit that transfers a signal charge transferred from the imaging unit. In the solid-state imaging device having a plurality of charge storage units that store charges and transferring signal charges between the charge storage units by changing the potential of the charge storage units, the charge storage unit includes a first region And a second region adjacent to the signal charge transfer direction side of the first region, and the falling timing of the transfer clock applied to the first region is applied to the second region. Earlier than the falling timing of the transfer clock.

  Here, since the falling timing of the transfer clock applied to the first region is earlier than the falling timing of the transfer clock applied to the second region, the charge is not adversely affected to the transfer of the signal charge. The amount of charge handled by the transfer unit can be increased.

  In the charge transfer unit and the solid-state imaging device to which the present invention is applied, it is possible to realize both the transfer of signal charges and the increase in the amount of handled charges, which are considered to be in a trade-off relationship.

Hereinafter, embodiments of the present invention will be described with reference to the drawings to facilitate understanding of the present invention.
FIG. 1 is a schematic plan view for explaining a CCD solid-state imaging device (1) which is an example of a solid-state imaging device to which the present invention is applied, and FIG. 2 is a CCD solid-state imaging device (1) to which the present invention is applied. It is a schematic diagram for demonstrating this horizontal transfer register.

  The CCD solid-state imaging device shown here is similar to the conventional CCD solid-state imaging device described above, and is provided in the silicon substrate adjacent to the light receiving portions 1 arranged in a matrix, and is captured by the light receiving portion. A read gate (not shown) for reading out the signal charge, a vertical transfer register 3 provided adjacent to the read gate and transferring the signal charge read by the read gate in the vertical direction, and a signal transferred by the vertical transfer register A channel transfer region (not shown) is provided on the opposite side to the horizontal transfer register 4 for transferring charges in the horizontal direction and the readout gate of the light receiving unit, and suppresses color mixing. In addition, the horizontal transfer register has a plurality of charge storage units that store the signal charges obtained from the light receiving unit, and changes the potential of the charge storage unit by applying a transfer clock to the transfer electrode on the horizontal transfer register. The signal charges are horizontally transferred between the charge storage units.

  Here, each charge storage section of the horizontal transfer register is divided into a transfer section indicated by reference numeral Tr in FIG. 2 and a storage section indicated by reference numeral St in FIG. 2, and the transfer section is further transferred by reference numeral Tr1 in FIG. (1) and the transfer part (2) indicated by the reference numeral Tr2 in FIG. 2, the transfer electrodes (H1a, H2a) on the storage part, the transfer electrodes (H1b, H2b) on the transfer part (1), and A transfer electric field is formed from the Transfer section (2) toward the Storage section by individually applying a DC bias generated by the bias circuit 5 to the transfer electrodes (H1c, H2c) on the Transfer section (2). It is configured like this.

  Specifically, in the bias circuit, (DC bias value generated by the circuit indicated by reference numeral 5a in FIG. 2) = (DC bias value generated by the circuit indicated by reference numeral 5d in FIG. 2)> (at reference numeral 5b in FIG. 2) DC bias value generated by the circuit shown in FIG. 2 = (DC bias value generated by the circuit indicated by reference numeral 5e in FIG. 2)> (DC bias value generated by the circuit indicated by reference numeral 5c in FIG. 2) = (reference numeral 5e in FIG. 2) 2 is generated, and the DC bias generated by the circuit indicated by reference numeral 5a in FIG. 2 is applied to the transfer electrode indicated by reference numeral H1a in FIG. 2, and the reference numeral 5b in FIG. 2 is applied to the transfer electrode indicated by symbol H1b in FIG. 2, and the DC bias generated by the circuit indicated by symbol 5c in FIG. 2 is applied to the transfer electrode indicated by symbol H1c in FIG. 2d in FIG. 2 is applied to the transfer electrode indicated by symbol H2a in FIG. 2, and the DC bias generated by the circuit indicated by symbol 5e in FIG. 2 is applied to the transfer electrode indicated by symbol H2b in FIG. A transfer electric field is formed from the transfer portion (2) toward the storage portion by applying a DC bias generated in the circuit indicated by the intermediate symbol 5f to the transfer electrode indicated by the reference symbol H2c in FIG.

  The Transfer part (2) is an example of the first area, and the Transfer part (1) and the Storage part are examples of the second area. Further, the transfer part (1) is an example of the third area, and the storage part is an example of the fourth area.

  Further, a transfer clock indicated by symbol φH1α in FIG. 3 is applied to the transfer electrode indicated by symbol H1a in FIG. 2 via a capacitor C, and applied to the transfer electrode indicated by symbol H1b in FIG. 2 and the transfer electrode indicated by symbol H1c in FIG. A transfer clock indicated by symbol φH1β in FIG. 3 is applied via a capacitor C, and a transfer clock indicated by symbol φH2α in FIG. 3 is applied via a capacitor C to a transfer electrode indicated by symbol H2a in FIG. A transfer clock indicated by symbol φH2β in FIG. 3 is applied via a capacitor C to the transfer electrode indicated by symbol H2b and the transfer electrode indicated by symbol H2c in FIG.

  Accordingly, a DC bias generated by the circuit indicated by reference numeral 5a in FIG. 2 is applied to the transfer electrode indicated by reference numeral H1a in FIG. 2, and a transfer clock indicated by reference numeral φH1α in FIG. 3 is applied via the capacitor. A DC bias generated by a circuit indicated by reference numeral 5b in FIG. 2 is applied to the transfer electrode indicated by reference numeral H1b, and a transfer clock indicated by reference numeral φH1β in FIG. 3 is applied via a capacitor. A DC bias generated by a circuit indicated by reference numeral 5c in FIG. 2 is applied to the transfer electrode shown, and a transfer clock indicated by reference numeral φH1β in FIG. 3 is applied via a capacitor. 2 is applied with a DC bias generated by a circuit indicated by reference numeral 5d in FIG. 2 and a transfer clock indicated by reference numeral φH2α in FIG. 3 via a capacitor. A DC bias generated by the circuit indicated by reference numeral 5e in FIG. 2 is applied to the transfer electrode indicated by reference numeral H2b, and a transfer clock indicated by reference numeral φH2β in FIG. 3 is applied via a capacitor. A DC bias generated by a circuit indicated by reference numeral 5f in FIG. 2 is applied to the transfer electrode shown, and a transfer clock indicated by reference numeral φH2β in FIG. 3 is applied via a capacitor.

Hereinafter, driving of the CCD solid-state imaging device configured as described above will be described.
The timing chart of each transfer clock for horizontal transfer in the CCD solid-state imaging device configured as described above is as shown in FIG. 3. The transfer clock φH1β rises at the same timing as the transfer clock φH1α, and the transfer clock φH1β is transferred. The fall timing is earlier than the clock φH1α. Further, the transfer clock φH2β rises at the same timing as the transfer clock φH2α, and the transfer clock φH2β falls earlier than the transfer clock φH2α. Note that φH1α and φH2α are the same transfer clocks as φH1 and φH2 applied to the conventional CCD solid-state imaging device, and φH1α and φH2α are transfer clocks having opposite phases.

  At the timing indicated by the symbol t1 in FIG. 3, φH1α and φH1β are at the H level, φH2α and φH2β are at the L level, and signal charges are accumulated under the H1a electrode, the H1b electrode, and the H1c electrode ( (See FIG. 4A (a).) At this point, there is no particular difference from the above-described conventional CCD solid-state imaging device.

  Next, at the timing indicated by the symbol t2 in FIG. 3, the potential under the H1c electrode is made shallow by setting φH1β to the L level (see FIG. 4A (b)). Here, the reason why φH1β is set to the L level prior to φH1α is to increase the amount of charge handled by the charge storage unit to which the transfer clock is applied by the H1 electrodes (H1a, H1b, H1c).

  Subsequently, φH1α and φH2α are at the M level at the timing indicated by symbol t3 in FIG. 3, and the amount of charge handled at this timing is minimized. However, the potential below the H1c electrode is reduced at the timing indicated by symbol t2 in FIG. Since it is shallow, the signal charge does not overflow in the direction opposite to the transfer direction, and the adjacent pixel and the signal charge are not mixed. Although it is conceivable that the signal charge overflows in the signal charge transfer direction as the amount of charge handled increases, even if the signal charge overflows in the signal charge transfer direction, the signal charge does not mix with adjacent pixels. (See FIG. 4B (c).)

  Thereafter, φH1α and φH1β are set to L level and φH2α and φH2β are set to L level at the timing indicated by reference numeral t4 in FIG. 3, so that a transfer clock is applied to the H2 electrodes (H1a, H1b, H1c) from the charge storage unit The transfer of the signal charge to the charge storage portion to which the transfer clock is applied is completed at the electrodes (H2a, H2b, H2c) (see FIG. 4B (d)).

  Thereafter, horizontal transfer is realized by repeating the same driving as described above.

  FIG. 5A is a schematic diagram for explaining a horizontal transfer register of a CCD solid-state imaging device (2) which is another example of the solid-state imaging device to which the present invention is applied. The CCD solid-state image pickup device (2), which is another example of the solid-state image pickup device to which the present invention is applied, has a CCD solid-state image pickup device (example of a solid-state image pickup device to which the present invention is applied described above) except for the horizontal transfer register ( Same as 1). That is, the same structure as in FIG. 1 is adopted.

Each charge storage section of the horizontal transfer register of the CCD solid-state imaging device shown here is divided into a transfer section indicated by reference numeral Tr in FIG. 5A and a storage section indicated by reference numeral St in FIG. 5A. A potential difference is formed such that the potential of the storage portion becomes deeper than the potential of the transfer portion by impurity ion implantation.
Further, the transfer part is divided into a transfer part (1) indicated by reference numeral Tr1 in FIG. 5 (a) and a transfer part (2) indicated by reference numeral Tr2 in FIG. 5 (a). Transfer parts (2) indicated by reference numeral Tr2 in FIG. A potential difference is formed such that the potential of 1) is deeper than the potential of the transfer portion (2).

  Further, a transfer clock indicated by symbol φH1α in FIG. 3 is applied to the transfer electrode indicated by symbol H1a in FIG. 5A, and a transfer clock indicated by symbol φH1β in FIG. 3 is applied to the transfer electrode indicated by symbol H1b in FIG. 5A. 3 is applied to the transfer electrode indicated by symbol H2a in FIG. 5A, and the transfer clock indicated by symbol φH2α in FIG. 3 is applied to the transfer electrode indicated by symbol H2b in FIG. 5A at the symbol φH2β in FIG. The transfer clock shown is configured to be applied.

  The CCD solid-state imaging device configured as described above is also driven in the same manner as the CCD solid-state imaging device (1) which is an example of the solid-state imaging device to which the present invention is applied to perform horizontal transfer of signal charges. Become.

  FIG. 5B is a schematic diagram for explaining a horizontal transfer register of a CCD solid-state imaging device (3) which is still another example of the solid-state imaging device to which the present invention is applied. The CCD solid-state imaging device (3), which is still another example of the solid-state imaging device to which the present invention is applied, has a structure other than the horizontal transfer register, which is an example of the solid-state imaging device to which the present invention is applied. This is the same as the CCD solid-state imaging device (2) as another example of the solid-state imaging device to which (1) and the present invention are applied. That is, the same structure as in FIG. 1 is adopted.

Each charge storage section of the horizontal transfer register of the CCD solid-state imaging device shown here is divided into a transfer section indicated by reference numeral Tr in FIG. 5B and a storage section indicated by reference numeral St in FIG. 5B. A potential difference is formed such that the potential of the storage portion becomes deeper than the potential of the transfer portion by impurity ion implantation.
Further, the transfer part includes a transfer part (1) indicated by reference numeral Tr1 in FIG. 5 (b), a transfer part (2) indicated by reference numeral Tr2 in FIG. 5 (b), and a transfer part indicated by reference numeral Tr3 in FIG. 5 (b). The transfer portion (1), the transfer portion (2), and the transfer portion (3) are formed so that the potential becomes shallower in the order of impurity ion implantation.

  Further, a transfer clock indicated by symbol φH1α in FIG. 3 is applied to the transfer electrode indicated by symbol H1a in FIG. 5B, and a transfer clock indicated by symbol φH1β in FIG. 3 is applied to the transfer electrode indicated by symbol H1b in FIG. 5B. 3 is applied to the transfer electrode indicated by symbol H2a in FIG. 5B, and the transfer clock indicated by symbol H2b in FIG. 5B is applied to the transfer electrode indicated by symbol H2b in FIG. 5B at the symbol φH2β in FIG. The transfer clock shown is configured to be applied.

  The CCD solid-state imaging device configured as described above is also another example of the CCD solid-state imaging device (1) that is an example of the solid-state imaging device to which the present invention is applied and the solid-state imaging device to which the present invention is applied. It is driven in the same manner as the CCD solid-state imaging device (2) to perform horizontal transfer of signal charges.

  In the CCD solid-state imaging device (1) and the CCD solid-state imaging device (2) to which the present invention is applied, the transfer unit (2) can be driven separately from the transfer unit (1) and the storage unit. By making the falling timing of the transfer clock applied to the section (2) earlier than the falling timing of the transfer clock applied to the Transfer section (1) or the Storage section, the amount of charge handled by the horizontal transfer register is increased. It is possible to improve signal charge transfer in the horizontal transfer register.

  Similarly, in the CCD solid-state imaging device (3) to which the present invention is applied, the transfer unit (3) can be driven separately from the transfer unit (1), the transfer unit (2), and the storage unit. By making the falling timing of the transfer clock applied to (3) earlier than the falling timing of the transfer clock applied to the Transfer unit (1), Transfer unit (2), or Storage unit, the amount of charge handled by the horizontal transfer register can be reduced. It is possible to increase the signal charges and improve the transfer of signal charges in the horizontal transfer register.

It is a typical top view for demonstrating the CCD solid-state imaging device (1) which is an example of the solid-state imaging device to which this invention is applied. It is a schematic diagram for demonstrating the horizontal transfer register | resistor of CCD solid-state imaging device (1) to which this invention is applied. It is a figure for demonstrating each transfer clock. It is a schematic diagram (1) for demonstrating the horizontal transfer of a signal charge. It is a schematic diagram (2) for demonstrating the horizontal transfer of a signal charge. A horizontal transfer register of a CCD solid-state imaging device (2) which is another example of the solid-state imaging device to which the present invention is applied and a CCD solid-state imaging device (3) which is still another example of the solid-state imaging device to which the present invention is applied will be described. It is a schematic diagram for doing. It is a typical top view for demonstrating the conventional CCD solid-state imaging device. It is the figure for demonstrating the potential of the horizontal transfer register of the conventional CCD solid-state imaging device, and the figure for demonstrating each transfer clock. It is a schematic diagram for demonstrating the handling charge amount of a charge transfer part, and transfer of a signal charge.

Explanation of symbols

1 Photodetector 3 Vertical transfer register 4 Horizontal transfer register 5 Bias circuit

Claims (5)

In a charge transfer unit that has a plurality of charge storage units that store signal charges and transfers signal charges between the charge storage units by changing the potential of the charge storage units.
The charge storage unit includes a first region and a second region adjacent to the signal charge transfer direction side of the first region,
The charge transfer unit, wherein the falling timing of the transfer clock applied to the first region is earlier than the falling timing of the transfer clock applied to the second region. The second region includes a third region and a fourth region adjacent to the third region in the signal charge transfer direction, and the third region to the fourth region by impurity implantation. The charge transfer unit according to claim 1, wherein a potential difference is formed toward The second region includes a third region and a fourth region adjacent to the third region in the direction of signal charge transfer, from the third region toward the fourth region. The charge transfer unit according to claim 1, wherein a transfer electric field is formed. The charge transfer unit according to claim 1, wherein the rising timing of the transfer clock applied to the first region is substantially the same as the rising timing of the transfer clock applied to the second region. . An imaging unit;
A charge transfer unit that transfers the signal charge transferred from the imaging unit,
In the solid-state imaging device, the charge transfer unit includes a plurality of charge storage units that store signal charges, and transfers signal charges between the charge storage units by changing a potential of the charge storage unit.
The charge storage unit includes a first region and a second region adjacent to the signal charge transfer direction side of the first region,
The solid-state imaging device, wherein the falling timing of the transfer clock applied to the first region is earlier than the falling timing of the transfer clock applied to the second region.

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