JP2014022689A - Pixel structure for rear surface irradiation type solid imaging device, rear surface irradiation type solid imaging device, driver, imaging apparatus and driving method of pixel structure for rear surface irradiation type solid imaging device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a pixel structure for a rear surface irradiation type solid imaging device in which a speed of an electronic shutter can be increased.SOLUTION: Each of pixel parts in a pixel structure for a rear surface irradiation type solid imaging device 20 comprises: charge collection gates 21 and 22 for collecting signal charges; a VCCD 25 for transferring the signal charges to an output side; and an overflow drain gate 23 and a drain 24 for discarding the signal charges. The charge collection gate 22 includes an electrode of which the area is smaller than an area subtracting a total area summing up areas of electrodes of the charge collection gate 21, the overflow drain gate 23, the drain 24 and the VCCD 25 from areas of pixels, and signal charges collected by the charge collection gate 21 are outputted to the VCCD 25 during a first term, and outputted to the overflow drain gate 23 and the drain 24 during a second term following the first term.

Description

  The present invention relates to a pixel structure of a back-illuminated solid-state image sensor, a back-illuminated solid-state image sensor, a driving device and an imaging device, and a driving method of a pixel structure of a back-illuminated solid-state image sensor.

  Solid-state imaging devices are used in photographing devices such as digital still cameras and digital video cameras. Up to now, solid-state imaging devices have been improved in image quality by miniaturizing pixels and increasing the number of pixels, but miniaturization of pixels also causes a decrease in sensitivity and saturation charge. Therefore, attention is paid to a back-illuminated type instead of the front-side illuminated type as a structure capable of increasing sensitivity even if the pixels are miniaturized, and a manufacturing method has been invented (Patent Document 1). In the back-illuminated solid-state imaging device, a photoelectric conversion unit of each pixel is provided on the back side of the device, and an A / D converter, a signal storage unit, and the like are provided on the surface side of the device.

  Incidentally, some surface-illuminated solid-state imaging devices have a vertical overflow drain structure. If this structure is used to sweep out a surplus of signal charges, blooming can be suppressed. In addition, this type of surface-illuminated solid-state imaging device realizes an electronic shutter function by capturing signal charges during a desired light receiving period and discarding other signal charges via the vertical overflow drain.

  However, with the same configuration as this, the back-illuminated solid-state imaging device cannot have an electronic shutter function. The reason will be described below.

  FIG. 24 is a schematic cross-sectional view of a vertical overflow drain in a surface irradiation type photogate. In the surface irradiation type photogate, an overflow drain structure is realized by using an overflow drain barrier at the bottom of the photogate and an n-type substrate.

  FIG. 25 is a potential distribution diagram in the depth direction of the vertical overflow drain of the surface irradiation type photogate. Here, the horizontal axis indicates the depth from the surface in the cross section A1-A2 shown in FIG. 24, and the vertical axis indicates the potential.

  In the surface irradiation type, charges are accumulated in the charge accumulation unit by applying a voltage VH to the gate electrode during accumulation, and in the charge accumulation unit by applying a voltage VL to the gate electrode during application of the reset voltage. The accumulated charge is thrown away to the substrate.

  However, the back-illuminated type has a structure in which light is incident from the substrate side and charges are collected on the front side. Therefore, the substrate cannot be used as a drain, and a front-illuminated vertical overflow drain structure cannot be realized.

  Therefore, a structure for realizing an overflow drain has also been studied in the backside illumination type solid-state imaging device, and the drain is configured on the back side (Patent Document 2), and the drain is configured on the front side (Patent Document 3). ~ 5) are known.

  Patent Document 2 describes a structure having a transparent electrode on the back surface side and sweeping out charges on the back surface side, and this structure results in a vertical overflow drain structure, which enables multiple pixels and a high dynamic range. It is described that it enables an electronic shutter that sweeps away charges on the side.

  In Patent Document 3, a plurality of photosensor portions are provided on the back side of a semiconductor substrate, and a vertical transfer register and an overflow drain portion are provided in parallel on the front side for each region corresponding to each pixel column of the photosensor portion. The electronic shutter function can be easily realized by using the overflow drain portion.

Patent Document 4 describes a structure in which a p layer, an n layer, a p ⁺ layer, an n ⁺ layer, and an electrode are sequentially formed from the back side where light enters, and the barrier formed in the p ⁺ layer is eliminated. It is described that the electric charge in the potential well formed in the photoelectric conversion region can be reset by applying a certain voltage to the electrode, and thus an electronic shutter can be realized using this.

Patent Document 5 describes an improved type of that described in Patent Document 4, and the potential formed in the photoelectric conversion region by forming the n ⁺ layer at a position overlapping the maximum potential point of the n layer in plan view. It is described that the electric shutter function can be sufficiently realized because the charge in the well can be completely reset.

Japanese Patent Laid-Open No. 9-331052 JP 2001-257337 A JP 2003-209245 A JP 2008-103368 A JP 2008-103668 A

  However, the back-illuminated solid-state imaging devices described in Patent Documents 2 to 5 are intended to realize an electronic shutter function with an overflow drain structure, but are not considered for speeding up the electronic shutter, and have high image quality. Improvement was difficult.

  In view of the circumstances described above, the present invention provides a pixel structure of a back-illuminated solid-state image sensor, a back-illuminated solid-state image sensor, a driving device and an imaging device, and a back-illuminated solid-state image sensor capable of increasing the speed of an electronic shutter. An object is to provide a driving method of a pixel structure.

  The pixel structure of the back-illuminated solid-state imaging device according to the present invention has a plurality of pixel portions arranged in a two-dimensional array on one surface side of a semiconductor substrate, and subject light from the other surface side of the semiconductor substrate. The pixel structure of the back-illuminated solid-state imaging device that is incident on the pixel portion, wherein each of the pixel units is connected to the signal charge collecting unit that collects signal charges generated by the subject light, and the signal charge is connected to the signal charge collecting unit. A signal charge output unit that outputs the signal charge, a transfer unit that is connected to the signal charge output unit and transfers the input signal charge to the output side, and a signal charge discard unit that is connected to the signal charge output unit and discards the input signal charge And the signal charge output unit has an area smaller than an area obtained by subtracting the total area of the electrodes of the signal charge collection unit, the transfer unit, and the signal charge discard unit from the area of the pixel. Power of The signal charge collected by the signal charge collecting unit is output to the transfer unit in a first period, and is output to the signal charge discarding unit in a second period following the first period. It has the composition which is.

  With this configuration, in the pixel structure of the backside illumination type solid-state imaging device of the present invention, the signal charge output unit outputs the signal charge collected by the signal charge collection unit to the transfer unit in the first period, and the first period Since the signal charge is output to the signal charge discarding unit in the second period subsequent to, the electronic shutter function is provided.

  In addition, with this configuration, the pixel structure of the back-illuminated solid-state imaging device of the present invention has an RC time constant by making the electrode area of the signal charge output unit, which is an electrode that controls the response of the electronic shutter, narrower than the conventional one. Since it can be made smaller, the response speed to the input signal can be increased.

  Therefore, the pixel structure of the backside illumination type solid-state imaging device of the present invention can increase the speed of the electronic shutter.

  Further, the pixel structure of the back-illuminated solid-state imaging device of the present invention is connected to the signal charge output unit between the signal charge output unit and the transfer unit, and sequentially accumulates the signal charges in the transfer unit. A plurality of signal charge accumulation and transfer units for transferring, and the signal charge output unit has an area of each electrode of the signal charge collection unit, the transfer unit, the signal charge discarding unit, and the plurality of signal charge accumulation and transfer units. An electrode having an area smaller than an area obtained by subtracting a total area of the pixels from the area of the pixel, and the signal charge collected by the signal charge collection unit is transmitted to the plurality of signal charge accumulation and transfer units in the first period. Is output to the transfer unit via the signal, and is output to the signal charge discarding unit in the second period.

  With this configuration, the pixel structure of the back-illuminated solid-state imaging device according to the present invention can increase the speed of the electronic shutter even in the case where a plurality of signal charge accumulation and transfer units are provided between the signal charge output unit and the transfer unit. be able to.

  The backside illumination type solid-state imaging device of the present invention has a configuration including a pixel structure of the backside illumination type solid-state imaging device and a backside electrode provided on the other surface side.

  With this configuration, the back-illuminated solid-state image sensor of the present invention has the pixel structure of the back-illuminated solid-state image sensor, so that the speed of the electronic shutter can be increased.

  The driving device according to the present invention applies a back electrode voltage applying means for applying a voltage for driving the back electrode, and a voltage for collecting the signal charge generated by the subject light in the signal charge collecting unit to the signal charge collecting unit. A signal charge collecting voltage applying means for performing, a signal charge output voltage applying means for applying a voltage for transferring the signal charge collected by the signal charge collecting section to the signal charge output section, and the signal charge. Transfer voltage applying means for applying a voltage for transferring the signal charge input from the output section toward the output side, and a discard voltage application for applying a voltage for discarding the signal charge input from the signal charge output section And means.

  With this configuration, the driving device of the present invention can increase the speed of the electronic shutter with respect to the back-illuminated solid-state image sensor having the pixel structure of the back-illuminated solid-state image sensor.

  An imaging apparatus according to the present invention includes a back-illuminated solid-state image sensor, a driving device, and a signal processing circuit that processes signals from a plurality of pixel units of the back-illuminated solid-state image sensor and outputs video signals. It has a configuration.

  With this configuration, the imaging apparatus of the present invention includes the backside illumination type solid-state imaging device having the pixel structure of the backside illumination type solid-state imaging device, so that the speed of the electronic shutter can be increased.

  The driving method of the pixel structure of the back-illuminated solid-state imaging device according to the present invention has a plurality of pixel portions arranged in a two-dimensional array on one surface side of the semiconductor substrate, and the other surface side of the semiconductor substrate. Driving method of a pixel structure of a back-illuminated solid-state imaging device that makes subject light incident thereon, wherein each pixel unit includes a signal charge collecting unit that collects signal charges generated by the subject light, and the signal charge collecting unit A signal charge output unit connected to the signal charge output unit, a transfer unit connected to the signal charge output unit for transferring the input signal charge to the output side, and a signal charge connected to the signal charge output unit A signal charge discarding unit to be discarded, and the signal charge output unit subtracts the total area of the electrodes of the signal charge collecting unit, the transfer unit, and the signal charge discarding unit from the area of the pixel. Area The signal charge output unit outputs the signal charge collected by the signal charge collection unit to the transfer unit in a first period; and the signal charge output unit includes: And a step of outputting to the signal charge discarding unit in a second period following the first period.

  With this configuration, the back-illuminated solid-state imaging device pixel structure driving method according to the present invention has a function of an electronic shutter and can increase the response speed to an input signal. Thus, the speed of the electronic shutter can be increased.

  The present invention relates to a pixel structure of a back-illuminated solid-state image pickup device, an effect of increasing the speed of an electronic shutter, a back-illuminated solid-state image sensor, a driving device and an image pickup device, and a pixel structure of a back-illuminated solid-state image sensor. The driving method can be provided.

It is the figure which showed typically the structure of the drive device which concerns on this invention, and the structure of the surface side of a back irradiation type solid-state image sensor. It is a cross-sectional schematic diagram along the VCCD from the charge collection gate of the backside illumination type solid-state imaging device according to the present invention. It is a cross-sectional schematic diagram along the drain from the charge collection gate of the backside illumination type solid-state imaging device according to the present invention. It is a schematic diagram of the drive voltage waveform for operating the electronic shutter function of the backside illumination type solid-state imaging device according to the present invention (time aperture ratio of electronic shutter 1/1). It is a schematic diagram of the drive voltage waveform for operating the electronic shutter function of the backside illumination type solid-state imaging device according to the present invention (time aperture ratio of electronic shutter is 1/2). It is a schematic diagram of the drive voltage waveform for operating the electronic shutter function of the backside illumination type solid-state imaging device according to the present invention (time aperture ratio of electronic shutter is ¼). It is a schematic diagram of the drive voltage waveform for operating the electronic shutter function of the backside illumination type solid-state imaging device according to the present invention (temporal aperture ratio 1/8 of the electronic shutter). FIG. 7 is a schematic cross-sectional potential diagram during periods T1, T2, T3, and T4 in FIG. 6 in the backside illumination type solid-state imaging device according to the present invention. In the conventional front-illuminated solid-state image sensor, the conventional back-illuminated solid-state image sensor, and the back-illuminated solid-state image sensor according to the present invention, the ratio of the area occupied in one pixel by the electrode that controls the response of the electronic shutter It is a figure which shows an example of wiring resistance ratio. It is a figure which shows the conventional surface irradiation type solid-state image sensor. It is a figure which shows the response characteristic of the voltage applied to the electrode which governs the response of an electronic shutter in the conventional front-illuminated solid-state image sensor, the conventional back-illuminated solid-state image sensor, and the back-illuminated solid-state image sensor according to the present invention. . It is the schematic diagram which showed the conventional surface irradiation type pixel periphery recording solid-state image sensor. FIG. 10 is a schematic plan view of one pixel in a conventional surface irradiation type pixel peripheral recording type solid-state imaging device. It is a figure which shows the response characteristic of the photogate electrode which is an electrode which manages the response of an electronic shutter in the pixel of the conventional surface irradiation type pixel periphery recording solid-state image sensor. FIG. 2 is a schematic plan view of a front surface side of a backside illuminated pixel peripheral recording solid-state image sensor according to the first embodiment and a configuration diagram of a driving device. It is a surface side plane schematic diagram of a pixel of a back irradiation type pixel peripheral recording solid-state image sensor in a first embodiment. It is a figure which shows the response characteristic of the electric charge collection gate electrode which is an electrode which manages the response of an electronic shutter in the pixel of the back surface irradiation type pixel periphery recording solid-state image sensor in 1st Embodiment. It is a drive voltage waveform schematic diagram for operating the electronic shutter function of the backside illumination type pixel peripheral recording solid-state imaging device in the first embodiment (time aperture ratio of electronic shutter 1/1). It is a drive voltage waveform schematic diagram for operating the electronic shutter function of the backside illumination type pixel peripheral recording solid-state imaging device in the first embodiment (the time aperture ratio of the electronic shutter is ½). It is a drive voltage waveform schematic diagram for operating the electronic shutter function of the backside illumination type pixel peripheral recording solid-state imaging device in the first embodiment (time aperture ratio of electronic shutter is ¼). It is a drive voltage waveform schematic diagram for operating the electronic shutter function of the backside illuminated pixel peripheral recording type solid-state imaging device in the first embodiment (time aperture ratio of electronic shutter is 1/8). FIG. 21 is a schematic cross-sectional potential diagram during periods T1, T2, T3, and T4 in FIG. 20 in the backside illuminated pixel peripheral recording solid-state imaging device according to the first embodiment. It is a block block diagram of the imaging device in 2nd Embodiment. It is a cross-sectional schematic diagram of the vertical overflow drain in the conventional surface irradiation type photogate. It is a potential distribution diagram in the depth direction of a vertical overflow drain of a conventional surface irradiation type photogate.

  First, before describing an embodiment of the present invention, a basic configuration of a pixel structure of a back-illuminated solid-state imaging device according to the present invention will be described.

  FIG. 1 is a diagram schematically showing the configuration of the driving device 10 according to the present invention and the configuration of the front side of the backside illumination type solid-state imaging device 20.

  The driving device 10 includes a back electrode voltage applying unit 11 that applies a driving voltage φBS, a gate electrode voltage applying unit 12 that applies a driving voltage φG1, and a gate electrode that applies a driving voltage φG2 to the backside illumination solid-state imaging device 20. A voltage application unit 13, a discard electrode voltage application unit 14 that applies the drive voltage φODG, a drain electrode voltage application unit 15 that applies the drive voltage φDRA, a vertical transfer voltage application unit 16 that applies the drive voltage φV, and a drive voltage φH A horizontal transfer voltage application unit 17 is provided.

  Here, the back surface electrode voltage application part 11 comprises the back surface electrode voltage application means which concerns on this invention. The gate electrode voltage application unit 12 constitutes signal charge collection voltage application means according to the present invention. The gate electrode voltage application unit 13 constitutes signal charge output voltage application means according to the present invention. The discard electrode voltage application unit 14 constitutes a discard voltage application unit according to the present invention. The drain electrode voltage application unit 15 constitutes a waste voltage application unit according to the present invention. The vertical transfer voltage application unit 16 constitutes transfer voltage application means according to the present invention.

  The back-illuminated solid-state imaging device 20 includes charge collection gates 21 and 22, an overflow drain gate 23, a drain 24, a VCCD (vertical transfer CCD) 25, an HCCD (horizontal transfer CCD) 26, and an amplifier 27. The area shown in an enlarged view in the figure is an area of one pixel.

  Here, the charge collection gate 21 constitutes a signal charge collection unit according to the present invention. The charge collection gate 22 constitutes a signal charge output unit according to the present invention. The overflow drain gate 23 and the drain 24 constitute a signal charge discarding unit according to the present invention.

  As illustrated, the pixel structure of the back-illuminated solid-state imaging device 20 includes a charge collection gate electrode G1 that is an electrode of the charge collection gate 21, a charge collection gate electrode G2 that is an electrode of the charge collection gate 22, and an overflow drain gate 23. It includes an overflow drain gate electrode ODG which is an electrode, a drain electrode DRA which is an electrode of the drain 24, and VCCD electrodes V1 to V4 which are electrodes of the VCCD 25.

  Here, the area of the charge collection gate electrode G2 is the sum of the area of the charge collection gate electrode G1, the area of the overflow drain gate electrode ODG, the area of the drain electrode DRA, and the areas of the VCCD electrodes V1 to V4. It is smaller than the area obtained by subtracting the area from the area of the pixel.

  The charge collection gate electrode G1 receives the drive voltage φG1 from the gate electrode voltage application unit 12. The charge collection gate electrode G2 receives the drive voltage φG2 from the gate electrode voltage application unit 13. The overflow drain gate electrode ODG receives the drive voltage φODG from the discard electrode voltage application unit 14. The drain electrode DRA receives the drive voltage φDRA from the drain electrode voltage application unit 15.

  The VCCD electrodes V1 to V4 are driven by four-phase clock drive voltages φV (φV1 to 4) output from the vertical transfer voltage application unit 16 and having different phases. For example, drive voltages φV1, φV2, φV3, and φV4 are applied to the VCCD electrodes V1, V2, V3, and V4, respectively. By applying the four-phase clocks φV1 to φ4, the VCCD 25 sequentially transfers the signal charges output from the charge collection gate 22 to the HCCD 26.

  The VCCD 25 is connected to the HCCD 26 common to all columns. The HCCD 26 receives the drive voltage φH from the horizontal transfer voltage application unit 17 and is connected to the amplifier 27. The amplifier 27 amplifies the signal charge and outputs it as an external signal.

  Since FIG. 1 shows the configuration of the front side of the backside illumination type solid-state imaging device 20, the photoelectric conversion unit on the back side is not shown, but the signal charge generated in the photoelectric conversion unit is the charge on the front side. They gather at the collection gate 21 and are sent to the charge collection gate 22. The outlet of the charge collection gate 22 is branched into two, and is divided into a path connected to the drain 24 for each pixel through the overflow drain gate 23 and a path connected to the VCCD 25 for each pixel.

  FIG. 2 is a schematic cross-sectional view along the VCCD 25 from the charge collection gate 21 of the back-illuminated solid-state imaging device 20.

  The back-illuminated solid-state imaging device 20 has a front surface 41 of a semiconductor substrate on the surface side on which a plurality of pixel portions (see FIG. 1) are arranged and formed in a two-dimensional array, and a back surface 42 on which light is incident. Here, the front surface 41 constitutes one surface according to the present invention, and the back surface 42 constitutes another surface according to the present invention.

Further, the backside illumination type solid-state imaging device 20 has a p ⁺ semiconductor layer 51 (back electrode BS), a p ⁻ semiconductor layer 52 (photoelectric conversion unit), and an n ⁻ semiconductor layer 53 (charge collecting layer) from the back surface 42 side of the semiconductor substrate. ) Are sequentially formed. Each of these layers is formed by an epitaxial growth method. Here, the p ⁺ semiconductor layer 51 receives the drive voltage φBS from the back electrode voltage application unit 11 of the drive device 10 (see FIG. 1). This p ⁺ semiconductor layer 51 constitutes a back electrode according to the present invention.

Further, the back-illuminated solid-state imaging device 20 includes a p ⁻ semiconductor layer (p well) 54, an n ⁺ semiconductor layer 55, an oxide film 56, and a wiring layer 57 sequentially formed on the upper surface of the n ⁻ semiconductor layer 53. .

FIG. 3 is a schematic cross-sectional view from the charge collection gate 21 to the drain 24 of the back-illuminated solid-state imaging device 20, and the same components as those in FIG. As illustrated, a charge collection gate electrode G1, a charge collection gate electrode G2, an overflow drain gate electrode ODG, and a drain electrode DRA are formed. The drain electrode DRA is connected to the transfer path of the n ⁻ semiconductor layer 53 and the wiring layer 57.

  In addition, as a manufacturing method of the back irradiation type solid-state image sensor 20, it describes in Unexamined-Japanese-Patent No. 2010-283232, for example, and since it is well-known, description is abbreviate | omitted.

  In the back-illuminated solid-state image sensor 20 described above, the electronic shutter function of the back-illuminated solid-state image sensor 20 is achieved by the relationship of voltage application to the three electrodes of the charge collection gate electrode G2, the overflow drain gate electrode ODG, and the VCCD electrode V1. It can be operated. Hereinafter, it demonstrates concretely, referring drawings.

  4 to 7 are schematic diagrams of drive voltage waveforms for operating the electronic shutter function of the back-illuminated solid-state imaging device 20. 4 is a time aperture ratio 1/1 (total time exposure) of the electronic shutter, FIG. 5 is a time aperture ratio 1/2 of the electronic shutter, FIG. 6 is a time aperture ratio 1/4 of the electronic shutter, and FIG. The schematic diagram of the drive voltage waveform in time aperture ratio 1/8 is shown.

As shown in FIGS. 4 to 7, the driving device 10 applies a DC voltage having a predetermined voltage amplitude to the back electrode BS as the driving voltage φBS, and charges the DC voltage higher than the driving voltage φBS as the driving voltage φG1. Applied to the collection gate electrode G1. As a result, a DC bias is applied between the back surface electrode BS and the charge collection gate electrode G1, and the depletion layer is expanded, and the signal charge generated in the p ⁻ semiconductor layer 52 which is the photoelectric conversion unit is the charge collection gate electrode. Gather in G1 at high speed.

  Further, as shown in FIGS. 4 to 7, the driving device 10 outputs clocks of φG2, φV1, and φV2 as driving voltages to the charge collection gate electrode G2, the VCCD electrode V1, and the electrode V2, respectively. These clocks have a high level period of ½ of one cycle and a low level period of ½ of one cycle, and the phases are different from each other by ¼ cycle. Of these signal charges collected by the charge collection gate 21 by these drive voltages, the signal charges in the period ("opening period of the electronic shutter") indicated as "used" in the figure are transferred to the VCCD 25 via the charge collection gate 22. Sequentially transferred. The drive voltage waveforms of the VCCD electrode V3 and the electrode V4 are not shown.

  Further, as shown in FIG. 4, the driving device 10 applies a DC voltage having a predetermined voltage amplitude as the driving voltage φODG to the overflow drain gate electrode ODG at a time aperture ratio of 1/1 of the electronic shutter. A DC voltage higher than the drive voltage φODG is applied to the drain electrode DRA as φDRA.

  On the other hand, as shown in FIGS. 5 to 7, the driving device 10 generates a clock having predetermined voltages VL and VH as the driving voltage φODG except for the time aperture ratio 1/1 of the electronic shutter, and overflow drain gate electrode ODG. And a DC voltage higher than the voltage VH of the drive voltage φODG is applied to the drain electrode DRA as the drive voltage φDRA. Of the signal charges collected by the charge collection gate 21 due to this drive voltage, the signal charges during the period indicated as “discard” in the figure (the closing period of the electronic shutter) are applied to the charge collection gate 22 and the overflow drain gate electrode ODG. Via the drain electrode DRA.

  Next, in order to explain a specific operation in the drive voltage waveforms of FIGS. 4 to 7, the case of the time aperture ratio 1/4 of the electronic shutter shown in FIG. 6 is taken up, and a cross-sectional potential schematic diagram thereof is shown in FIG. Show. FIG. 8 is a schematic cross-sectional potential diagram in periods T1, T2, T3, and T4 in FIG. 6, the path of BS-G1-G2-V1-V2-V3 is indicated by a solid line, and the path of G2-ODG-DRA is It is represented by a dotted line.

  In the bias relationship of the period T1, the signal charge generated in the depletion layer near the back electrode BS moves to the VCCD electrode V1 through the charge collection gates 21 and 22, and remains there.

  In the bias relationship of the period T2, the signal charge generated in the depletion layer near the back electrode BS moves to the charge collection gate electrode G1 and remains there. In addition, the signal charge remaining at the VCCD electrode V1 in the period T1 remains at the VCCD electrodes V1 and V2.

  In the bias relationship of the period T3, the signal charge generated in the depletion layer near the back electrode BS moves to the charge collection gate electrode G1 and remains there. In addition, the signal charge remaining at the VCCD electrode V1 and the electrode V2 in the period T2 is transferred to the VCCD electrode V2 and the electrode V3.

  In the bias relationship in the period T4, the signal charge generated in the depletion layer near the back electrode BS and the signal charge remaining in the charge collection gate electrode G1 in the periods T2 and T3 are drained through the path of G1-G2-ODG-DRA. Discarded at 24.

  In summary, in the operation from the period T1 to the period T4, the signal charges generated in the period T1 are transferred to the path V1-V2-V3 and transferred to the outside of the back-illuminated solid-state imaging device 20, but the periods T2, T3 The signal charges generated at T4 are discarded to the drain electrode DRA through the path of G2-ODG-DRA. That is, the time aperture ratio of the electronic shutter in this case is ¼.

  For example, in one period shown in FIG. 6, the period T1 corresponds to the first period according to the present invention, and the periods T2 to T4 correspond to the second period according to the present invention. Here, if one cycle is interpreted as the periods T2, T3, T4, and T1, one cycle is a period in which a “use” period follows a “discard” period.

  FIG. 9 shows a conventional front-illuminated solid-state image sensor, a conventional back-illuminated solid-state image sensor, and an electrode that controls the response of the electronic shutter in the back-illuminated solid-state image sensor 20 according to the present embodiment. Shows an example of the area ratio and the wiring resistance ratio.

  Here, the conventional surface irradiation type solid-state imaging device has a configuration shown in FIG. That is, the conventional surface irradiation type solid-state imaging device 30 includes a photogate 31 that generates signal charges, a transfer gate 32 that functions as an analog switch, a VCCD 33 that transfers signal charges in the vertical direction, and an HCCD 34 that transfers signal charges in the horizontal direction. The amplifier 35 amplifies the signal charge.

  Further, as a conventional backside illumination type solid-state imaging device, for example, the one shown in FIG.

  As shown in FIG. 9, first, in the example of the conventional surface irradiation type solid-state imaging device (see FIG. 10), the electrode that controls the response of the electronic shutter is the photogate 31, and the area occupied by this electrode in one pixel. The ratio is 50%. The wiring resistance ratio is 100% in the case of this conventional surface irradiation type solid-state imaging device.

  Next, in the conventional back-illuminated solid-state imaging device (see FIG. 3 of Patent Document 3), the electrode that controls the response of the electronic shutter is the overflow drain portion, and the ratio of the area occupied by this electrode in one pixel is 50. %. In the back irradiation type, since the photoelectric conversion part is on the back surface, the area that was the photoelectric conversion part in the front side irradiation type can also be used as wiring. Therefore, the conventional back-illuminated solid-state imaging device can reduce the wiring resistance to one half and the wiring resistance ratio to 50% compared to the conventional front-illuminated solid-state imaging device.

  Next, in the back-illuminated solid-state imaging device 20 (see FIG. 1) according to the present invention, the electrode that controls the response of the electronic shutter is the charge collection gate electrode G2, and the ratio of the area occupied by this electrode in one pixel is 6%. Since the back-illuminated solid-state image sensor 20 is a back-illuminated type, the wiring resistance ratio can be reduced to 50% compared to the conventional front-illuminated solid-state image sensor.

  In the pixel structure (see FIGS. 1 to 3) of the back-illuminated solid-state imaging device 20 according to the present invention, when the drive waveforms shown in FIGS. 4 to 7 are applied, the electronic shutter can be operated as described above. . Further, by operating this electronic shutter, as shown below, the back-illuminated solid-state image sensor 20 is more than the conventional front-illuminated solid-state image sensor or conventional back-illuminated solid-state image sensor shown in FIG. It is possible to respond at high speed.

  FIG. 11 is a diagram showing the response characteristics of the voltage applied to the electrode that controls the response of the electronic shutter. The ratio of the area occupied by the electrode of the electronic shutter in one pixel and the wiring resistance ratio shown in FIG. 5 is a graph comparing the values of the capacitance C and the resistance R as relative values. In FIG. 11, RC on the horizontal axis indicates an RC time constant that is the product of the resistance R and the capacitance C.

  In FIG. 11, the response characteristics indicated by dotted lines are the response characteristics when R = 1 and C = 0.5, and correspond to the response characteristics of the conventional surface irradiation type solid-state imaging device. The response characteristic indicated by the alternate long and short dash line is a case where R = 0.5 and C = 0.5, and corresponds to the response characteristic of a conventional back-illuminated solid-state imaging device. The response characteristics indicated by the solid line are for R = 0.5 and C = 0.06, and correspond to the response characteristics of the back-illuminated solid-state imaging device 20 in the present embodiment.

  As shown in FIG. 11, when R = 0.5 and C = 0.06, the electronic shutter responds about 10 times faster than when R = 1 and C = 0.5. Further, as is apparent from the configuration shown in FIG. 1 and the drive waveforms shown in FIGS. 4 to 7, this electronic shutter is a so-called global shutter that can perform pixel reset, exposure, and signal readout simultaneously. is there.

(First embodiment)
Next, an example in which the driving device according to the present invention is applied to a back-illuminated pixel peripheral recording solid-state imaging device will be described.

  Here, the pixel peripheral recording type solid-state imaging device will be briefly described. The pixel peripheral recording type solid-state imaging device includes a front surface irradiation type and a back surface irradiation type. FIG. 12 is a schematic diagram showing a front-illuminated pixel peripheral recording solid-state imaging device.

  As shown in FIG. 12, the front-illuminated pixel peripheral recording type solid-state imaging device 60 includes a photogate 61, a CCD memory 62, a junction 63, a drain 64, a VCCD 65, an HCCD 66, and an amplifier 67. An oblique linear CCD memory 62 for sequentially recording signal charges is connected directly to the photogate 61 for each pixel. The signal charge recorded in the CCD memory 62 is transferred to the VCCD 65 via the junction 63 and the drain 64. In addition, the area | region of pixel width x pixel length shown with the dotted line in the figure is an area | region of 1 pixel.

  FIG. 13 is a schematic plan view of one pixel in the surface irradiation type pixel peripheral recording type solid-state imaging device 60. The electrode of the photogate 61 has a two-layer configuration of a photogate electrode PG1 and a photogate electrode PG2. The CCD memory 62 includes CCD memory electrodes M1 to M4 and is operated by four-phase driving. The VCCD 65 is a four-phase drive of a CCD memory electrode M1, a VCCD electrode V2, a CCD memory electrode M3, and a VCCD electrode V4. In this configuration, the two electrodes constituting the electronic shutter function are the photogate electrode PG1 and the photogate electrode PG2, but the electrode that controls the response of the electronic shutter is the photogate electrode PG2.

  FIG. 14 shows the response characteristics of the photogate electrode PG2, which is the electrode that controls the response of the electronic shutter in the pixels of the front-illuminated pixel peripheral recording solid-state imaging device 60. The applied rectangular input waveform (dotted line) has a period of 1000 nanoseconds, a duty ratio of 50%, VH = 12V, and VL = 0V. The response waveform (solid line) rises to 11.95 V in 500 nanoseconds after applying the rectangular wave. This indicates that an electronic shutter to which a sufficient applied voltage is applied needs a pulse width of about 500 nanoseconds.

  Next, FIG. 15 shows a schematic plan view of the front surface side of the back-illuminated pixel peripheral recording solid-state image sensor 70 and the configuration diagram of the driving device 10 in this embodiment.

  The back-illuminated pixel peripheral recording solid-state imaging device 70 includes charge collection gates 71 and 72, an overflow drain gate 73, an overwrite gate 74, a drain 75, a CCD memory 76, a junction 77, a VCCD 78, an HCCD 79, and an amplifier 80. Yes. An area of pixel width × pixel length indicated by a dotted line in the drawing is an area of one pixel.

  Here, the back-illuminated pixel peripheral recording solid-state image sensor 70 constitutes a back-illuminated solid-state image sensor according to the present invention. The charge collection gate 71 constitutes a signal charge collection unit according to the present invention. The charge collection gate 72 constitutes a signal charge output unit according to the present invention. The overflow drain gate 73 and the drain 75 constitute a signal charge discarding unit according to the present invention. The CCD memory 76 constitutes a plurality of signal charge accumulation and transfer units according to the present invention. The VCCD 78 constitutes a transfer unit according to the present invention.

  In FIG. 15, the configuration of the front side of the back-illuminated pixel peripheral recording solid-state imaging device 70 is shown, so the photoelectric conversion unit on the back side is not shown, but the signal charge generated in the photoelectric conversion unit is The charges are collected at the charge collection gate 71 on the surface side and sent to the charge collection gate 72. The outlet of the charge collection gate 72 is branched into two, and is divided into a path connected to the drain 75 for each pixel via the overflow drain gate 73 and a path connected to the CCD memory 76 in the oblique linear shape for each pixel.

  The CCD memory 76 is connected to a readout VCCD 78 common to one column via a junction 77. The junction 77 is connected to the drain 75 via the overwrite gate 74. The VCCD 78 is connected to the HCCD 79 common to all columns. The HCCD 79 is connected to an amplifier 80 that amplifies the signal charge and outputs it as an external signal.

  FIG. 16 is a schematic plan view of the front surface side of the pixel of the back-illuminated pixel peripheral recording solid-state image sensor 70. The pixel structure of the back-illuminated pixel peripheral recording solid-state imaging device 70 includes a charge collection gate electrode G1 that is an electrode of the charge collection gate 71, a charge collection gate electrode G2 that is an electrode of the charge collection gate 72, and an overflow drain gate 73. Overflow drain gate electrode ODG as an electrode, overwrite gate electrode OWG as an electrode of overwrite gate 74, drain electrode DRA as an electrode of drain 75, CCD memory electrodes M1 to M4 as electrodes of CCD memory 76, and electrodes of VCCD 78 It includes VCCD electrodes M1, V2, M3, V4.

  The CCD memory 76 is driven by a drive voltage φM (φM1 to 4) of a four-phase clock that is output from the accumulation transfer voltage application unit 18 and that has different phases. For example, drive voltages φM1, φM2, φM3, and φM4 are applied to the CCD memory electrodes M1, M2, M3, and M4, respectively. By applying the four-phase clocks φM1 to φ4, the CCD memory 76 sequentially accumulates the signal charges output from the charge collection gate 22 and sequentially transfers them to the VCCD 78.

  The back-illuminated pixel peripheral recording solid-state image sensor 70 has a configuration in which a CCD memory 76 is provided between the charge collection gate 22 and the VCCD 25 in the back-illuminated solid-state image sensor 20 shown in FIG. 2, V 1, V 2, V 3, and V 4 are M 2, M 3, M 4, and M 1 in the cross-sectional direction shown in FIG. 2, and the cross-sectional direction shown in FIG. Become.

  The final stage of the CCD memory 76 includes a path connected to the drain DRA via the junction electrode SW and the overwrite gate electrode OWG, and a path connected to the junction electrode SW, VCCD electrodes M1, V2, M3, and V4. The VCCD 78 is a four-phase drive of a CCD memory M1, a vertical transfer path V2, a CCD memory M3, and a vertical transfer path V4. In this configuration, there are three electrodes that constitute the electronic shutter function: the charge collection gate electrode G2, the overflow drain gate electrode ODG, and the CCD memory electrode M2. The electrode that controls the response of the electronic shutter is the charge collection gate electrode G2. is there.

  Here, the area of the charge collection gate electrode G2 includes the area of the charge collection gate electrode G1, the area of the overflow drain gate electrode ODG, the area of the drain electrode DRA, the areas of the CCD memory electrodes M1 to M4, and the VCCD electrode M1. , V2, M3, and V4 are smaller than the total area obtained by subtracting the total area from the pixel area.

  FIG. 17 shows the response characteristics of the charge collection gate electrode G2, which is the electrode that controls the response of the electronic shutter in the pixels of the back-illuminated pixel peripheral recording solid-state imaging device. This is a case where a rectangular wave having a period of 1000 nanoseconds, a duty ratio of 50%, VH = 12V, and VL = 0V is applied.

  As shown in FIG. 17, the applied rectangular input waveform (dotted line) and the response waveform (solid line) almost coincide. Further, as shown in the enlarged view of the rising portion, the time from when the rectangular wave is applied to when the response waveform rises is approximately 4 nanoseconds. This indicates that the response characteristic of the electronic shutter is very fast. In the back-illuminated pixel peripheral recording solid-state imaging device 70, the area of the charge collection gate electrode G2 that controls the response of the electronic shutter is smaller than the conventional one, and the reduction of the wiring resistance can be realized. A fast response was achieved.

  18 to 21 are drive voltage waveform schematic diagrams for operating the electronic shutter function of the back-illuminated pixel peripheral recording solid-state imaging device 70. FIG. 18 is a time aperture ratio 1/1 (total time exposure) of the electronic shutter, FIG. 19 is a time aperture ratio 1/2 of the electronic shutter, FIG. 20 is a time aperture ratio 1/4 of the electronic shutter, and FIG. The schematic diagram of the drive voltage waveform in time aperture ratio 1/8 is shown.

As shown in FIGS. 18 to 21, the driving device 10 in the present embodiment applies a DC voltage of −5V as the driving voltage φBS to the back electrode BS, and a DC voltage of 4V higher than the driving voltage φBS as the driving voltage φG1. Is applied to the charge collection gate electrode G1. As a result, a DC bias is applied between the back surface electrode BS and the charge collection gate electrode G1, and the depletion layer is expanded, and is generated in the p ^- semiconductor layer 52 (see FIGS. 2 and 3) which is a photoelectric conversion unit. The signal charges thus collected are collected at the charge collection gate electrode G1 at a high speed.

  Further, as shown in FIGS. 18 to 21, the driving device 10 outputs clocks of φG2, φM2, and φM3 as drive voltages to the charge collection gate electrode G2 and the CCD memory electrodes M2 and M3, respectively. These clocks have a high level period of ½ of one cycle and a low level period of ½ of one cycle, and the phases are different from each other by ¼ cycle. The drive voltage φG2 has a high level of 8V and a low level of −3.5V. The drive voltages φM2 and φM3 are both high level 12V and low level −3.5V. Of these signal charges collected by the charge collection gate 71 by these drive voltages, the signal charge during the period “used” in the figure (opening period of the electronic shutter) is transferred to the VCCD 78 via the charge collection gate 72. Sequentially transferred.

  Further, as shown in FIG. 18, the driving device 10 applies a DC voltage of −3.5 V to the overflow drain gate electrode ODG as the driving voltage φODG at a time aperture ratio 1/1 of the electronic shutter, and as the driving voltage φDRA. A DC voltage of 26 V higher than the drive voltage φODG is applied to the drain electrode DRA.

  On the other hand, as shown in FIGS. 19 to 21, the driving device 10 overflows the clock having the voltage VL = −3.5 V and the voltage VH = 15 V as the driving voltage φODG except for the time aperture ratio 1/1 of the electronic shutter. A DC voltage 26V higher than the voltage VH of the drive voltage φODG is applied to the drain electrode DRA as the drive voltage φDRA. Of the signal charges collected by the charge collection gate 71 by this drive voltage, the signal charges in the period (disclosed in the electronic shutter) indicated as “discard” in the figure pass through the charge collection gate 72 and the overflow drain gate 73. Then, it is discarded in the drain 75.

  Next, in order to explain specific operations in the drive voltage waveforms of FIGS. 18 to 21, the case of the electronic shutter shown in FIG. Show. FIG. 22 is a schematic diagram of cross-sectional potentials in the periods T1, T2, T3, and T4 in FIG. 20, the path of BS-G1-G2-M2-M3-M4 is represented by a solid line, and the path of G2-ODG-DRA is It is represented by a dotted line.

  In the bias relationship in the period T1, the signal charge generated in the depletion layer near the back electrode BS moves to the CCD memory electrode M2 through the charge collection gates 21 and 22, and stays there.

  In the bias relationship of the period T2, the signal charge generated in the depletion layer near the back electrode BS moves to the charge collection gate electrode G1 and remains there. In addition, the signal charge remaining at the CCD memory electrode M2 in the period T1 remains at the CCD memory electrode M2 and the CCD memory electrode M3.

  In the bias relationship of the period T3, the signal charge generated in the depletion layer near the back electrode BS moves to the charge collection gate electrode G1 and remains there. In addition, the signal charges remaining in the CCD memory electrode M2 and the CCD memory electrode M3 in the period T2 are transferred to the CCD memory electrode M3 and the CCD memory electrode M4.

  In the bias relationship in the period T4, the signal charge generated in the depletion layer near the back electrode BS and the signal charge remaining in the charge collection gate electrode G1 in the periods T2 and T3 are drained through the path of G1-G2-ODG-DRA. Discarded in the electrode DRA.

  In summary, in the operation from the period T1 to T4, the signal charge generated in the period T1 is transferred to the path M2-M3-M4 and transferred to the outside of the back-illuminated pixel peripheral recording solid-state imaging device 70. The signal charges generated in the periods T2, T3, and T4 are discarded to the drain electrode DRA through the G2-ODG-DRA path. That is, the time aperture ratio of the electronic shutter in this case is ¼.

  As described above, the back-illuminated pixel peripheral recording solid-state image sensor 70 according to the present embodiment operates as an electronic shutter, and is more effective than the conventional front-illuminated or back-illuminated solid-state image sensor. The speed can be increased. Therefore, the back-illuminated pixel peripheral recording solid-state image sensor 70 can improve the image quality of the image.

(Second Embodiment)
As shown in FIG. 23, the imaging device 90 according to the present embodiment includes a lens that collects subject light by incident light in addition to the driving device 10 and the back-illuminated pixel peripheral recording solid-state imaging device 70 shown in FIG. 91, an analog signal processing unit 92 for processing analog signals, an AD conversion unit 93 for converting analog signals into digital signals (hereinafter referred to as "AD conversion"), a digital signal processing unit 94 for processing digital signals, and an image A video signal memory 95 for storing signals, a video signal output unit 96 for outputting video signals, and a display unit 97 for displaying video are provided.

  Note that the configurations of the driving device 10 and the back-illuminated pixel peripheral recording type solid-state imaging device 70 have been described in the first embodiment, and will be omitted. Further, the analog signal processing unit 92 and the digital signal processing unit 94 constitute a signal processing circuit according to the present invention. Although not shown, the imaging device 90 includes a control unit including a CPU, a ROM, a RAM, and the like, and the control unit controls the entire device based on a program stored in the ROM. ing.

  Hereinafter, the operation of the imaging apparatus 90 will be described with reference to FIG.

  As described in the first embodiment, the driving device 10 drives the back-illuminated pixel peripheral recording solid-state imaging device 70 by applying each driving voltage. As a result, the signal charge of the optical signal that has passed through the lens 91 and entered the charge collection gate 21 is sequentially stored in the CCD memory 76.

  As a result, among the optical signals that have passed through the lens 91 and entered the charge collection gate 21, signal charges accumulated within a predetermined opening time of the electronic shutter are sequentially accumulated in the CCD memory 76.

  Thereafter, the driving device 10 drives to read out the signal charges accumulated in the CCD memory 76. That is, the driving device 10 applies the driving voltage φM of the read clock to the CCD memory 76, applies the driving voltage φV to the VCCD 78, and applies the driving voltage φH to the HCCD 79. As a result, the signal charge accumulated in the CCD memory 76 is output to the analog signal processing unit 92 via the amplifier 80.

  The analog signal processing unit 92 performs analog signal processing such as automatic gain adjustment and correlated double sampling processing on the analog signal output from the back-illuminated pixel peripheral recording solid-state imaging device 70, and the AD conversion unit 93. Output to.

  The AD conversion unit 93 converts the analog signal applied by the analog signal processing unit 92 into a digital signal and outputs the digital signal to the digital signal processing unit 94.

  The digital signal processing unit 94 performs digital signal processing such as rearrangement corresponding to frames at the time of shooting, interpolation processing, white balance correction, RGB / YC conversion processing, etc., on the video signal obtained from the AD conversion unit 93. And output to the video signal memory 95.

  The video signal memory 95 receives and stores the digital video signal from the digital signal processing unit 94. The video signal memory 95 can store a video signal of about several thousand frames, for example.

  The video signal output unit 96 converts the video signal from the video signal memory 95 into, for example, an HD-SDI (High Definition-Serial Digital Interface) standard video signal, and sends it to the display unit 97 and an external device (not shown) at a predetermined rate. To output. For example, in the case of a normal television rate, the video signal output unit 96 outputs a video signal at 30 frames / second.

  The display unit 97 is composed of, for example, a liquid crystal display, and displays an image based on the video signal output from the video signal output unit 96.

  As described above, the imaging device 90 according to the present embodiment includes the driving device 10 and the backside-illuminated pixel peripheral recording solid-state image sensor 70, so that a conventional front-side illumination type or back-side illumination type solid-state image sensor can be obtained. The speed of the electronic shutter can be increased as compared with the imaging device provided. Therefore, the imaging device 90 can improve the captured image quality.

  As described above, the pixel structure of the back-illuminated solid-state image sensor, the back-illuminated solid-state image sensor, the driving device and the imaging apparatus, and the driving method of the pixel structure of the back-illuminated solid-state image sensor according to the present invention are high-speed electronic shutters. The pixel structure of a back-illuminated solid-state image sensor used in a photographing apparatus such as a digital still camera or a digital video camera, a back-illuminated solid-state image sensor, a driving device and an imaging device, and back-surface illumination This is useful as a method for driving a pixel structure of a solid-state image sensor.

DESCRIPTION OF SYMBOLS 10 Drive apparatus 11 Back surface electrode voltage application part (back surface electrode voltage application means)
12 Gate electrode voltage application section (Signal charge collection voltage application means)
13 Gate electrode voltage application section (signal charge output voltage application means)
14 Waste electrode voltage application section (Discard voltage application means)
15 Drain electrode voltage application unit (waste voltage application means)
16 Vertical transfer voltage application unit (transfer voltage application means)
20 Back-illuminated solid-state imaging device 21 Charge collection gate (signal charge collection unit)
22 Charge collection gate (signal charge output part)
23 Overflow drain gate (signal charge disposal part)
24 Drain (Signal charge disposal part)
25 VCCD (transfer section)
41 Surface (one surface)
42 Back side (other side)
51 p ⁺ semiconductor layer (back electrode)
70 Back-illuminated pixel peripheral recording solid-state image sensor (back-illuminated solid-state image sensor)
71 Charge Collection Gate (Signal Charge Collection Unit)
72 Charge collection gate (signal charge output part)
73 Overflow drain gate (signal charge disposal part)
75 Drain (Signal charge disposal part)
76 CCD memory (multiple signal charge storage and transfer units)
78 VCCD (transfer section)
90 Imaging device 92 Analog signal processing unit (signal processing circuit)
94 Digital signal processor (signal processing circuit)

Claims (6)

A pixel structure of a back-illuminated solid-state imaging device that has a plurality of pixel portions arranged in a two-dimensional array on one surface side of a semiconductor substrate, and injects subject light from the other surface side of the semiconductor substrate. And
Each pixel portion is
A signal charge collecting unit for collecting signal charges generated by the subject light;
A signal charge output unit connected to the signal charge collection unit and outputting the signal charge;
A transfer unit connected to the signal charge output unit and transferring the input signal charge to the output side;
A signal charge discarding unit that is connected to the signal charge output unit and discards the input signal charge;
With
The signal charge output unit includes an electrode having an area smaller than an area obtained by subtracting a total area of the electrodes of the signal charge collection unit, the transfer unit, and the signal charge discard unit from the area of the pixel. The signal charge collected by the signal charge collecting unit is output to the transfer unit in a first period, and is output to the signal charge discarding unit in a second period following the first period. A pixel structure of a back-illuminated solid-state imaging device. A plurality of signal charge storage and transfer units connected to the signal charge output unit and sequentially storing the signal charges and transferring the signal charge to the transfer unit between the signal charge output unit and the transfer unit;
The signal charge output unit is an area obtained by subtracting the total area of the electrodes of the signal charge collecting unit, the transfer unit, the signal charge discarding unit, and the plurality of signal charge storage and transfer units from the area of the pixel. The signal charge collected by the signal charge collection unit is output to the transfer unit via the plurality of signal charge accumulation and transfer units in the first period, The pixel structure of the backside illumination type solid-state imaging device according to claim 1, wherein the pixel structure is output to the signal charge discarding unit during a period of 2. The pixel structure of the back-illuminated solid-state imaging device according to claim 1 or 2,
A back electrode provided on the other surface side;
A back-illuminated solid-state imaging device. A driving apparatus for driving the back-illuminated solid-state imaging device according to claim 3,
Back electrode voltage application means for applying a voltage for driving the back electrode;
A signal charge collecting voltage applying means for applying a voltage for collecting the signal charge generated by the subject light to the signal charge collecting unit to the signal charge collecting unit;
Signal charge output voltage applying means for applying a voltage for transferring the signal charge collected by the signal charge collecting unit to the signal charge output unit;
Transfer voltage applying means for applying a voltage for transferring the signal charge input from the signal charge output section toward the output side;
A discard voltage applying means for applying a voltage for discarding the signal charge input from the signal charge output unit;
A drive device comprising: A back-illuminated solid-state imaging device according to claim 3,
A drive device according to claim 4;
A signal processing circuit that processes a signal from a plurality of pixel portions of the back-illuminated solid-state imaging device and outputs a video signal;
An imaging apparatus comprising: Driving a pixel structure of a back-illuminated solid-state imaging device having a plurality of pixel portions arranged in a two-dimensional array on one surface side of a semiconductor substrate and injecting subject light from the other surface side of the semiconductor substrate A method,
Each pixel portion is
A signal charge collecting unit for collecting signal charges generated by the subject light;
A signal charge output unit connected to the signal charge collection unit and outputting the signal charge;
A transfer unit connected to the signal charge output unit and transferring the input signal charge to the output side;
A signal charge discarding unit that is connected to the signal charge output unit and discards the input signal charge;
With
The signal charge output unit includes an electrode having an area smaller than an area obtained by subtracting a total area of the electrodes of the signal charge collection unit, the transfer unit, and the signal charge discard unit from the area of the pixel. ,
The signal charge output unit outputting the signal charge collected by the signal charge collection unit to the transfer unit in a first period;
The signal charge output unit outputting to the signal charge discarding unit in a second period following the first period;
A method for driving a pixel structure of a back-illuminated solid-state imaging device, comprising:

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