JP2008103668A - Back irradiation image sensor and imaging device with that image sensor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a back irradiation image sensor having an overflow drain mechanism advantageous to downscaling and discharging unnecessary charges surely while preventing deterioration in blue sensitivity. <P>SOLUTION: A back irradiation image sensor 100 which performs imaging by irradiating the back side of a p-substrate 30 with light and reading out charges generated in the p-substrate 30 depending on the light from the surface side of the p-substrate 30 comprises a plurality of n-layers 4 for storing the charges formed on the same plane near the surface of the p-substrate 30 in the p-substrate 30, a plurality of n+ layers 6 formed between the plurality of n-layers 4 and the surface of the p-substrate 30, respectively, and functioning as an overflow drain for discharging unnecessary charges stored in the plurality of n-layers 4, respectively, and a plurality of p+ layers 5 formed between the plurality of n+ layers 6 and the plurality of n-layers 4, respectively, and functioning as an overflow barrier for the overflow drain wherein the n+ layer 6 is formed at a position overlapping the maximum potential point (center) of the n-layer 4 on the plan view. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a backside illuminating type imaging device that irradiates light from a back surface side of a semiconductor substrate, reads out charges generated in the semiconductor substrate in response to the light from the front surface side of the semiconductor substrate, and performs imaging.

  Light is irradiated from the back side of the semiconductor substrate, and electric charges generated in the semiconductor substrate in response to the light are accumulated in a charge accumulation region formed on the front side of the semiconductor substrate, and according to the electric charges accumulated here There has been proposed a back-illuminated image sensor that outputs a signal to the outside by a CCD, a CMOS circuit, or the like and performs imaging. In the following, a general imaging device that is currently popular with respect to the backside illumination type imaging device is referred to as a front side illumination type imaging device.

  In this backside illuminating type image pickup device as well, it is necessary to provide an overflow drain mechanism for discharging excess charges unnecessary for image pickup accumulated in the photoelectric conversion element as in the case of the front side illuminating type image pickup device. The overflow drain mechanism applied to the surface irradiation type imaging device includes a vertical overflow drain mechanism and a horizontal overflow drain mechanism. In the horizontal overflow drain mechanism, a drain region is provided in parallel to each photoelectric conversion element adjacent to each photoelectric conversion element. With this mechanism, when miniaturization progresses, the size of each constituent element is sufficiently large. It is difficult to maintain the saturation signal amount. On the other hand, since the vertical overflow drain mechanism has a structure in which a drain region is provided below each photoelectric conversion element, the size of each component can be secured even when miniaturization progresses, and the saturation signal amount Can be maintained.

  Patent Document 1 discloses a configuration in which a vertical overflow drain mechanism is employed in a back-illuminated image sensor.

  Patent Document 2 discloses a configuration in which an overflow drain mechanism is provided on the front surface side in a back-illuminated image sensor.

JP 2001-257337 A JP 2006-49338 A

  The configuration disclosed in Patent Document 1 is a configuration in which light irradiated from the back surface of the back-illuminated image sensor first enters the vertical overflow drain region, and light that has passed there enters the photoelectric conversion device. Therefore, charges generated in the vertical overflow drain region and its depletion layer are discharged from this drain region. This drain region exists at a shallow position in the semiconductor substrate as viewed from the light incident side. Here, a large amount of light in the blue wavelength region is absorbed, and as a result, the imaging device has a significantly low blue sensitivity.

  On the other hand, according to the configuration disclosed in Patent Document 2, it is possible to prevent a decrease in blue sensitivity, but since the drain region is provided above the position away from the maximum potential point of the photodiode, it is excessive. Charges cannot be discharged sufficiently. In particular, when the electronic shutter function is realized by sweeping out all charges accumulated in the photodiode, the charge remains in the photodiode when the electronic shutter is turned on, and fixed pattern noise or the like is generated.

  The present invention has been made in view of the above circumstances, and is advantageous for miniaturization, can prevent a decrease in blue sensitivity, and can completely sweep out unnecessary charges, that is, an electron with less fixed pattern noise. An object of the present invention is to provide a back-illuminated image sensor having an overflow drain mechanism capable of realizing a shutter function.

  The backside illumination type imaging device of the present invention irradiates light from the backside of the semiconductor substrate, and reads back the charge generated in the semiconductor substrate in response to the light from the topside of the semiconductor substrate to perform imaging. A plurality of first impurity diffusion layers of a first conductivity type for accumulating the electric charge formed on the same surface of the semiconductor substrate near the surface of the semiconductor substrate; A second impurity diffusion layer of the first conductivity type formed between each of the first impurity diffusion layers and the surface of the semiconductor substrate, and is accumulated in each of the plurality of first impurity diffusion layers. A plurality of second impurity diffusion layers functioning as overflow drains for discharging unnecessary charges, and each of the plurality of second impurity diffusion layers and each of the plurality of first impurity diffusion layers. Formed between and over A plurality of third impurity diffusion layers of a second conductivity type opposite to the first conductivity type that function as an overflow barrier of a low drain, wherein the second impurity diffusion layer is the first impurity in plan view It is formed at a position overlapping the maximum potential point of the diffusion layer.

  In the backside illumination type imaging device of the present invention, the maximum potential point of the first impurity diffusion layer is at the center of the first impurity diffusion layer in plan view.

  In the backside illumination type imaging device of the present invention, the maximum potential point of the first impurity diffusion layer is a depth within 0.3 μm from the boundary surface between the first impurity diffusion layer and the third impurity diffusion layer. It is in.

  The back-illuminated imaging device of the present invention is a first conductivity type impurity diffusion layer having a lower concentration than the second impurity diffusion layer formed in the vicinity of each of the plurality of second impurity diffusion layers. And a depletion layer expansion layer for expanding the depletion layer formed by the second impurity diffusion layer in a direction parallel to the surface.

  In the backside illumination type imaging device of the present invention, the depletion layer formed by the second impurity diffusion layer covers 2/3 or more of the first impurity diffusion layer in plan view.

  The backside illumination type imaging device of the present invention has an exposed surface where each of the plurality of second impurity diffusion layers is exposed on the surface, and includes an electrode connected to the exposed surface.

  The imaging apparatus of the present invention includes the backside illumination type imaging device, a first voltage applying unit that applies a first voltage that determines a saturation charge amount of the first impurity diffusion layer to the electrode, and the first A second voltage applying means for applying a second voltage higher than the first voltage necessary for eliminating the overflow barrier formed by the third impurity diffusion layer when the voltage is applied to the electrode. Prepare.

  In the imaging apparatus of the present invention, the second voltage application unit variably controls the application timing of the second voltage, thereby adjusting the exposure time of the backside illumination type imaging device.

  In the imaging apparatus of the present invention, the first voltage application unit adjusts the saturation charge amount of the first impurity diffusion layer by variably controlling the first voltage.

  In the imaging apparatus of the present invention, the second voltage is determined by a value based on the first voltage.

  In the imaging device of the present invention, the back-illuminated imaging device transfers a vertical charge transfer device that transfers charges accumulated in each of the plurality of first impurity diffusion layers in a vertical direction, and transfers the vertical charge transfer device. A horizontal charge transfer device that transfers the generated charge in a horizontal direction orthogonal to the vertical direction, wherein the first voltage is equal to or lower than a driving voltage of the horizontal charge transfer device, and the second voltage is It is below the read voltage for reading the charge to the vertical charge transfer device.

  In the imaging device of the present invention, the plurality of first impurity diffusion layers are divided into n (n is a natural number of 2 or more) groups, and charges accumulated in each group are added by the vertical charge transfer device. And a non-addition transfer mode in which charges accumulated in each group are transferred in a non-addition manner by the vertical charge transfer device, and when the addition transfer mode is set, the first transfer mode can be set. The voltage application means is configured to determine a saturation charge amount of the first impurity diffusion layer, which is determined by the first voltage to be applied to the electrode when the non-addition transfer mode is set. The first voltage is variably controlled so as to be / n.

  The imaging device of the present invention includes a source follower circuit in which the backside illumination type imaging device converts the charge transferred from the horizontal charge transfer device into a voltage signal and outputs the voltage signal, and the vertical charge transfer device has the largest voltage. Are driven by three voltages, VH, which is the smallest voltage, and VM, which is the voltage between VH and VL, and the second voltage is the voltage of the source follower circuit. This is a value obtained by adding one of the drain applied voltage of the final stage transistor, the difference between the VL and the VM, and the difference between the VH and the VM and the first voltage.

  In the imaging device of the present invention, the backside illumination type imaging device reads out and accumulates charges accumulated in each of the plurality of first impurity diffusion layers, and the charge accumulation layer And a CMOS circuit that outputs a signal corresponding to the accumulated charge.

  According to the present invention, an overflow drain mechanism that is advantageous for miniaturization, can prevent a decrease in blue sensitivity, and can completely sweep out unnecessary charges, that is, can realize an electronic shutter function with less fixed pattern noise. Can be provided.

  Embodiments of the present invention will be described below with reference to the drawings.

(First embodiment)
FIG. 1 is a partial cross-sectional schematic diagram of an interline back-illuminated image sensor for explaining a first embodiment of the present invention.
A back-illuminated imaging device 100 shown in FIG. 1 includes a p-type silicon layer (hereinafter referred to as a p layer) 1 and a p ++ type silicon layer (hereinafter referred to as a p ++ layer) 2 having a higher impurity concentration than the p layer 1. A p-type semiconductor substrate (hereinafter referred to as a p-substrate) 30 is provided. The back-illuminated image sensor 100 performs imaging by allowing light to enter from the lower side to the upper side in the drawing. In the present specification, of the two surfaces perpendicular to the light incident direction of the p-substrate 30, the surface on the light incident side is referred to as the back surface, and the opposite surface is referred to as the surface. In addition, the direction in which the incident light travels is defined as the upper direction of each component when the components constituting the back-illuminated image sensor 100 are used as a reference, and the direction opposite to the direction in which the incident light travels is defined as the component. It is defined as below. Further, a direction orthogonal to the back surface and the front surface of the p substrate 30 is defined as a vertical direction, and a direction parallel to the back surface and the front surface of the p substrate 30 is defined as a horizontal direction.

  On the same surface extending in the horizontal direction near the surface of the p substrate 30 in the p layer 1, an n-type impurity diffusion layer (hereinafter referred to as n layer) for accumulating charges generated in the p substrate 30 in response to incident light. A plurality of 4). The n layer 4 has a two-layer structure of an n layer 4a formed on the surface side of the p substrate 30 and an n− layer 4b having a lower impurity concentration than the n layer 4a formed under the n layer 4a. However, it is not limited to this. The charges generated in the n layer 4 and the charges generated in the p substrate 30 on the path of light incident on the n layer 4 are accumulated in the n layer 4.

  A high-concentration p-type impurity diffusion layer (hereinafter referred to as a p + layer) 5 is formed on each n layer 4 to prevent dark charges generated on the surface of the p substrate 30 from accumulating in each n layer 4. ing. In each p + layer 5, an n-type impurity diffusion layer (hereinafter referred to as an n + layer) 6 having a higher concentration than the n layer 4 is formed from the surface of the p substrate 30 toward the inside thereof. The n + layer 6 functions as an overflow drain for discharging unnecessary charges accumulated in the n layer 4, and the p + layer 5 also functions as an overflow barrier for the overflow drain. As illustrated, the n + layer 6 has an exposed surface exposed on the surface of the p substrate 30.

  A charge transfer channel 12 made of an n-type impurity diffusion layer having a higher concentration than the n layer 4 is formed slightly adjacent to the right side of the p + layer 5 and the n layer 4. A p + layer is formed around the charge transfer channel 12. A p layer 11 having a concentration lower than 5 is formed. The charge transfer channel 12 transfers the charge read from the n layer 4 in a direction perpendicular to the paper surface.

  In the p layer 11 and the p layer 1 between the p + layer 5 and the n layer 4 and the charge transfer channel 12, a charge reading region (not shown) for reading out the charges accumulated in the n layer 4 to the charge transfer channel 12. ) Is formed. Charge transfer for controlling the charge transfer operation by supplying a voltage to the charge transfer channel 12 via the gate insulating film 20 made of a silicon oxide film, an ONO film or the like above the charge transfer channel 12 and the charge readout region. An electrode 13 made of polysilicon or the like serving as an electrode and a charge readout electrode for controlling a charge readout operation by supplying a readout voltage to the charge readout region is formed. An insulating film 14 such as silicon oxide is formed around the electrode 13. The charge transfer channel 12 and the electrode 13 thereabove constitute a vertical charge transfer device (VCCD).

  Although not shown in FIG. 1, charge transfer is performed on the surface of the p layer 1 by receiving the charge transferred through the charge transfer channel 12 and transferring it in a direction orthogonal to the charge transfer direction of the charge transfer channel 12. A channel is formed, and a charge transfer electrode for controlling the charge transfer operation of the charge transfer channel is formed above the channel. The charge transfer channel and the charge transfer electrode constitute a horizontal charge transfer device (HCCD). . At the end of the HCCD, a floating diffusion (FD) region for accumulating the charges transferred from the HCCD is provided, and a source follower circuit for outputting a signal corresponding to the charges accumulated in the FD region to the FD region. A signal output amplifier consisting of is connected.

  An element isolation layer 15 made of a p-type impurity diffusion layer is formed between adjacent n layers 4 below the p layer 11. The element isolation layer 15 is for preventing the charges to be accumulated in the n layer 4 from leaking to the adjacent n layer 4.

  A gate insulating layer 20 is formed on the surface of the p substrate 30, and an insulating layer 9 such as silicon oxide is formed on the gate insulating layer 20, and an electrode 13 and an insulating film 14 are formed in the insulating layer 9. Is buried. Further, in the gate insulating layer 20 and the insulating layer 9, a contact hole having an area equal to or smaller than the exposed surface in plan view is formed on the exposed surface of the n + layer 6 in the contact hole. An electrode 7 is formed.

  The electrode 7 only needs to be a conductive material, and is particularly preferably composed of a metal material such as W (tungsten), Ti (titanium), or Mo (molybdenum), or silicide with these. Between the electrode 7 and the n + layer 6, it is preferable to provide a diffusion preventing layer for preventing diffusion of the conductive material constituting the electrode 7. For example, TiN (titanium nitride) is used as a constituent material of the diffusion prevention layer. By providing the diffusion prevention layer, the PN junction between the n + layer 6 and the p + layer 5 becomes uniform, and the saturation variation between pixels can be reduced.

  An electrode 8 is formed on the insulating layer 9, and the electrode 8 is connected to the electrode 7. A protective layer 10 is formed on the electrode 8. The electrode 8 may be any conductive material. A terminal is connected to the electrode 8, and a predetermined voltage can be applied to the terminal.

  Since the charges transferred to the n + layer 6 move to the electrode 7 connected to the exposed surface of the n + layer 6 and the electrode 8 connected thereto, the n + layer 6 can function as an overflow drain.

A p ++ layer 2 is formed from the back surface to the inside of the p substrate 30 in order to prevent dark charges generated on the back surface of the p substrate 30 from moving to the n layer 4. A terminal is connected to the p ++ layer 2, and a predetermined voltage (including a case where the voltage is a ground voltage) can be applied to the terminal. The concentration of the p ++ layer 2 is, for example, 1 × 10 ¹⁷ / cm ³ to 1 × 10 ²⁰ / cm ³ .

  Under the p ++ layer 2, an insulating layer 3 transparent to incident light such as silicon oxide or silicon nitride is formed. Under the insulating layer 3, incident light such as silicon nitride or diamond structure carbon film is used to prevent reflection of light on the back surface of the p substrate 30 due to a difference in refractive index between the insulating layer 3 and the p substrate 30. A transparent high refractive index transparent layer 16 is formed. The high refractive index transparent layer 16 is made of amorphous silicon nitride or the like that can be formed at a low temperature of 400 ° C. or lower such as plasma CVD or photo CVD. It is preferable to make it a layer.

  Under the high refractive index transparent layer 16, a color filter layer formed by arranging a plurality of color filters 18 in the horizontal direction is formed. The plurality of color filters 18 are classified into a plurality of types of color filters that transmit light in different wavelength ranges. For example, the color filter layer includes an R color filter that transmits light in the red wavelength region, a G color filter that transmits light in the green wavelength region, and a B color filter that transmits light in the blue wavelength region. It has become the composition. The color filter 18 is formed below each of the plurality of n layers 4, and one color filter 18 is provided for each n layer 4. Further, since each n layer 4 corresponds to one n + layer 6, it can be said that the color filter 18 corresponds to one of the plurality of n + layers 6.

  A light shielding member 17 for preventing color mixture is formed between adjacent color filters 18. The light shielding member 17 may be any member having a function of not transmitting light, and a metal having a low visible light transmittance such as W, Mo, and Al (aluminum) or a black filter can be used.

  The light shielding member 17 has a cross-sectional shape that is tapered (a triangle whose apex is directed toward the light incident side, or a trapezoid whose upper base is longer than the lower base) that widens toward the back surface of the p substrate 30. Is preferred. By doing in this way, the light perpendicularly incident on the light shielding member 17 can be reflected by the tapered surface and guided into the p substrate 30, and the light utilization efficiency can be increased.

  Under each color filter 18, a microlens 19 is formed. The shape of the microlens 19 is determined so that the refracted light becomes an optical path that avoids the light blocking member 17 between the color filter 18 above and the color filter 18 adjacent to the color filter 18. . Further, the focal point of the microlens 19 is designed to be in the center of the n layer 4.

  Of the region from the upper surface of the n layer 4 to the back surface of the p substrate 30, the region partitioned by the element isolation layer 15 in plan view is a region that performs photoelectric conversion contributing to imaging, and is hereinafter referred to as a photoelectric conversion region. Since a signal corresponding to the charge generated in one photoelectric conversion region is the basis of one pixel data of image data, this photoelectric conversion region is also referred to as a pixel in this specification. That is, the back-illuminated image sensor 100 includes a plurality of pixels and a CCD-type or CMOS-type signal readout unit that reads out a signal corresponding to the charge generated in each of the plurality of pixels.

  It has been experimentally found that the silicon substrate needs to have a thickness of 9 μm or more in order to absorb all the light in the visible region due to the difference in the light absorption coefficient for each wavelength. For this reason, also in the backside illumination type imaging device 100, it is preferable that the vertical length of the p substrate 30 is 9 μm or more. By doing so, visible light can be absorbed without fail, and the sensitivity can be improved.

When the vertical length of the p substrate 30 is 9 μm or more, there are the following advantages.
Since light hardly reaches the charge transfer channel 12, no back-shielding layer for shielding the charge transfer channel 12 is provided in the p substrate 30, and the back-illuminated image sensor is made to be a frame interline type. Therefore, an image sensor with sufficiently low smear can be realized even in the interline type.
・ Quantum efficiency increases and sensitivity improves.
・ Long wavelength sensitivity is increased.
・ Near-infrared sensitivity increases dramatically.

  However, if the vertical length of the p substrate 30 is 9 μm or more, each photoelectric conversion is performed at a low depletion voltage of the n layer 4 (about 3 V used in the current imaging device) due to the influence of the charge separation layer 15 and the like. It becomes difficult to form a depletion layer in the region. Therefore, the concentration of the p substrate 30 is optimized so that a depletion layer can be formed in each photoelectric conversion region, and a potential gradient that can move the charge generated in this depletion layer to the n layer 4 is provided. It is necessary to design.

As a result of simulation, the present applicant has found that the above conditions can be satisfied by configuring the p substrate 30 to have the following configurations (1) to (3).
(1) The intermediate layer between the n layer 4 and the p ++ layer 2 includes at least an n layer or p layer of 1 × 10 ¹⁴ / cm ³ or i layer, or (2) the intermediate layer is 2 × and 10 ¹⁴ / cm ³ or less of the n layer, a configuration and a 2 × ¹⁰ 14 / cm ³ or less of p layer (3) between the n layer and p layer ^{(2), 1 × 10 14} / cm 3 or less A structure including at least one of an n layer, a p layer of 1 × 10 ¹⁴ / cm ³ or less, and an i layer

  In the back-illuminated imaging device 100 configured as described above, light incident on one microlens 19 enters the color filter 18 above the microlens 19, and light transmitted therethrough enters the color filter 18. The light enters the corresponding n layer 4. At this time, charges are also generated in the portion of the p substrate 30 that serves as a path for incident light. However, the charges move to the n layer 4 through the potential slope formed in the photoelectric conversion region and are accumulated there. The The charges generated here upon entering the n layer 4 are also accumulated here. The charges accumulated in the n layer 4 are read and transferred to the charge transfer channel 12, converted into a signal by an output amplifier, and output to the outside.

FIG. 2 is a diagram showing a potential profile of the BB line shown in FIG.
As shown in FIG. 2, it can be seen that potential wells are formed in the n + layer 6 and the photoelectric conversion region, respectively, and the p + layer 5 functions as a barrier between these potential wells. The charge exceeding the saturation capacity of the potential well formed in the photoelectric conversion region flows into the potential well formed in the n + layer 6, and the flowed-in charge moves to the electrode 7 and is discharged to the outside. Therefore, the saturation capacity of the n layer 4 can be controlled by changing the voltage applied to the electrode 7 connected to the n + layer 6 to adjust the height of the barrier of the p + layer 5. For example, in the moving image shooting mode in which signals are added and read out, overflow in the charge transfer channel 12 can be prevented by performing control to reduce the saturation capacity of the n layer 4.

  Further, as shown by a broken line in FIG. 2, a voltage at a level that can eliminate the barrier formed in the p + layer 5 is applied to the electrode 7 connected to the n + layer 6 to form the photoelectric conversion region. Since the charge in the potential well can be reset, an electronic shutter can be realized by utilizing this fact.

  In order to completely reset the charge in the potential well formed in the photoelectric conversion region, the formation position of the n + layer 6 is important. Since the maximum potential point of the n layer 4 (synonymous with the maximum potential point of the photoelectric conversion region) is the deepest place of the potential well, if the charges accumulated here can be moved to the n + layer 6, the photoelectric conversion region The charge in the formed potential well can be completely reset. In the back-illuminated image sensor 100, the n + layer 6 is formed at a position overlapping the maximum potential point of the n layer 4 in plan view. Due to this positional relationship, the charge in the potential well formed in the photoelectric conversion region is transferred. It is possible to reset completely. As disclosed in Patent Document 2, when the n + layer 6 is provided at a position that does not overlap with the maximum potential point of the n layer 4, the charge accumulated in the deepest place of the potential well formed in the photoelectric conversion region is the n + layer. 6 is not suitable for realizing the electronic shutter function, but according to the configuration of the back-illuminated image sensor 100, the electronic shutter function can be sufficiently realized.

  FIG. 3 is a plan view of the n layer 4. As shown in FIG. 3, since the concentration of the n layer 4 is constant in the horizontal direction, the maximum potential point M exists at the center of the n layer 4. For this reason, in the backside illumination type image pickup device 100, the electronic shutter function can be realized by providing the n + layer 6 at a position overlapping the center of the n layer 4.

  Note that the maximum potential point of the n layer 4 is not necessarily at the center of the n layer 4. For example, when the configuration of the n layer 4 is as shown in FIG. 4, the maximum potential point of the n layer 4 exists at a position shifted from the center thereof, as shown. In this case, the n + layer 6 may be provided at a position overlapping the maximum potential point M shown in FIG.

  Further, the distance (depth) of the maximum potential point of the n layer 4 from the boundary surface between the p + layer 5 and the n layer 4 is more complete for sweeping out charges from the potential well formed in the photoelectric conversion region. In order to keep the voltage applied to the electrodes 7 and 8 lower during charge sweeping, it is preferably within 0.3 μm.

  The electrode 7 connected to the n + layer 6 is connected in common for each type of color filter 18 corresponding to the n + layer 6, and voltage is independently applied to each electrode 7 common to each type of color filter 18. A configuration is also conceivable so that the voltage can be applied. In this case, it is possible to independently apply an electronic shutter for each photoelectric conversion region corresponding to each type of color filter. That is, the charge accumulation time in each photoelectric conversion region can be changed for each color of light incident thereon, and an output with a uniform color balance can be obtained by controlling the charge accumulation time.

  In addition, a plurality of n + layers 6 includes a first group of n + layers 6 corresponding to the n layer 4 that reads charges in a shooting mode that performs thinning readout such as a moving image shooting mode, and n that does not read charges in the shooting mode. It is classified into a second group consisting of n + layers 6 corresponding to the layers 4, and electrodes 7 are connected in common to each n + layer 6 belonging to the same group, and each of the common electrodes 7 is connected. A configuration in which a voltage can be applied independently is also conceivable. In this case, by changing the applied voltage for each group, it is possible to enhance the inter-pixel blooming suppression effect for highlight light.

  The voltage application to the electrodes 7 and 8 may be performed by a driver that drives the backside illumination type image sensor 100 in an imaging apparatus such as a digital camera equipped with the backside illumination type image sensor 100. Hereinafter, a configuration example of an imaging apparatus including the backside illumination type imaging element 100 will be described.

FIG. 5 is a block diagram illustrating a configuration example of an imaging apparatus including the backside illumination type imaging device 100.
An imaging apparatus 800 shown in FIG. 5 includes a back-side illuminated image sensor 100, a voltage applying unit 200 that applies a voltage to the electrode 8 of the back-side illuminated image sensor 100, and an H driver that drives the HCCD of the back-side illuminated image sensor 100. 300, a V driver 400 that drives the VCCD of the back-illuminated image sensor 100, an amplifier power source 500 that is a power source of a signal output amplifier of the back-illuminated image sensor 100, a control unit 600 that performs overall control of the entire image capturing apparatus, And an operation unit 700.

  The V driver 400 drives the VCCD by supplying a read voltage VH for reading out charges from the n layer 4 to the VCCD and voltages VM and VL necessary for charge transfer to the back-illuminated image sensor 100. Note that VH> VM> VL, and VH is, for example, about 15V.

  The H driver 300 drives the HCCD by supplying the voltages vH and vL necessary for charge transfer to the back-illuminated image sensor 100. Note that vH> vL, and vH is, for example, about 3.3V.

  The amplifier power supply 500 is a power supply that supplies the drain voltage of the transistor at each stage of the source follower circuit of the signal output amplifier.

  The voltage application unit 200 applied a first function for applying a first voltage for determining the saturation charge amount of the n layer 4 (synonymous with the saturation charge amount of the photoelectric conversion region) to the electrode 8 and the first voltage. And has a second function of applying a second voltage higher than the first voltage necessary for eliminating the overflow barrier formed by the p + layer 5 to the electrode 8. The first voltage is preferably HCCD drive voltage (amplitude 3.3V) or less, and the second voltage is preferably read voltage VH (amplitude 15V) or less. By doing so, the first voltage and the second voltage can be generated from the existing power supply, and a new power supply becomes unnecessary.

  The second voltage is preferably set to a value based on the first voltage. For example, the second voltage is set to a value obtained by adding one of the drain applied voltage of the final stage transistor of the source follower circuit, the difference between VL and VM, and the difference between VH and VM to the first voltage. By doing in this way, a 2nd voltage can be produced | generated from the existing power supply, and a new power supply can be made unnecessary.

The voltage application unit 200 adjusts the saturation charge amount of the n layer 4 by variably controlling the first voltage, or variably controls the application timing of the second voltage, thereby exposing the exposure time of the backside illumination type image sensor 100. To adjust. For example, the imaging apparatus 800 divides a plurality of n layers 4 into n (n is a natural number of 2 or more) groups, and adds and transfers charges accumulated in each group by the VCCD, It is assumed that the non-addition transfer mode in which the charges accumulated in each group are transferred without being added by the VCCD can be set. The non-addition transfer mode is executed, for example, in a still image shooting mode that requires high image quality, and the addition transfer mode is executed, for example, in a moving image shooting mode that requires high-speed operation.
When the addition transfer mode is set, the voltage application unit 200 is 1 / n of the saturation charge amount of the n layer 4 determined by the first voltage to be applied to the electrode 8 when the non-addition transfer mode is set. Thus, the first voltage is variably controlled (see FIG. 6). By doing so, it is possible to prevent the charge from overflowing in the VCCD or HCCD.

An operation of the imaging apparatus 800 having the above configuration will be described.
When the still image shooting mode is set by the user via the operation unit 700 and the exposure time is determined by the control unit 600, the voltage application unit 200 performs the electrode 8 until just before the start of the exposure time determined by the control unit 600. The second voltage application as shown in FIG. 6 is repeated. Simultaneously with the start of exposure, the voltage applied to the electrode 8 is switched to the first voltage (1) as shown in FIG. After the exposure period ends, the charges accumulated in the n layer 4 by the H driver 300 and the V driver 400 are transferred to the signal output amplifier, where they are converted into signals and output.

  On the other hand, when the moving image shooting mode is set by the user via the operation unit 700 and the exposure time is determined by the control unit 600, the voltage application unit 200 performs the electrode operation until immediately before the start of the exposure time determined by the control unit 600. 8 repeatedly applies the second voltage as shown in FIG. Simultaneously with the start of exposure, the voltage applied to the electrode 8 is switched to the first voltage (2) as shown in FIG. After the exposure period ends, the charges accumulated in the n layer 4 by the H driver 300 and the V driver 400 are transferred to the signal output amplifier, where they are converted into signals and output.

  Since the back-illuminated imaging device 100 is an interline type, light may enter the charge transfer channel 12 during the exposure period, which causes smear. In the following, as described above, it is proved based on the simulation results that smear can be kept low if the vertical length of the p substrate 30 is 9 μm or more.

FIG. 7 is a partially simplified view of the back-illuminated image sensor 100 shown in FIG. 1, and the same elements as those in FIG. 1 are denoted by the same reference numerals.
In FIG. 7, symbol a represents the vertical length of the depletion layer of the charge transfer channel 12, symbol b represents the horizontal length of the depletion layer of the charge transfer channel 12, and symbol c represents the p substrate 30. The symbol d indicates the arrangement pitch of the n layers 4. In the model shown in FIG. 7, a light absorption layer 21 that absorbs light is provided instead of the insulating layer 9.

  Here, a = 0.00004 cm, b = 0.00005 cm, c = 0.0005 cm, d = 0.0002 cm, and all the electrons generated in the charge transfer channel 12 other than the depletion layer formed therein are all Assuming that the signal flows into the n layer 4 corresponding to the charge transfer channel 12 and becomes a signal, all electrons generated in the depletion layer of the charge transfer channel 12 are assumed to be a smear signal. The arrangement of the n layer 4 was a square arrangement, and the signal readout method was an interline method. Further, all the light that has passed through the p substrate 30 is absorbed by the light absorption layer 21.

  The light absorption rate Y of silicon having a thickness x (cm) is Y = {1−Exp (−α × x)} (where α is the light absorption coefficient of silicon). An IR cut filter is arranged below the back surface side of the p-type substrate 30 of the image sensor, and each wavelength (400 to 700 nm, 10 nm interval) is determined from the transmission spectrum of each pixel when the IR cut filter is irradiated with light from a 3300K light source. The signal and the smear signal are calculated to calculate an average value, and when the ratio of the smear signal to the signal is obtained under the condition that the implantation occurs in the region of 1/10 of the p substrate 30 in the vertical direction, 0.032% (n layer) When 4 is a honeycomb arrangement, it was 0.056%) (see FIG. 8).

  When c = 8 μm = 0.0008 cm, the smear signal ratio is 0.0075% (0.013% when the n-layer 4 is arranged in a honeycomb), and when c = 10 μm = 0.001 cm, The smear signal ratio was 0.0032% (0.0056% when the n-layer 4 is arranged in a honeycomb arrangement) (see FIG. 8).

  Here, the honeycomb arrangement is an arrangement in which a large number of rows of n layers 4 arranged in the row direction are arranged in a column direction orthogonal to the row direction, and even and odd rows are arranged in the row direction. When compared with the square arrangement, the area of the charge transfer channel is increased by 1.75 times. Therefore, the result of the square arrangement is 1.75 times the estimated value of the honeycomb arrangement. It was.

  From the simulation results shown in FIG. 8, the interline-type backside-illuminated image sensor 100 has an interline-type surface-illuminated image sensor for obtaining the same sensitivity when the length of the p-substrate 30 in the vertical direction is 5 μm or more. It was found that smear can be suppressed more than the device. It was also found that smear can be further suppressed when the vertical length of the p substrate 30 is 8 μm or more, and smear can be further suppressed when the length is 10 μm or more.

  As described above, according to the backside illumination type imaging device 100, since the overflow drain is provided on the front surface side of the p substrate 30 where incident light hardly reaches, the conventional structure in which the overflow drain is provided on the back surface side of the p substrate 30 is employed. In comparison, the blue sensitivity can be improved.

  Also, by controlling the voltage applied to this overflow drain, the saturation capacity and charge accumulation time of each photoelectric conversion region can be controlled uniformly or independently, and various patterns can be easily driven. it can.

  Further, according to the backside illumination type image pickup device 100, the voltage amplitude applied to the n + layer 6 when realizing an electronic shutter can be greatly reduced as compared with the conventional structure in which an overflow drain is provided on the backside of the p substrate 30. Yes (23V → 15V or less). On the contrary, if the voltage amplitude is the same as the conventional one, the saturation capacity of each photoelectric conversion region can be greatly increased.

  In FIG. 1, the p ++ layer 2 is omitted. Instead, a transparent electrode such as ITO transparent to the incident light is provided under the insulating layer 3 so that a voltage can be applied to the transparent electrode. If a negative voltage is applied to the transparent electrode, dark current generated on the back surface of the p substrate 30 can be suppressed.

  In the above description, as described above, if the length of the p substrate 30 in the vertical direction is 8 μm or more, smear is sufficiently suppressed. Therefore, the back-illuminated image sensor 100 is an interline type. Even if the depth of the photoelectric conversion region is 8 μm or more, smear is somewhat generated. For this reason, if the back-illuminated image sensor 100 is a frame interline type, further smear reduction can be achieved.

  In the above description, the back-illuminated image sensor 100 is of the CCD type, but it may of course be a MOS type. In other words, a signal corresponding to the charge accumulated in the n layer 4 may be read out by a MOS circuit such as a CMOS circuit or an NMOS circuit.

Next, an example of a method for manufacturing an SOI substrate including the p substrate 30 and the insulating layer 3 of the backside illumination type imaging device 100 shown in FIG. 1 will be described.
FIG. 9 is a diagram for explaining a manufacturing process of an SOI substrate used for the backside illumination type image sensor 100. In FIG. 9, the same components as those in FIG.
First, the p layer 1 is formed on the base substrate 22 such as silicon by epitaxial growth or the like (FIG. 9A). In FIG. 9A, the exposed surface of the p layer 1 is the back surface of the p substrate 30. Next, an insulating layer 3 made of silicon oxide is formed on the exposed surface of the p layer 1 by CVD, thermal oxidation, or the like (FIG. 9B).

  Next, ion implantation of boron or the like is performed from above the insulating layer 3 to form the p ++ layer 2 inside the interface between the p layer 1 and the insulating layer 3 (FIG. 9C). Next, hydrogen ions are implanted near the interface between the base substrate 22 and the p layer 1 (FIG. 9D). By this ion implantation, a boundary layer 30 for separating the base substrate 22 and the p layer 1 is formed.

  Next, after a base substrate 23 made of silicon or the like is bonded onto the insulating layer 3, the base substrate 23 is rotated downward and the base substrate 22 is rotated upward (FIG. 9E). Next, the berth substrate 22 is peeled off from the p layer 1 together with the boundary layer 30 (FIG. 9F).

  Then, from the state of FIG. 9 (f), an element in the vicinity of the surface of the p substrate 30 is formed. After the formation, the base substrate 23 is removed by etching using the insulating layer 3 as a stopper, and then the color filter 18 and the micro The lens 19 and the like are formed to complete the manufacture of the backside illumination type imaging device 100.

  As a method of removing the base substrate 23 in FIG. 9F, a method of performing etching using KOH as an etchant is conceivable. Etching using a photoexcitation method is also conceivable. In addition to silicon oxide, silicon nitride can be used as the insulating layer 3. In this case, an etchant using silicon nitride as a stopper may be used.

Next, a method for forming the n + layer 6 and the electrode 7 of the backside illumination type imaging device 100 will be described.
As the factors that destabilize the overflow drain characteristics of the back-illuminated image sensor 100, misalignment between the p + layer 5 and the n + layer 6, misalignment between the n + layer 6 and the electrode 7, and formation in the insulating layer 9 A defective coating of the electrode 7 on the contact hole is considered. In order to improve such misalignment and coverage, the simplest measure is to increase the areas of the p + layer 5 and the n + layer 6 and the electrode 7 in plan view. Such a measure becomes a major obstacle to the advancement of pixel miniaturization. Therefore, in the present embodiment, a method is proposed that can simultaneously achieve misalignment and coverage improvement and pixel miniaturization.

FIG. 10 is a diagram for explaining a method of forming the n + layer 6, the electrode 7, and the electrode 8 of the backside illumination type imaging device 100. 10, the same components as those in FIG. 1 are denoted by the same reference numerals.
First, from the state of FIG. 9 (f), after forming the n layer 4 and the p + layer 5 thereon by ion implantation or the like from the upper surface of the p substrate 30, the gate insulating layer 20 is formed on the surface of the p substrate 30. (Not shown), an insulating layer 9 is formed thereon, and in a plan view, a contact hole H is formed in a part of the region of the gate insulating layer 20 and the insulating layer 9 overlapping the p + layer 5 by photolithography and etching. This is formed (FIG. 10A).

  Next, for example, As (arsenic) is ion-implanted using the gate insulating layer 20 and the insulating layer 9 as a mask, and an n + layer 6 is formed in the p + layer 5 by self-alignment (FIG. 10B). From this state, for example, tungsten is deposited as a metal material constituting the electrode 7 by a CVD method or the like, flattened by etching or CMP using the insulating layer 9 as a stopper, and the contact hole H is filled with the metal material film. The electrode 7 is formed. Then, the conductive material constituting the electrode 8 is formed on the insulating layer 9 and the electrode 7, thereby completing the formation of the n + layer 6, the electrode 7, and the electrode 8.

  If the lower surface of the n + layer 6 and the n layer 4 come into contact with each other, the overflow barrier disappears, and the n + layer 6 cannot function as an overflow drain. A method for reliably preventing such a situation is shown in FIGS.

  After the n + layer 6 is formed by self-alignment, an impurity having a diffusion coefficient larger than that of the impurity of the n + layer 6, for example, B (boron) is ion-implanted using the gate insulating layer 20 and the insulating layer 9 as a mask. A p + layer 24 is formed under the layer 6 (FIG. 10C). Next, when annealing for activation is performed, since B has a larger diffusion coefficient than As, the p + layer 24 spreads to cover the end of the n + layer 6 (FIG. 10D). . Next, for example, tungsten is formed as a metal material constituting the electrode 7 by a CVD method or the like, and is flattened by etching or CMP using the insulating layer 9 as a stopper, and the contact hole H is filled with a metal material film, The electrode 7 is formed (FIG. 10E). Then, a conductive material constituting the electrode 8 is formed on the insulating layer 9 and the electrode 7, thereby completing the formation of the n + layer 6, the electrode 7, and the electrode 8 (FIG. 10F).

  Here, although the gate insulating layer 20 and the insulating layer 9 are used as a mask, the resist material layer used for forming an opening in the gate insulating layer 20 and the insulating layer 9 is left, and this resist material layer is combined. It may be used as a mask. Before forming the gate insulating layer 20 and the insulating layer 9, a resist material layer is formed on the surface of the p substrate 30, an opening is formed in the resist material layer, and then the n + layer 6 is formed using the resist material layer as a mask. And the p + layer 24 may be formed. In this case, the gate insulating layer 20 and the insulating layer 9 may be formed by removing the resist material layer after forming the n + layer 6 and the p + layer 24 and forming the electrode 7.

  According to the method shown in FIGS. 10C to 10F, even when the lower surface of the n + layer 6 is in contact with the n layer 4 in the state of FIG. 10B, the n + layer 6 and the n layer 4. Since the p + layer 24 can be formed in between, the p + layer 24 functions as an overflow barrier, and the n + layer 6 can function as an overflow drain.

  According to the above method, since the n + layer 6 is formed by self-alignment using the gate insulating layer 20 and the insulating layer 9 as a mask, misalignment between the n + layer 6 and the electrode 7 does not occur. For this reason, the horizontal width of the contact hole H can be reduced as much as possible, which does not become an obstacle when the pixels are miniaturized.

  Even if the aspect ratio of the contact hole H becomes strict, if tungsten is used as the material of the electrode 7, the electrode 7 can be embedded and the insulating layer 9 can be made thick.

  In the case of the back-illuminated image sensor 100, since it is not necessary to provide an opening above the n layer 4, the horizontal length of the portion of the electrode 13 protruding from the portion overlapping the charge transfer channel 12 to the n layer 4 side is set. It is possible to extend in the horizontal direction. If this portion can be lengthened, the read voltage when reading charges from the n layer 4 to the charge transfer channel 12 can be lowered. Conversely, if the read voltage is not changed, the concentration of the n layer 4 is increased. This is preferable because the saturation capacity can be increased. Therefore, in the backside illumination type image pickup device 100, it is effective to extend the horizontal length of the portion of the electrode 13 protruding from the portion overlapping the charge transfer channel 12 to the n layer 4 side in the horizontal direction.

  In this case, according to the method shown in FIG. 10, since the horizontal width of the electrode 7 can be made as thin as possible, the amount by which the electrode 13 can be extended can be increased, the read voltage is lowered, and the saturation capacity is increased. Very effective.

  The n + layer 6 is formed by performing ion implantation perpendicularly to the surface of the p + layer 5 exposed from the contact hole H so that the shadow of the insulating layer 9 does not occur during ion implantation, or the contact hole. It is preferable to perform ion implantation obliquely from at least four directions with respect to the surface of the p + layer 5 exposed from H.

  When ion implantation is performed obliquely (other than horizontal and vertical) from only one direction with respect to the surface of the p + layer 5 exposed from the contact hole H, the positions of the n + layer 6 and the contact hole H are affected by the shadow of the insulating layer 9. Due to the displacement, there is a risk that the electrode 7 and the p + layer 5 come into contact with each other and short-circuit. On the other hand, when the ion implantation is performed vertically or when the ion implantation is performed obliquely from at least four directions, the insulating layer 9 cannot be shaded, so that the electrode 7 and the p + layer 5 are in contact with each other. Can be prevented. If ion implantation is performed obliquely from at least four directions, the size of the n + layer 6 can be made larger than that of the contact hole H, which is more preferable.

  In addition, when ion implantation is performed vertically, it is preferable to perform ion implantation at a low acceleration. By performing at a low acceleration, the channeling problem can be almost ignored.

  Similarly, the p + layer 24 is formed by performing ion implantation perpendicularly to the surface of the p + layer 5 exposed from the contact hole H so that the shadow of the insulating layer 9 does not occur at the time of ion implantation, or by contact. Preferably, ion implantation is performed obliquely from at least four directions with respect to the surface of the p + layer 5 exposed from the hole H.

  When ion implantation is performed obliquely (other than horizontal and vertical) from only one direction with respect to the surface of the p + layer 5 exposed from the contact hole H, the position of the p + layer 24 is shifted by the shadow of the insulating layer 9. , The p + layer 24 cannot function as an overflow barrier. On the other hand, when the ion implantation is performed vertically or when the ion implantation is performed obliquely from at least four directions, the shadow of the insulating layer 9 cannot be formed, so that the p + layer 24 covers the lower surface of the n + layer 6. And the p + layer 24 can function reliably as an overflow barrier. When ion implantation is performed obliquely from at least four directions, it is more preferable because the size of the p + layer 24 can be surely made larger than that of the n + layer 6.

Next, an example of a method for gettering the contamination of the p substrate 30 of the SOI substrate will be listed below.
A gettering site is formed at the interface between the p substrate 30 and the insulating layer 3, and oxygen ions are implanted from the insulating layer 3 side to fix the contaminating impurities in the insulating layer 3.
As a method of forming a gettering site at the interface between the p substrate 30 and the insulating layer 3, there is a method of injecting fluorine or carbon into this interface from the insulating layer 3 side.
A gettering site is formed at the interface between the p substrate 30 and the insulating layer 3, and then the insulating layer 3 and the gettering site are removed by etching or the like, followed by low-temperature oxidation (radical oxidation or the like) to perform the insulating layer 3. An insulating layer serving as a substitute for is formed.

Next, modifications of the configuration and manufacturing method of the back-illuminated image sensor 100 are listed below.
The light shielding member 17 is provided on the entire surface between the color filter 18 and the high refractive index layer 16 for the specific color filter 18. With such a configuration, the photoelectric conversion region for detecting light transmitted through the specific color filter 18 can be used as a photoelectric conversion region for detecting the optical black level. If the position of the specific color filter 18 is the periphery of the back-illuminated image sensor 100, smear correction and black level correction can be performed in the same manner as a normal image sensor. Further, in this case, since the light shielding member 17 is provided between the color filter layer and the insulating layer 3, this manufacturing is easy.
The light shielding member 17 is also provided below the peripheral circuit of the backside illumination type image sensor 100.
The p ++ layer 2 is changed to a layer made of p-type amorphous SiC, and the insulating layer 3 is a transparent electrode transparent to incident light such as ITO, and a voltage can be applied to the transparent electrode.
When the p substrate 1 is composed of a plurality of impurity diffusion layers, each impurity diffusion layer is formed by dividing the process.
In the case where the p substrate 1 is composed of a plurality of impurity diffusion layers, each impurity diffusion layer is formed by dividing the process and then annealed to round the potential step.
When the p substrate 1 is composed of a plurality of impurity diffusion layers, each impurity diffusion layer is formed in the same process while changing the gas atmosphere concentration in an analog manner.

(Second embodiment)
In the back-illuminated image sensor 100 shown in FIG. 1, the p + layer 5 is formed so as to surround the n + layer 6. However, since the p + layer 5 may be at least a layer that functions as an overflow barrier, The p + layer 5 may be formed only between the n + layer 6 and the n layer 4 as shown in FIG. However, in this case, not the p + layer 6 but the p layer 11 exists between the surface of the p layer 1 and the n layer 4, and dark charges may move from this portion to the n layer 4. There is.

  If the n + layer 6 is made as large as possible in the horizontal direction, it is possible to suppress the movement of dark charges via the p layer 11, but if the n + layer 6 is made too large, element isolation is hindered. Absent. Therefore, in this embodiment, the n + layer 6 is set to the minimum necessary size (same size as the bottom area of the electrode 7), and a depletion layer formed by the n + layer 6 is disposed around the n + layer 6 in the horizontal direction. An n-type impurity diffusion layer (n layer) 40 having a concentration lower than that of the n + layer 6 is provided. By doing in this way, the dark charge moved to the n layer 40 can be moved to the n + layer 6 side, and the amount of dark charge moving to the n layer 4 can be reduced without hindering element isolation.

  In order to effectively reduce the dark charges moving to the n layer 4, it is preferable that the depletion layer formed by the n + layer 6 covers 2/3 or more of the n layer 4 in a plan view.

  In the first embodiment and the second embodiment, the case where the backside illumination type imaging device 100 is a CCD type has been described, but the backside illumination type imaging device 100 may be a CMOS type. That is, a configuration in which a CMOS circuit including a CMOS transistor that converts charges accumulated in the n layer 4 into a signal may be provided on the surface of the p layer 1. In the case of the CMOS type, a charge storage layer for temporarily storing charges read from the n layer 4 is formed in the vicinity of the n layer 4 and a signal corresponding to the charges stored in the charge storage layer is generated by the CMOS circuit. It is preferable to make it the structure to output. In this way, global exposure time control is possible, and the disadvantages peculiar to a CMOS type image sensor in which the subject under operation becomes a distorted image can be eliminated.

1 is a partial cross-sectional schematic diagram of an interline-type backside-illuminated image sensor for explaining a first embodiment of the present invention. The figure which shows the electric potential profile of the BB line shown in FIG. Plan view of n layer 4 shown in FIG. The figure which shows the modification of the back irradiation type image pick-up element shown in FIG. 1 is a block diagram illustrating a configuration example of an imaging apparatus including the backside illumination type imaging device illustrated in FIG. The figure which showed the relationship between the voltage applied to the drain of the back irradiation type image pick-up element shown in FIG. 1, and the saturation charge amount of the n layer 4 The figure which shows the structure of the back side illumination type image sensor which was used for simulation The figure which shows the simulation result which calculated | required the relationship between the thickness of p substrate, and smear The figure for demonstrating the manufacturing process of the SOI substrate used for a back irradiation type imaging device The figure for demonstrating the formation method of the n + layer 6, the electrode 7, and the electrode 8 of a back irradiation type imaging device Partial cross-sectional schematic diagram of an interline back-illuminated image sensor for explaining a second embodiment of the present invention

Explanation of symbols

1 p layer 2 p ++ layer 3, 9, 14 Insulating layer 4 n layer 5 p + layer (overflow barrier)
6 n + layer (overflow drain)
7, 8 Electrode 10 Protective layer 11 P layer 12 Charge transfer channel 13 Charge transfer electrode / charge readout electrode 15 Element isolation layer 16 High refractive index transparent layer 17 Light shielding member 18 Color filter 19 Microlens 20 Gate insulating layer

Claims (14)

A backside-illuminated imaging device that irradiates light from the back side of a semiconductor substrate, reads out charges generated in the semiconductor substrate in response to the light from the front side of the semiconductor substrate, and performs imaging,
A plurality of first impurity diffusion layers of a first conductivity type for accumulating the charge formed on the same surface in the semiconductor substrate near the surface of the semiconductor substrate;
A second impurity diffusion layer of the first conductivity type formed between each of the plurality of first impurity diffusion layers and the surface of the semiconductor substrate, wherein the plurality of first impurity diffusion layers; A plurality of second impurity diffusion layers functioning as overflow drains for discharging unnecessary charges accumulated in each of them;
A second conductivity opposite to the first conductivity type formed between each of the plurality of second impurity diffusion layers and each of the plurality of first impurity diffusion layers and functioning as an overflow barrier of the overflow drain. A plurality of third impurity diffusion layers of the mold,
A back-illuminated imaging device in which the second impurity diffusion layer is formed at a position overlapping a maximum potential point of the first impurity diffusion layer in plan view. The back-illuminated image sensor according to claim 1,
A back-illuminated imaging device in which the maximum potential point of the first impurity diffusion layer is at the center of the first impurity diffusion layer in plan view. The back-illuminated image sensor according to claim 1 or 2,
A back-illuminated imaging device in which the maximum potential point of the first impurity diffusion layer is at a depth within 0.3 μm from the boundary surface between the first impurity diffusion layer and the third impurity diffusion layer. The back-illuminated image sensor according to any one of claims 1 to 3,
A first conductivity type impurity diffusion layer having a lower concentration than the second impurity diffusion layer formed adjacent to each of the plurality of second impurity diffusion layers, wherein the second impurity diffusion layer A back-illuminated imaging device comprising a depletion layer expansion layer for expanding a depletion layer to be formed in a direction parallel to the surface. The back-illuminated image sensor according to any one of claims 1 to 4,
A back-illuminated imaging device in which a depletion layer formed by the second impurity diffusion layer covers 2/3 or more of the first impurity diffusion layer in plan view. It is a backside illumination type image sensor according to any one of claims 1 to 5,
Each of the plurality of second impurity diffusion layers has an exposed surface exposed on the surface,
A back-illuminated imaging device comprising an electrode connected to the exposed surface. A back-illuminated image sensor according to claim 6,
First voltage applying means for applying a first voltage for determining a saturation charge amount of the first impurity diffusion layer to the electrode;
Second voltage application for applying a second voltage higher than the first voltage necessary for eliminating the overflow barrier formed by the third impurity diffusion layer when the first voltage is applied to the electrode An imaging apparatus. The imaging apparatus according to claim 7,
An imaging apparatus in which the second voltage application unit variably controls the application timing of the second voltage, thereby adjusting an exposure time of the backside illumination type imaging device. The imaging device according to claim 7 or 8,
An imaging apparatus in which the first voltage applying unit adjusts a saturation charge amount of the first impurity diffusion layer by variably controlling the first voltage. The imaging apparatus according to any one of claims 7 to 9,
The imaging apparatus, wherein the second voltage is determined by a value based on the first voltage. It is an imaging device of any one of Claims 7-10,
The back-illuminated image sensor includes a vertical charge transfer device that transfers charges accumulated in each of the plurality of first impurity diffusion layers in a vertical direction, and charges transferred through the vertical charge transfer device in the vertical direction. A horizontal charge transfer device for transferring in a horizontal direction orthogonal to the
The first voltage is equal to or lower than a driving voltage of the horizontal charge transfer device;
The imaging device, wherein the second voltage is equal to or lower than a read voltage for reading the charge to the vertical charge transfer device. The imaging apparatus according to claim 11,
An addition transfer mode in which the plurality of first impurity diffusion layers are divided into n (n is a natural number of 2 or more) groups, and charges accumulated in each group are added and transferred by the vertical charge transfer device; In addition, it is possible to set a non-addition transfer mode in which charges accumulated in each group are transferred by the vertical charge transfer device in a non-addition manner,
When the addition transfer mode is set, the first voltage application unit determines the saturation charge amount of the first impurity diffusion layer depending on the first voltage to be applied to the electrode when the non-addition transfer mode is set. An imaging apparatus that variably controls the first voltage so as to be 1 / n of a saturation charge amount of one impurity diffusion layer. The imaging device according to claim 11 or 12,
The backside-illuminated imaging device includes a source follower circuit that converts the charge transferred from the horizontal charge transfer device into a voltage signal and outputs the voltage signal.
The vertical charge transfer device is driven by three voltages: VH which is the largest voltage, VL which is the smallest voltage, and VM which is a voltage between the VH and the VL,
The second voltage is a value obtained by adding one of the drain applied voltage of the final stage transistor of the source follower circuit, the difference between the VL and the VM, and the difference between the VH and the VM and the first voltage. An imaging device. The imaging apparatus according to any one of claims 1 to 10,
The back-illuminated imaging device reads out and accumulates charges accumulated in each of the plurality of first impurity diffusion layers, and according to the charges accumulated in the charge accumulation layer An imaging apparatus comprising a CMOS circuit that outputs a signal.

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