JPH04360578A - Solid-state image sensing element and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain a solid-state image sensing element which is easily driven and has small power consumption by reducing a capacity across electrodes of the sensing element. CONSTITUTION:In a two-phase drive type charge transfer element, a gap is provided between a charge transfer electrode 3 of a first layer and a charge transfer electrode 13 of a second layer, an impurity of a conductivity type opposite to that of a channel 2 is implanted from the gap to a potential barrier region 12 formed between the electrode 3 of the channel 2, a second impurity implanted region 12 is formed, and a potential of the channel of the gap fixed to a predetermined potential.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image sensor (image sensor) that consumes less power for driving and a method for manufacturing the same.

0002

2. Description of the Related Art As image sensors have become more highly integrated in recent years, the power consumption required to drive the image sensors has increased. As the integration density increases, the number of integrated pixels increases, and for example, a one-dimensional image sensor has 10,000 pixels and a die size of about 80 mm on the long side. Therefore, the internal electrode capacitance increases, resulting in a significant increase in power consumption due to high-speed driving. FIG. 3(a) is a diagram showing the structure of a charge transfer electrode inside a conventional two-phase CCD type image sensor. In the figure, 1 is, for example, a P-type semiconductor substrate, 2 is a buried channel (n-type impurity region) of a CCD formed in the P-type semiconductor substrate 1, and 3a to 3d are first layers formed of polysilicon or the like. Eye transfer electrode, 4a
4d is a second layer transfer electrode provided so as to partially cover the adjacent first layer transfer electrodes 3a to 3d, and 5 is a P for determining the direction of charge transfer in the two-phase drive CCD. This is a potential barrier region into which type impurities are introduced. however,
Normally, the potential barrier region is doped with an amount of impurity to control the potential, and the P type is doped with an amount of impurity that does not cause inversion. Further, 6a to 6c and 7a to 7c are the parasitic capacitances between the transfer electrodes 3 and 4 in the first and second layers, and 8 is the capacitance of the transfer electrodes to the substrate.

Next, the operation during driving will be explained. Figure 3
(b) shows the channel potential when no drive voltage is applied to the clocks φ1 and φ2. Further, Q in the figure schematically represents a signal charge. Furthermore, FIG. 3(c) is a potential diagram when a low-level drive current is applied to the clock φ1 and a high-level drive current is applied to φ2, and the signal charge under the electrode to which the clock φ1 is applied is It is schematically shown that φ2 is applied and a deeper potential is transferred under the electrode where it is formed.

[0004] The clock voltage and channel potential applied to the solid-state imaging device configured as described above are set so as to satisfy the following conditions. Vba<Vst<Vba+Vclk<Vst+
Vclk (1) Here, Vclk is the amplitude of the drive clock.

By the way, when driving an image sensor, the parasitic capacitance that poses a problem in terms of current consumption is the capacitance 7 between the electrodes.
a to 7c and the transfer electrode capacitance 8 to the substrate, but since the capacitance 8 to the transfer electrode is the capacitance to the substrate via the buried channel 2, it is usually a very small capacitance compared to the capacitance 7 between the electrodes. be. Note that the capacitances 6a to 6c between the electrodes are the same as those of the first and second layer transfer electrodes 3a (3b,...3d) during driving.
), 4a (4b, . . . 4d), so the same clock is supplied between them, so it does not contribute to power consumption.

[0006]

[Problems to be Solved by the Invention] Conventional solid-state image sensors are constructed as described above, and in order to reduce power consumption, two-phase clocks with different potentials are applied to the first and second clocks.
It was necessary to reduce the parasitic capacitance shown by 7a to 7c between the transfer electrodes of the layers. In order to reduce this capacitance, these two layers of electrodes 4a (4b, 4c) and 3b (4c,
It is necessary to reduce the overlap between 4d), but if the overlap disappears, potential unevenness will occur in the gap, leading to deterioration of transfer efficiency. For this reason, the manufacturing margin when forming the transfer electrodes is 1
It requires an electrode overlap of about ~1.5 μm, and therefore the parasitic capacitance between the two layers of electrodes as described above is reduced.
It was not possible to reduce it sufficiently.

The present invention has been made to solve the above-mentioned problems, and aims to obtain a solid-state image pickup device that can sufficiently reduce parasitic capacitance and consume less power, and also provides a method for manufacturing the same. The purpose is to

[0008]

[Means for Solving the Problems] In the solid-state image sensor according to the present invention, the transfer electrodes in the second layer are configured such that the same clock is applied and only the adjacent transfer electrodes in the first layer are covered. a potential that fixes the potential level between these electrodes to a predetermined value; A fixed area is provided.

Further, in the method for manufacturing a solid-state imaging device according to the present invention, impurities are implanted using the second layer transfer electrode and the first layer transfer electrode, which have non-overlapping regions, as a mask, and the barrier A potential fixing region is provided in the region.

0010

[Operation] In the solid-state imaging device of the present invention, the same clock is applied and the second layer transfer electrode is provided so as to cover only the adjacent first layer transfer electrode, and the second layer transfer electrode is provided so as to cover only the adjacent first layer transfer electrode. Since the overlap between the transfer electrode and the first layer transfer electrode to which different clocks are applied is eliminated, the parasitic capacitance between the electrodes to which different clocks are applied is reduced, and the overlap between the transfer electrode and the second layer transfer electrode is reduced. A potential fixing region that fixes the potential level between these electrodes to a predetermined value is provided in the barrier region between the adjacent transfer electrodes of the first layer to which different clocks are applied, so that the electrodes are spaced apart. No irregularities in the potential occur even when

Further, in the method of manufacturing a solid-state imaging device according to the present invention, impurity implantation is performed using the second layer transfer electrode and the first layer transfer electrode, which have non-overlapping regions, as a mask, and the barrier region is Since the potential fixing region is provided in the substrate, the potential fixing region can be formed with high accuracy.

0012

DESCRIPTION OF THE PREFERRED EMBODIMENTS A solid-state imaging device according to an embodiment of the present invention will be described below with reference to FIG. 1(a). In FIG. 1(a), the same reference numerals as in FIG. 3 indicate the same or corresponding parts, and 11
1 is an impurity implantation region for determining the transfer direction of the two-phase CCD, and 13 is a second layer transfer electrode, which is formed apart from the first layer transfer electrode to which an adjacent clock phase is applied. Further, 12 indicates transfer electrodes 13a (13b, 13c), 3b (3c, 3d) to which different clocks φ2 and φ1 are applied.
This is a second impurity implantation region (potential fixing region) for fixing the channel potential of the gap between the channels, and an amount of impurity is introduced to the extent that the surface of the buried channel 2 is inverted to P type. Further, 14 is the electrode parasitic capacitance between the different clock phases of φ1 and φ2, as shown in FIG. 3(a) above.
This corresponds to a capacity of 7. In order to simplify the explanation, descriptions of parasitic capacitances such as 6 and 8 shown in FIG. 3(a) are omitted here. In this way, a structure is realized in which electrodes of different clock phases do not overlap, and the parasitic capacitance between these electrodes can be reduced (7>14).

Next, the operation will be explained. Figure 1(b)
shows the channel potential when no driving voltage is applied to both electrodes (both are at low level). At this time, the channel potential must be set so as to satisfy the following conditions. Vba<Vst<Vpin
...(2)

FIG. 1(c) shows the clock φ
This figure shows the channel potential when a high-level drive voltage is applied to the electrode to which clock φ1 is applied, and a low-level drive voltage is applied to the electrode to which clock φ1 is applied. The region indicated by 12 is set in a pinning state by P-type impurities on the substrate surface, and its channel potential is kept at a constant potential (Vpin) regardless of the potential applied to both transfer electrodes to which clocks φ1 and φ2 are supplied. It's dripping. Therefore, under the driving conditions shown in FIG. 1(c), the signal charge Q that was under the electrode to which the clock φ1 is applied is transferred to the electrode to which the clock φ2 is applied. The applied clock amplitude and channel potential are set to satisfy the following equation in addition to equation (2). Vst<Vpin<Vba+Vclk...(
3)

Next, the manufacturing method will be explained using FIG. 2. First, as shown in FIG. 2(a), an N-type impurity is introduced into a P-type semiconductor substrate 1 to form a buried channel 2. Next, after forming a thin oxide film (not shown) to serve as a gate insulating film, a first layer of polysilicon transfer electrode 3 is formed (FIG. 2(b)). Thereafter, P-type impurities are implanted by ion implantation using the first layer polysilicon transfer electrode 3 as a mask to form a first impurity implanted region 11 serving as a potential barrier (FIG. 2(c)). After further forming a gate oxide film (not shown), the second layer polysilicon transfer electrode 13 is connected to the first layer transfer electrode 13 to which adjacent clocks of the same phase are applied, as shown in FIG. 2(d). It is formed so as to cover a part of the electrode. Finally, using the first layer transfer electrode 3 and the second layer transfer electrode 13 as masks, P-type impurities are introduced to form a second impurity implantation region 12. By using such a process, each impurity implantation region 11
, 12 can be formed in self-alignment with respect to the transfer electrodes, and a highly accurate device structure can be easily formed.

As described above, according to this embodiment, the clocks φ2 and φ1 of different phases are applied, and between the adjacent second and first layer transfer electrodes (for example, 13a and 3b), the second layer The eye transfer electrode 13a is connected to the same phase clock φ2.
is applied, and is formed so as to cover only the adjacent first layer transfer electrode 3a, and is separated from the first layer transfer electrode 3b, to which a different clock φ1 is applied, to prevent overlap between the electrodes. Parasitic capacitance 1 between electrode 13a and electrode 3b to which different clocks are applied since the wrap is eliminated
4a is reduced compared to the conventional one (14a<7a), and in the first impurity implanted region 11a in the gap region between the second transfer electrode 13a and the first layer transfer electrode 3b, the impurity between these electrodes is reduced. The potential level is set to a predetermined value Vpin (V
Since the second impurity implantation region 12a is provided which fixes ba<Vst<Vpin), even if the electrodes are separated, potential unevenness does not occur and highly efficient charge transfer can be performed.

Furthermore, the first layer transfer electrode (for example 3a) and the second layer transfer electrode (for example 13a) to which the clock φ2 of the same phase is applied, and the first layer transfer electrode to which the clock φ1 is applied The first impurity implantation region (for example, 1
In 1a), impurity implantation is performed using these first and second layer transfer electrodes as masks, and the second impurity implantation region (for example, 12a) is provided in a self-aligned manner, so high precision can be achieved with a simple method. It is possible to obtain a unique device structure.

In order to set the potential of the second impurity implanted region 12 to the conditions shown in equations (2) and (3) under the buried channel forming conditions, the steps shown in FIG.
d) At the time of introducing the P-type impurity in the step shown in d), the N-type impurity may also be introduced at the same time. That is, when the concentration of N-type impurities in the buried channel 2 is low, even if the second impurity implantation region 12 is provided in a shallow part of the surface, the impurity will not be implanted to the deep channel layer 2 that reaches the substrate 1 below. This is because the potential level of the channel layer 2 becomes higher than the potential of the second impurity region 12, and the condition of equation (2) may not be satisfied. However, by using N-type impurities in the process shown in Figure 2(d), (2)
It is possible to form the second impurity implanted region 12 that satisfies the conditions shown in the formula.

In the above embodiments, the semiconductor substrate is of P type, but the same effect can be obtained even when the semiconductor substrate is formed in a P well.

Furthermore, in the above embodiment, the two-phase clock driven C
Although a CD has been described, similar effects can be expected for a CCD driven by a clock other than two phases by using the above-mentioned electrode structure between adjacent electrodes to which different clocks are applied.

Furthermore, when forming a P-type buried channel on an N-type substrate, it is obvious that the same effect can be achieved by replacing all impurity types with P and N.

[0022]

As described above, according to the solid-state image sensing device of the present invention, the same clock is applied and the transfer electrodes in the second layer are transferred by covering only the adjacent transfer electrodes in the first layer. Since the overlap between the second layer transfer electrode and the first layer transfer electrode to which different clocks are applied is eliminated, the parasitic capacitance between the electrodes to which different clocks are applied is reduced. , and a potential fixing region that fixes the potential level between these electrodes to a predetermined value in the barrier region between the second layer transfer electrode and the first layer transfer electrode that is adjacent to and to which a different clock is applied. Because of this provision, potential unevenness does not occur even if the electrodes are spaced apart, and a solid-state imaging device can be obtained that consumes less power for driving and can perform highly efficient charge transfer. There is.

Further, in the method for manufacturing a solid-state imaging device according to the present invention, impurity implantation is performed using the second layer transfer electrode and the first layer transfer electrode, which have non-overlapping regions, as a mask, and the barrier region is Since the potential fixing region is provided in the semiconductor device, the potential fixing region can be easily formed with high precision, and the manufacturing precision of the device can be improved.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a charge transfer section of a solid-state imaging device according to an embodiment of the present invention and a diagram showing channel potential.

FIG. 2 is a diagram showing a method of manufacturing a solid-state image sensor according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view of a charge transfer section of a conventional solid-state image sensor and a diagram showing channel potential.

[Explanation of symbols]

1 Semiconductor substrate 2 Buried channel region 3
First layer transfer electrodes 4, 13 Second layer transfer electrodes 5, 11 Potential barrier regions 7, 14 Parasitic capacitance

Claims (3)

[Claims] 1. A channel layer of a second conductivity type formed on a semiconductor substrate of a first conductivity type, a first layer transfer electrode disposed on the substrate, and one of the first layer transfer electrodes. solid-state imaging comprising: a second layer transfer electrode provided so as to cover the second layer; and a barrier region provided in the channel layer and serving as a potential barrier between electrodes to which different clocks of the transfer electrode are applied. In the device, the second layer transfer electrode is formed so as to cover only the adjacent first layer transfer electrode to which the same clock is applied;
A potential fixing region for fixing the potential level between these electrodes to a predetermined value is provided in the barrier region between the first layer transfer electrode adjacent to the first layer transfer electrode to which a different clock is applied. A solid-state image sensor characterized by: 2. The method for manufacturing a solid-state image sensor according to claim 1, wherein the first layer of transfer electrodes is covered only above the first layer of transfer electrodes to which the same clock is applied. A step of forming a second layer transfer electrode, and implanting a first conductivity type impurity into the barrier region using the first and second layer transfer electrodes as a mask to form a potential fixing region in the barrier layer. 1. A method for manufacturing a solid-state image sensor, the method comprising: forming a solid-state image sensor. 3. The solid-state imaging device according to claim 2, wherein the step of forming a potential fixing region in the barrier layer is performed by adding an impurity of a second conductivity type to an impurity of a first conductivity type. Method of manufacturing elements.