JP2008244098A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP2008244098A JP2008244098A JP2007081760A JP2007081760A JP2008244098A JP 2008244098 A JP2008244098 A JP 2008244098A JP 2007081760 A JP2007081760 A JP 2007081760A JP 2007081760 A JP2007081760 A JP 2007081760A JP 2008244098 A JP2008244098 A JP 2008244098A
- Authority
- JP
- Japan
- Prior art keywords
- concentration impurity
- impurity region
- low
- layer
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 55
- 239000012535 impurity Substances 0.000 claims abstract description 141
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 31
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 31
- 230000005669 field effect Effects 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims description 24
- 239000002184 metal Substances 0.000 abstract description 12
- 230000015572 biosynthetic process Effects 0.000 abstract description 7
- 239000010408 film Substances 0.000 description 32
- 238000000034 method Methods 0.000 description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 6
- 229910019001 CoSi Inorganic materials 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 5
- 238000000206 photolithography Methods 0.000 description 5
- 230000003071 parasitic effect Effects 0.000 description 3
- 238000002955 isolation Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/13—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body combined with thin-film or thick-film passive components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/20—Resistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Thin Film Transistor (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
【解決手段】抵抗回路120,130,140は、SOI層103内に形成された、低濃度不純物領域すなわち抵抗素子121,131,141および高濃度不純物領域すなわち抵抗用配線112,122,132,142を有する。高濃度不純物領域112,122,132,142は、一方の端部が低濃度不純物領域121,131,141の端部に接し、且つ、他方の端部が他の素子(電界効果トランジスタ、他の抵抗素子等)の不純物領域と接する。さらに、高濃度不純物領域112,122,132,142上には、シリサイド層118,123,133,143が、選択的に形成される。コンタクトやメタル配線を用いずに配線できるのでレイアウトが容易であり、また、シリサイド層を選択的に形成するので高特性である。
【選択図】図1
Description
以下、この発明の第1の実施形態に係る半導体装置について、図1〜図3を用いて説明する。
次に、第2の実施形態に係る半導体装置について、図4を用いて説明する。
101 シリコン基板
102 酸化膜
103 SOI層
110 電界効果トランジスタ
111,112 高濃度不純物領域
113 ゲート絶縁膜
114 ゲート電極
115 サイドウォール
116 チャネル形成領域
117,118,119 シリサイド層
120,130,140 抵抗回路
121,131,141 低濃度不純物領域(抵抗素子)
122,132,142 高濃度不純物領域(抵抗素子用配線)
123,133,143 シリサイド層
150 絶縁膜
160,170 コンタクト層
180,190 メタル配線
Claims (7)
- SOI基板の半導体層に形成された抵抗素子を有する半導体装置であって、
前記半導体層内に形成された、前記抵抗素子としての低濃度不純物領域と、
前記半導体層内に形成され、一方の端部が該低濃度不純物領域の端部に接し、且つ、他方の端部が他の素子の不純物領域と接する、抵抗素子用配線としての高濃度不純物領域と、
前記高濃度不純物領域上に選択的に形成されたシリサイド層と、
を有することを特徴とする半導体装置。 - 前記SOI基板の表面を覆う絶縁膜を貫いて前記シリサイド層と接するように形成された、コンタクト層をさらに備えることを特徴とする請求項1に記載の半導体装置。
- 前記高濃度不純物領域が、前記半導体層に形成された電界効果トランジスタの高濃度不純物領域と、共通化されたことを特徴とする請求項1または2に記載の半導体装置。
- 前記高濃度不純物領域が、前記半導体層に形成された他の前記抵抗素子の前記高濃度不純物領域と共通化されたことを特徴とする請求項1または2に記載の半導体装置。
- SOI基板の半導体層に形成された抵抗素子を有する半導体装置であって、
前記半導体層内に形成された、前記抵抗素子としての低濃度不純物領域と、
前記半導体層内に形成され、該低濃度不純物領域の対応する端部に接する、抵抗素子用配線としての第1、第2高濃度不純物領域と、
前記半導体層上に形成され、前記第1、第2高濃度不純物領域の一方と前記低濃度不純物領域とを空乏層によってそれぞれ二分離するためのゲート電極と、
を有することを特徴とする半導体装置。 - 前記ゲート電極として、
前記低濃度不純物領域および前記第1低濃度不純物領域を空乏層によってそれぞれ二分離するための第1ゲート電極と、
前記低濃度不純物領域および前記第2低濃度不純物領域を空乏層によってそれぞれ二分離するための第2ゲート電極と、
を交互に形成したことを特徴とする請求項5に記載の半導体装置。 - 前記ゲート電極を複数有し、且つ、これらのゲート電極が前記空乏層の生成と非生成とを個別に選択できるように構成されたことを特徴とする請求項5または6に記載の半導体装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007081760A JP4344390B2 (ja) | 2007-03-27 | 2007-03-27 | 半導体装置 |
US12/076,053 US20080237801A1 (en) | 2007-03-27 | 2008-03-13 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007081760A JP4344390B2 (ja) | 2007-03-27 | 2007-03-27 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008244098A true JP2008244098A (ja) | 2008-10-09 |
JP4344390B2 JP4344390B2 (ja) | 2009-10-14 |
Family
ID=39792791
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007081760A Active JP4344390B2 (ja) | 2007-03-27 | 2007-03-27 | 半導体装置 |
Country Status (2)
Country | Link |
---|---|
US (1) | US20080237801A1 (ja) |
JP (1) | JP4344390B2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPWO2012029915A1 (ja) * | 2010-09-02 | 2013-10-31 | シャープ株式会社 | トランジスタ回路、フリップフロップ、信号処理回路、ドライバ回路、および表示装置 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4987309B2 (ja) * | 2005-02-04 | 2012-07-25 | セイコーインスツル株式会社 | 半導体集積回路装置とその製造方法 |
-
2007
- 2007-03-27 JP JP2007081760A patent/JP4344390B2/ja active Active
-
2008
- 2008-03-13 US US12/076,053 patent/US20080237801A1/en not_active Abandoned
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPWO2012029915A1 (ja) * | 2010-09-02 | 2013-10-31 | シャープ株式会社 | トランジスタ回路、フリップフロップ、信号処理回路、ドライバ回路、および表示装置 |
JP5579855B2 (ja) * | 2010-09-02 | 2014-08-27 | シャープ株式会社 | トランジスタ回路、フリップフロップ、信号処理回路、ドライバ回路、および表示装置 |
US9030237B2 (en) | 2010-09-02 | 2015-05-12 | Sharp Kabushiki Kaisha | Transistor circuit, flip-flop, signal processing circuit, driver circuit, and display device |
Also Published As
Publication number | Publication date |
---|---|
JP4344390B2 (ja) | 2009-10-14 |
US20080237801A1 (en) | 2008-10-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9660022B2 (en) | Semiconductive device with a single diffusion break and method of fabricating the same | |
JP5703790B2 (ja) | 半導体装置及びその製造方法 | |
CN106992173B (zh) | 包括场效应晶体管的半导体器件 | |
JP6316725B2 (ja) | 半導体装置 | |
JP2010141107A (ja) | 半導体装置及びその製造方法 | |
JP5535486B2 (ja) | 絶縁体上に半導体が設けられた構造(soi)を有するボディコンタクト素子の形成方法及び装置 | |
JP2009164609A (ja) | ディープトレンチ構造を有する半導体素子及びその製造方法 | |
JPWO2005020325A1 (ja) | 半導体装置及びその製造方法 | |
JP2006253648A (ja) | 半導体装置及び半導体装置の製造方法 | |
JP5743831B2 (ja) | 半導体装置 | |
US8823137B2 (en) | Semiconductor device | |
JP4579512B2 (ja) | 半導体装置およびその製造方法 | |
JP2008085117A (ja) | 半導体装置およびその製造方法 | |
JP4344390B2 (ja) | 半導体装置 | |
JP2008060537A (ja) | 半導体装置及びその製造方法 | |
JP2005209792A (ja) | 半導体装置 | |
TW201332121A (zh) | 半導體裝置及用於製造半導體裝置之方法 | |
CN108074925B (zh) | 半导体器件 | |
JP4887662B2 (ja) | 半導体装置およびその製造方法 | |
JP6707917B2 (ja) | 半導体装置及びその製造方法 | |
JP2005109400A (ja) | 半導体集積回路 | |
JP2007335463A (ja) | 静電気放電保護素子および半導体装置 | |
US9640629B1 (en) | Semiconductor device and method of manufacturing the same | |
JP2009059894A (ja) | 半導体装置 | |
JP2009188200A (ja) | 半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20080926 |
|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A712 Effective date: 20081218 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20090115 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20090203 |
|
RD03 | Notification of appointment of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7423 Effective date: 20090226 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20090312 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20090407 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20090602 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20090623 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20090710 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120717 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 4344390 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120717 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130717 Year of fee payment: 4 |
|
S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
S533 | Written request for registration of change of name |
Free format text: JAPANESE INTERMEDIATE CODE: R313533 |
|
S533 | Written request for registration of change of name |
Free format text: JAPANESE INTERMEDIATE CODE: R313533 |
|
S533 | Written request for registration of change of name |
Free format text: JAPANESE INTERMEDIATE CODE: R313533 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |