JP2008232962A - Semiconductor testing method and apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To eliminate the influence on a test, when then output signal of an output terminal of a device under test is not certain as to whether it is "H" or "L". <P>SOLUTION: A semiconductor testing method includes steps of inputting a test signal to each input terminal of the device under test, comparing and collating output signals of "H" or "L" from m output terminals of the device with m "H" or "L" expected values, and determining the device as "good", when the collating results of the output signals of the m output terminals of the device "coincide" with the m expected values respectively and determining the device as "defective" in other cases. An intermediate level "Z", between "H" and "L", is further prepared as the expected value, and the collating results by using "Z" are defined to "coincide" for any output signals. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor test method and apparatus for performing a function test of a device under test (semiconductor device), and particularly when the device under test has a specific output terminal for outputting an indeterminate signal, the indefinite signal is tested. The present invention relates to a semiconductor test method and apparatus that do not affect the results.

  As shown in FIG. 4, a semiconductor test apparatus for performing a function test of a device under measurement generally has devices under test 40A and 40B (in FIG. 4, two devices under test are shown for simplicity). In general, several to several tens are targeted), and n test signals are output from the test signal output terminals P1 to Pn of the test signal generation circuit 51 of the tester 50, A common input is applied to the input terminals IN1 to INn of the devices under test 40A and 40B, and m output signals respectively processed within the devices under test 40A and 40B are extracted from the output terminals OUT1 to OUTm. Are input to the input terminals Y11 to Y1m and Y21 to Y2m of the measurement circuit 52 of the tester 50, and the expected values set in the measurement circuit 52 are compared with those output signals. , The comparison result is "pass" the the device under test if the expected values, it is an "fail" if not.

  However, in the semiconductor test apparatus shown in FIG. 4, the test signal input terminals (input terminals corresponding to the input terminals IN1 to INn) of the performance board 30 may be shared by the devices under test 40A and 40B. However, terminals corresponding to the output terminals OUT1 to OUTm of the devices under test 40A and 40B are individually provided, and terminals corresponding to the input terminals Y11 to Y1m and Y21 to Y2m of the measurement circuit 52 of the tester 50 are also provided individually. Therefore, the number of terminals is required by “the number of output terminals of the device under test × the number of devices under test”, and the number of output terminals of the performance board 30 and the number of input terminals of the tester 50 are increased. The scale of the device increases.

  In view of this, a technique has been proposed in which the number of output terminals of the performance board and the number of input terminals of the tester are reduced by using a measured terminal reduction circuit (see, for example, Patent Document 1).

  FIG. 5 is a diagram showing a semiconductor test apparatus adopting this method. In this semiconductor test apparatus, the number of measured terminal reduction circuits 80A and 80B is mounted on the performance board 60 by the number of measured devices 40A and 40B (two in the case of FIG. 4), and the test signal generating circuit 71 of the tester 70 is mounted. N test signals from the test signal output terminals P1 to Pn are commonly input to the input terminals IN1 to INn of the devices under test 40A and 40B, and the test signal generation circuit 71 of the tester 70 is used in the terminal under test reduction circuit 80A. Expected values output from the output terminals S1 to Sm of the device and the output signals output from the output terminals OUT1 to OUTm of the device under test 40A are compared. Expected values output from the expected value output terminals S1 to Sm of the circuit 71 and output terminals OUT1 to OUTm of the device under test 80B. The received output signals are compared, and a “pass” or “fail” signal as a result of the comparison is generated in the measured terminal reduction circuits 80A and 80B, and the input terminal X1 of the pass / fail counting circuit 72 of the tester 70 is generated. , X2.

  FIG. 6 is a diagram showing an internal configuration of the measured terminal reduction circuit 80A described in FIG. Data output from the output terminals OUT1 to OUTm of the device under test is captured in the flip-flops 811 to 81m by the clock CK output from the tester 70, and the captured data is output to the expected value output terminals in the XOR circuits 821 to 82m. The output is compared with the expected value output from S <b> 1 to Sm. When “match”, the output is “L”, and when “mismatch” is “H”, the output is input to the NOR circuit 83. Therefore, the output of the NOR circuit 83 when the output signals of the output terminals OUT1 to OUTm of the device under test 80A and the expected values of the expected value output terminals S1 to Sm are “mismatch” (= “H”). “L” indicating “fail” is input to the input terminal X 1 of the pass / fail counting circuit 54. The same applies to the measured terminal reduction circuit 80B.

The semiconductor test apparatus shown in FIG. 5 can significantly reduce the number of output terminals on the performance board 60 and the number of input terminals on the tester 70 as compared with the semiconductor test apparatus shown in FIG. Thus, the number of devices under simultaneous measurement can be increased.
JP 2003-84045 A

  However, the semiconductor test apparatus shown in FIG. 5 has no problem when the output signals of the output terminals OUT1 to OUTm of the devices under test 40A and 40B can completely estimate either “H” or “L”. However, since there are cases where the output cannot be estimated, for example, when there are flip-flops that are not initialized when the power is turned on in the devices under test 40A, 40B, it is difficult to apply to general test vectors. If a vector for completely determining the internal state is applied first, it is possible to perform the test by this method, but this is not preferable because the test time increases.

  The object of the present invention is to treat the result of comparison with the expected value of the signal at the indeterminate output terminal as “match” when the output signal at the output terminal of the device under test is indefinite. Thus, it is an object of the present invention to provide a semiconductor test method and apparatus in which the influence on the test of an indefinite output terminal is eliminated.

In order to achieve the above object, a semiconductor test method according to a first aspect of the present invention is such that a test signal is input to each input terminal of a device under test, and “H” or “ The “L” output signal is compared with the m expected values of “H” or “L”, and the output signal of the m output terminals of the device under test is compared with the m expected values. In the semiconductor test method in which the device under test is “passed” and the other devices are “failed” when “match” respectively, the expected value is an intermediate level “Z” between “H” and “L”. "Is further prepared, and the result of the collation performed using the" Z "is set as the" match "regardless of the output signal.
According to a second aspect of the present invention, in the semiconductor test method according to the first aspect, the output value of the m output terminals of the device to be measured is “Z” as the expected value for an output terminal whose output signal is indefinite. It is characterized by using.
According to a third aspect of the present invention, there is provided a semiconductor test apparatus including an “H” or “L” output signal of m output terminals of a device under test, to which a test signal is input to each input terminal, and “H” and “L”. M comparison means for comparing each of m expected values, and when all the m comparison means output “match”, the device under test is set to “pass”, and the others are set to “fail” In the semiconductor test apparatus including a determination means for outputting a signal "", an intermediate level "Z" between "H" and "L" is further prepared as the expected value, and the m comparison means are When the expected value is “Z”, which is an intermediate level between “H” and “L”, the “match” is output regardless of the output signal of the output terminal of the device under measurement. .
According to a fourth aspect of the present invention, in the semiconductor test apparatus according to the third aspect, the m number of comparison means are set such that an intermediate level between the “Z” and the “H” is set as a first threshold value. 1 comparator, a second comparator in which an intermediate level between the “Z” and the “L” is set as a second threshold, an inverted signal of the output signal of the output terminal of the device under measurement, A first AND circuit that takes an AND logic of an output signal of the first comparator; a second AND that takes an AND logic of an output signal of an output terminal of the device under test and an inverted signal of the output signal of the second comparator; And an OR circuit that takes OR logic of the first and second AND circuits.

  According to the present invention, when an intermediate potential “Z”, which is an intermediate level between “H” and “L”, is given as an expected value of a specific output terminal, a comparison result with the expected value of that output terminal Is always “coincidence”, and therefore, when the indeterminate output terminal is collated, by giving this intermediate potential “Z” as an expected value, the test result is not adversely affected.

  FIG. 1 shows a configuration of a measured terminal reduction circuit 10 according to one embodiment of the present invention. This measured terminal reduction circuit 10 is used in place of the measured terminal reduction circuits 80A and 80B shown in FIG.

  In the measured terminal decreasing circuit 10 of FIG. 1, reference numeral 11 denotes a flip-flop, and an output signal output from the output terminal OUT1 of the measured device is captured by the clock CK output from the test signal generating circuit 71 of the tester 70 of FIG. . 12 is a first comparator that compares the expected value output from the expected value output terminal S1 of the test signal generation circuit 71 with the first threshold voltage VH, and 13 is a second comparator that is also compared with the second threshold voltage VL. It is a comparator. 14 is an AND circuit that takes the AND logic of the inverted signal of the Q output of the flip-flop 11 and the output of the comparator 12, and 15 is an AND circuit that takes the AND logic of the inverted signal of the Q output of the flip-flop 11 and the output of the comparator 13. is there. Reference numeral 16 denotes an OR circuit that takes the OR logic of both AND circuits 14 and 15.

  The flip-flop 11, the comparators 12 and 13, the AND circuits 14 and 15, and the OR circuit 16 are set as one set, which is arranged in the number of output terminals OUT1 to OUTm of the device under test, that is, m sets. The output of the OR circuit 16 is input to the NOR circuit 17 which is a determination means. When the measured terminal decreasing circuit 10 is used in place of the measured terminal decreasing circuit 80A of FIG. 5, the output of the NOR circuit 17 is input to the input terminal X1 of the pass / fail counting circuit 71 of the tester 70 of FIG. . When used in place of the measured terminal decreasing circuit 80B, the output of the NOR circuit 17 is input to the input terminal X2 of the pass / fail counting circuit 71.

  FIG. 2 is a diagram showing a configuration of the expected value output circuit 20 newly provided at the expected value output terminal S1 of the test signal generation circuit 71 of the tester 70 of FIG. Reference numeral 21 denotes a driver that amplifies an expected value signal. The driver 21 outputs a voltage VIH indicating “H” and a voltage VIL indicating “L”, and outputs the expected value output terminal S1 via the analog switch 22. Output to. One of the analog switches 22 and 23 is turned on by the switching signal CTR and the inverter 24, and the other is turned off. When the analog switch 23 is turned on, an intermediate voltage VT indicating “Z” is output from the output terminal S1. The expected value output circuits corresponding to the other expected value output terminals S2 to Sm have the same configuration.

  FIG. 3 is a diagram showing signal voltage levels handled in this embodiment. VIL and VIL are “H” and “L” voltages output to the test signal output terminals P1 to Pm and the expected value output terminals S1 to Sm, respectively. The intermediate voltage VT indicating “Z” is the voltages VIH and VIL. The intermediate value of The first threshold voltage VH is a voltage between the voltages VT and VIH, and the second threshold voltage VL is a voltage between the voltages VT and VIL.

  Next, a case where the expected value verification that the output terminal OUT1 of the device under test is “H” is performed will be described. At this time, the expected value of the expected value output terminal S1 of the test signal generating circuit 71 of the tester 70 is set to “H”. As shown in FIG. 3, the voltage of “H” is higher than the first threshold voltage VH of the comparator 12 and the second threshold voltage VL of the comparator 13. 13 outputs “H”. At this time, if the output terminal OUT1 of the device under test is “H”, the Q output of the flip-flop 11 is “H”, and the outputs of the AND circuits 14 and 15 are “L”. Therefore, the output of the OR circuit 16 is also “L”, and the output terminal OUT1 is “matched”. However, if the output terminal OUT1 of the device under test is “L”, the Q output of the flip-flop 11 is “L”, the output of the AND circuit 14 is “H”, and the output of the AND circuit 15 is “L”. " Therefore, the output of the OR circuit 16 becomes “H”, and the output terminal OUT1 becomes “mismatch”.

  Next, the case where the expected value verification that the output terminal OUT1 of the device under test is “L” is performed will be described. At this time, the expected value of the expected value output terminal S1 of the test signal generating circuit 71 of the tester 70 is set to “L”. As shown in FIG. 3, this “L” voltage is lower than the first threshold voltage VH of the comparator 12 and the second threshold voltage VL of the comparator 13. 13 outputs “L”. At this time, if the output terminal OUT1 of the device under test is “L”, the Q output of the flip-flop 11 is “L”, and the outputs of the AND circuits 14 and 15 are “L”. Therefore, the output of the OR circuit 16 is also “L”, and the output terminal OUT1 is “matched”. However, if the output terminal OUT1 of the device under test is “H”, the Q output of the flip-flop 11 is “H”, the output of the AND circuit 14 is “L”, and the output of the AND circuit 15 is “H”. " Therefore, the output of the OR circuit 16 becomes “H”, and the output terminal OUT1 becomes “mismatch”.

  Next, a case where expected value matching is not performed for the output terminal OUT1 of the device under measurement will be described. At this time, the expected value of the expected value output terminal S1 of the test signal generation circuit 71 of the tester 70 is set to “Z” (= VT). As shown in FIG. 3, the voltage VT is lower than the first threshold voltage VH of the comparator 12 and higher than the second threshold voltage VL of the comparator 13, and the comparator 12 sets “L”. The comparator 13 outputs “H”. Therefore, the AND circuits 14 and 15 output “L” regardless of whether the Q output of the flip-flop 11 is “H” or “L”. Therefore, the output of the OR circuit 16 is also “L”. That is, at this time, expected value matching is not performed, and the output terminal OUT1 is handled in the same way as “match”.

  The above is for the expected value matching of the output terminal OUT1 of the device under test, but the expected value matching is also performed for the other output terminals OUT2 to OUTm at the same time, and these matching results are input to the NOR circuit 17. . When the output of the OR circuit 16 is “L” for all the output terminals OUT1 to OUTm of the device under test, the output of the NOR circuit 17 is “H”. When used in place of the measured terminal decreasing circuit 80A, “H” (= “match”) is input to the input terminal X1 of the pass / fail counting circuit 72 of the tester 70.

It is a block diagram which shows the structure of the to-be-measured terminal reduction circuit mounted in the performance board of the semiconductor testing apparatus of one Example of this invention. It is a block diagram which shows the structure of the expected value output circuit of the test signal generation circuit of a tester. It is explanatory drawing of voltage VIH, VIL, VT, VH, VL. It is a block diagram which shows the structure of the conventional semiconductor test apparatus. It is a block diagram which shows the structure of the semiconductor test apparatus of another conventional example. FIG. 6 is a block diagram showing an internal configuration of a measured terminal reduction circuit described in FIG. 5.

Explanation of symbols

10, 80A, 80B: measured terminal reduction circuit 20: expected value output circuit 30, 60: performance board 40A, 40B: measured device 50, 70: tester

Claims (4)

A test signal is input to each input terminal of the device under test, and the “H” or “L” output signal of the m output terminals of the device under test is set to the m expected values of “H” or “L”. When the comparison result of each of the output signals of the m output terminals of the device to be measured and the m expected values is “match”, the device to be measured is “passed”, and the rest In the semiconductor test method to be “Fail”,
As the expected value, “Z” at an intermediate level between “H” and “L” is further prepared, and the result of collation performed using the “Z” is the “match” regardless of the output signal. A semiconductor test method characterized by the above. The semiconductor test method according to claim 1,
A semiconductor test method, wherein “Z” is used as the expected value for an output terminal with an indefinite output signal among the m output terminals of the device under test. M for comparing “H” or “L” output signals of m output terminals of the device under test whose test signals are input to the respective input terminals with m expected values of “H” and “L”, respectively. And a determination means for outputting a signal indicating that the device under test is “pass” and the others are “fail” when all of the m comparison means output “match”. In semiconductor testing equipment
As the expected value, the intermediate level “Z” between “H” and “L” is further prepared,
When the expected value is “Z”, which is an intermediate level between “H” and “L”, the m comparison means determine the “match” regardless of the output signal of the output terminal of the device under test. A semiconductor testing apparatus characterized by outputting. 4. The semiconductor test apparatus according to claim 3, wherein the m number of comparison means are:
A first comparator in which an intermediate level between “Z” and “H” is set as a first threshold, and an intermediate level between “Z” and “L” is set as a second threshold. A second AND circuit, a first AND circuit that takes an AND logic of the inverted signal of the output signal of the output terminal of the device under test and the output signal of the first comparator, and the output terminal of the device under test And a second AND circuit that takes an AND logic of an inverted signal of the output signal of the second comparator, and an OR circuit that takes an OR logic of the first and second AND circuits. Semiconductor test equipment.

Images