JP2008224585A - Semiconductor tester - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor tester inexpensively performing parallel tests of many DUTs. <P>SOLUTION: The semiconductor tester including a pin electronics substrate 11 applying a test signal to the plurality of DUTs 13 to measure the signal output from each DUT, includes a pin expansion board 14 distributing a serial test signal outputted from the pin electronics substrate 11 to each DUT and parallel/serial converting the signal output from each DUT. The pin electronics substrate 11 parallel/serial converts the serial signal output from the pin expansion board 14. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor test apparatus such as an IC tester for measuring a plurality of devices under test (DUT) in parallel.

  In general, a semiconductor test apparatus gives a test signal to an IC, LSI or the like to be tested (DUT), measures the output of the DUT, and determines whether the DUT is good or bad. The semiconductor test apparatus has a pin electronics board (hereinafter referred to as a pin electronics board) composed of a combination of a driver circuit and a comparator circuit in a test head, where test signal output and DUT evaluation are performed.

  FIG. 4 is a block diagram showing the configuration of a conventional pin electronics board of an IC tester. The pin electronic board 1 is connected to a DUT group 3 composed of n DUTs via n cables 2. The waveform generation circuit 11 outputs n test signals for n DUTs in parallel. The driver / comparator 12 drives each test signal output from the waveform generation circuit with n drivers, and compares the signal output from the DUT group 3 with a logic threshold value with n comparators. The relay 13 controls the connection between the driver / comparator 12 and the pin 14. The n cables 2 connect the pins 14 composed of n pins to the DUT group 3. The comparison circuit 15 logically compares the n logic signals output from the comparator of the driver / comparator 12 with an expected value to determine pass / fail. Here, in the driver / comparator 12 and the relay 13, each element of the pin 14 corresponds to each DUT of the DUT group 3 on a one-to-one basis.

  The operation of the apparatus of FIG. 4 will be described below. A plurality of the same test signals output in parallel from the waveform generation circuit 11 are driven by the driver of the driver / comparator 12, and each DUT of the DUT group 3 is connected via the pin 14 and the cable 2 with the relay 13 closed. To be applied. As a result, the signal output from each DUT (DUT1, DUT2,... DUTn) of the DUT group 3 is compared with the threshold value in each comparator of the driver / comparator 12 via the cable 2, the pin 14, and the relay 13. The The logical signal output from each comparator is logically compared with an expected value by the comparison circuit 15, and pass / fail judgment is performed for each DUT in the DUT group 3.

  Prior art documents related to semiconductor test equipment include the following.

JP 2003-139817 A

  In the conventional semiconductor test apparatus, waveforms can be applied or acquired only to the same number of DUTs as the number of pins 14 of the pin elevator board 1. For this reason, in the case where a large number of DUTs are tested in parallel, there is a problem that the hardware increases correspondingly and the cost becomes high.

  An object of the present invention is to provide a semiconductor test apparatus that can perform a parallel test of a large number of DUTs at low cost.

In order to achieve such a problem, a semiconductor test apparatus according to the invention described in claim 1 is provided.
A semiconductor test apparatus having a pin electronics substrate that applies a test signal to a plurality of DUTs and logically compares parallel logic signals based on signals output from the respective DUTs with expected values to perform pass / fail judgment,
A pin expansion board that distributes the test signal output in series from the same pin of the pin electronics board to each DUT and converts a parallel logic signal based on the signal output from each DUT into a serial logic signal;
The pin electronics board converts a serial logic signal output from the pin expansion board via the pin into a parallel logic signal.

The invention according to claim 2
The semiconductor test apparatus according to claim 1,
The pin expansion board is
A distribution circuit for distributing the test signal to the DUTs;
A comparator for level comparison of signals output in parallel from each DUT;
A parallel / serial conversion circuit for converting a parallel logic signal output from the comparator into a serial logic signal;
The pin electronics substrate is
A waveform generation circuit for generating the test signal;
And a serial / parallel conversion circuit for converting the serial logic signal output from the pin expansion board into a parallel logic signal.

The invention described in claim 3
The semiconductor test apparatus according to claim 2,
Each of the parallel / serial conversion circuit and the serial / parallel conversion circuit includes N flip-flop circuits,
The distribution circuit distributes the test signal to N DUTs.

  As is apparent from the above description, according to the present invention, a test signal is applied to a plurality of DUTs, and a parallel logic signal based on the signal output from each DUT is logically compared with an expected value to pass / fail. A semiconductor test apparatus having a pin electronics board for performing determination, wherein the test signal output in series from the same pin of the pin electronics board is distributed to each DUT, and parallel based on the signal output from each DUT A pin expansion board for converting a logic signal into a serial logic signal, wherein the pin electronics board converts a serial logic signal output from the pin expansion board via the pin into a parallel logic signal, thereby converting a plurality of logic signals into parallel logic signals. It is possible to provide a semiconductor test apparatus capable of performing DUT parallel testing at low cost.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing the configuration of an example of a semiconductor test apparatus according to an embodiment of the present invention. Here, a case where four DUTs are driven by one pin output from a pin electronics board is shown. The pin electronics board 11 is connected to a pin expansion board 14 via a cable 12 (coaxial cable), and is connected to four DUT pins of the DUT group 13 via four pins parallel to the pin 144 of the pin expansion board 14. The When testing a large number of DUTs in parallel, a plurality of such configurations are used corresponding to the number of pins 114 from the pin electronics board 11. The cable 15 is a coaxial cable for sending a timing signal from the pin electronics board 11 to the pin expansion board 14.

The pin electronic board 11 sequentially outputs the same test signals for the four DUTs serially (in series in time), and outputs the serial test signals to the cable 2 and the logic signals via the cables 2. I / O changeover switch 116 for switching between inputs, the pin 114 to which the output from the I / O changeover switch 116 is connected, the cable 12, the pin 114, and the I / O changeover switch 116 are input from the pin expansion board 14 in series. A serial / parallel conversion circuit (hereinafter referred to as a serial / para conversion circuit) 117 including four flip-flop circuits for converting a logical signal into a parallel logical signal, and a parallel logical signal output from the serial / para conversion circuit 117 are expected values. Comparison circuit 115 for determining pass / fail compared to the above and each flip-flop of serial / para conversion circuit 117 A timing generation circuit 118 that provides a parallel timing signal in accordance with a test rate to the circuit, and a parallel / serial conversion that converts the parallel timing signal output from the timing generation circuit 118 into a serial timing signal and outputs the serial timing signal to the cable 15 The circuit 119 is configured.

The pin expansion board 14 inputs a serial test signal via the I / O changeover switch 146 and the I / O changeover switch 146 for switching between a serial test signal input via the cable 2 and a serial logic signal output to the cable 2. A driver 142D composed of four drivers, four parallel signals output from each driver of the DUT group 13 and a relay 143 that distributes four parallel signals output from the driver 142D to each DUT of the DUT group 13 by four relays Is input via four relays of the relay 143 and is compared with a predetermined level (threshold), the comparator 142C is composed of four comparators, and the parallel logic signal output from the comparator 142C is converted into a serial logic signal to obtain I / O A parallel / serial circuit comprising four flip-flop circuits that are output to the O selector switch 146. A serial conversion circuit (hereinafter referred to as a para / serial conversion circuit) 147 and a serial timing signal sent via the cable 15 are converted to provide parallel timing signals to each flip-flop circuit of the para / serial conversion circuit 147. / Para conversion circuit 149.

Further, the four relays on the driver side of the relay 143 constitute a distribution circuit that distributes the serial test signal output from the pin electronics board 11 to each DUT in parallel.

  The operation of the apparatus of FIG. 1 will be described below. The serial test signal output from the waveform generation circuit 111 is input to the I / O changeover switch 146 of the pin expansion board 14 via the I / O changeover switch 116, the pin 114 and the cable 12. The serial test signal output from the I / O changeover switch 146 is distributed to each DUT of the DUT group 13 by a relay 143 that drives four drivers 142D and opens and closes at a predetermined timing. The four parallel signals output from each DUT of the DUT group 13 are input to the comparator 142C via the relay 143, and the level is compared with a predetermined threshold value. The parallel signal composed of the logic signals output from each comparator of the comparator 142C is converted into a serial logic signal by the para / serial conversion circuit 147, and is sent to the pin electronics board 11 via the cable 12 via the I / O changeover switch 146. Sent. The serial logic signal input from the pin expansion board 14 is input to the serial / para conversion circuit 117 via the pin 114 and the I / O changeover switch 116, and is adjusted to the test rate by the timing signal output from the timing generation circuit 118. It is converted into a parallel logic signal at the timing. The parallel logic signal output from the serial / para conversion circuit 117 is logically compared with an expected value by the comparison circuit 115 to determine pass / fail.

  FIG. 2 is a time chart showing timing signals output from the timing generation circuit 118. The serial logic signal input to the serial / para conversion circuit 117 is latched in the order of S1, S2, S3, and S4, and converted into a parallel logic signal. Therefore, the logic signal of each DUT is input to a separate terminal of the comparison circuit 115, and pass / fail judgment is performed in parallel.

  According to the semiconductor test apparatus configured as described above, when the same waveform signal is input from the pin electronics board and the signal output from the DUT is to be determined, the number of I / O pins of the pin electronics board is quadrupled. Since it can be increased, parallel testing of a large number of DUTs can be performed inexpensively.

  If the delay in the cable 12 becomes a problem, a delay corresponding to the timing signal input to the serial / para conversion circuit 117 may be provided for the timing signal input to the para / serial conversion circuit 147. Good.

The timing signal generating means for driving the serial / para conversion circuit 117 and the para / serial conversion circuit 147 is not limited to the above configuration.

Moreover, although the case where the number of I / O pins of the pin electronic board is increased four times in the above-described embodiment, as shown in FIG. 3, it can be increased to an arbitrary plural N times. In FIG. 3, a pin electronic board 21 includes a serial / para conversion circuit including N flip-flop circuits. A pin expansion board 24 connected to the pin electronic board 21 via one cable 22 per pin number is N A para / siri conversion circuit including one flip-flop circuit is provided. As a result, the DUT group 23 composed of N DUTs can be tested in parallel through the pin 25 composed of N pins.

FIG. 1 is a block diagram showing the configuration of an example of a semiconductor test apparatus according to an embodiment of the present invention. 2 is a time chart showing timing signals output from a timing generation circuit 118 of FIG. It is a block diagram which shows the modification of the Example of FIG. It is a block diagram which shows the structure of the pin electronic board of the conventional IC tester.

Explanation of symbols

11-pin electronics board 13 DUT
14-pin expansion board 111 Waveform generation circuit 117 Serial / parallel conversion circuit 142C Comparator 143 Distribution circuit 147 Parallel / serial conversion circuit

Claims (3)

A semiconductor test apparatus having a pin electronics substrate that applies a test signal to a plurality of DUTs and logically compares parallel logic signals based on signals output from the respective DUTs with expected values to perform pass / fail judgment,
A pin expansion board that distributes the test signal output in series from the same pin of the pin electronics board to each DUT and converts a parallel logic signal based on the signal output from each DUT into a serial logic signal;
The semiconductor device for testing a semiconductor device, wherein the pin electronics board converts a serial logic signal output from the pin expansion board via the pin into a parallel logic signal. The pin expansion board is
A distribution circuit for distributing the test signal to each DUT;
A comparator for level comparison of signals output in parallel from each DUT;
A parallel / serial conversion circuit for converting a parallel logic signal output from the comparator into a serial logic signal;
The pin electronics substrate is
A waveform generation circuit for generating the test signal;
2. The semiconductor test apparatus according to claim 1, further comprising a serial / parallel conversion circuit that converts the serial logic signal output from the pin expansion board into a parallel logic signal. Each of the parallel / serial conversion circuit and the serial / parallel conversion circuit includes N flip-flop circuits,
3. The semiconductor test apparatus according to claim 2, wherein the distribution circuit distributes the test signal to N DUTs.

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