JP2003344492A - Adapter device for ic tester - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an adapter device for an IC tester that enables a quick test of a target under test. <P>SOLUTION: The adapter device for an IC tester, which is detachably electrically connected to a test head and electrically connected to a target under test, has an exclusive OR circuit for subjecting a plurality of digital signals from the test head to an exclusive OR operation and outputting the result to the target under test. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an adapter device for an IC tester which is detachably electrically connected to a test head and electrically connected to an object to be tested. The present invention relates to the adapter device.

[0002]

2. Description of the Related Art An IC tester is an object to be tested (hereinafter referred to as DUT).
Abbreviated), for example, a test signal is given to IC, LSI,
The output of the DUT is compared with the expected value to determine the quality of the DUT. Such a device will be described below with reference to FIG.

In FIG. 3, a main body 1 is provided with a control section for controlling the apparatus, a power source for the apparatus, and the like. Test head 2
Is connected to the main body 1 by a cable 3 and is provided with a plurality of pin electronics boards (hereinafter abbreviated as PE) 20. The PE 20 has a driver that outputs a digital signal, a comparator that inputs a digital signal, and the like.

The performance board 4 is detachably electrically connected to the test head 2 and electrically connected to the PE 20. The DUT board 5 is detachably electrically connected to the performance board 5, and the DUT 6 is attached.
Connect electrically. Here, normally, when the DUT 6 is a package, the DUT board 5 is provided with a socket,
When the DUT 6 is a wafer, the DUT board 5 is provided with a probe.

The operation of such a device will be described below.
The test head 2 is connected to a transfer device (handler, prober, etc.) not shown, and the transfer device transfers the DUT 6 and electrically connects it to the DUT board 5.

Under the control of the main body 1, the PE 20 outputs a test signal (digital signal) to the DUT 6 via the performance board 4 and the DUT board 5.

The DUT 6 outputs a digital signal based on the test signal and inputs the digital signal to the PE 20 via the DUT board 5 and the performance board 4. And PE20
Compares the digital signal of the DUT 6 with an expected value to determine pass / fail.

Then, the carrier device replaces the DUT 6 and electrically connects to the DUT board 5. By repeating such an operation, the DUT 6 is tested.

[0009]

In recent years, due to the rapid increase in the speed of ICs, LSIs, etc., it has become impossible to test high-speed ICs, LSIs, etc. with conventional low-speed IC testers. .

On the other hand, a high-speed IC tester is expensive, and even an IC tester that is still low-speed can perform sufficient tests on ICs and LSIs.
There are many, etc., and if you introduce a high-speed IC tester,
Even when testing the low-speed DUT 6, there is a problem that the test cost increases.

Therefore, an object of the present invention is to realize an adapter device for an IC tester capable of performing a high-speed test of an object to be tested.

[0012]

The present invention according to claim 1 is an adapter device for an IC tester which is detachably electrically connected to a test head and electrically connected to an object to be tested. It is characterized by having an exclusive OR circuit for exclusive ORing a plurality of digital signals from the above to output to the device under test.

According to a second aspect of the present invention, in the first aspect of the present invention, the exclusive OR circuit is mounted on a performance board or a DUT board.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. Here, the same parts as those in FIG. 3 are designated by the same reference numerals and the description thereof will be omitted.

In FIG. 1, a plurality of drivers 21a to 2a are provided.
1d, the plurality of comparators 22 are provided in the test head 2 and mounted on the PE. The comparator 22 is
The output of the DUT 6 is input via the DUT board 5 and the performance board 4, the output of the DUT 6 is compared with the expected value, and the strobe h is used to judge the quality. The plurality of exclusive OR circuits 40 are mounted on the performance board 4, perform exclusive OR of a plurality of digital signals from the test head 2 and output the digital signals to the DUT 6 via the DUT board 5. The exclusive OR circuit 40 includes EXOR (exclusive OR) gates 41 to 43 and a driver 44. EXO
The R gate 41 outputs the outputs a and b of the drivers 21a and 21b.
Outputs the exclusive OR of. The EXOR gate 42 outputs the exclusive OR of the outputs c and d of the drivers 21c and 21d. The EXOR gate 43 includes the EXOR gate 41,
The signal g of the exclusive OR of the outputs e and f of 42 is output.
The driver 44 inputs the output g of the EXOR gate 43, adjusts the voltage, and outputs it to the DUT 6.

The operation of such a device will be described below.
FIG. 2 is a timing chart showing the operation of the device shown in FIG.

At the test rate, the drivers 21a, 21b
Outputs digital signals a and b. The EXOR gate 41 outputs the exclusive OR of the digital signals a and b as a digital signal e. This gives a test rate of 2
Two pulses can be output. On the other hand, driver 2
1c and 21d output digital signals c and d. The EXOR gate 42 outputs the exclusive OR of the signals c and d as a digital signal f. Thereby, two pulses can be output at the test rate.

Then, the EXOR gate 43 is connected to the EXOR gate.
Exclusive-OR the digital signals e and f of the gates 41 and 42 to output a digital signal (test signal) g. As a result, four pulses can be output at the test rate. Although an example of outputting four pulses has been shown,
One or three may be output at random. The driver 44 adjusts the voltage of this signal g and the DUT board 5
To the DUT 6 via. The DUT 6 outputs a digital signal based on the test signal g, and the comparator 2 via the DUT board 5 and the performance board 4.
Enter 2.

The comparator 22 compares the digital signal of the DUT 6 with the expected value, and determines whether the strobe h1 is good or bad. The same test is repeated, that is, the same test signal g is input to the DUT 6, and the comparator 22 causes the DU
The digital signal of T6 is compared with the expected value, and strobe h
A pass / fail judgment is made at 2. Further, the same test is repeated, and the comparator 22 compares the digital signal of the DUT 6 with the expected value, and determines whether the strobe h3 is good or bad.
The same test is repeated again, and the comparator 22
The digital signal of the DUT 6 is compared with the expected value, and the pass / fail is determined by the strobe h4. That is, the same test pattern is input to the DUT 6 four times, and the comparator 22 performs comparison at different timings and at expected values at different timings.
Here, it goes without saying that the expected values of the strobes h1 to h4 are different.

If the performance board 4 with the exclusive OR circuit 40 is removed and the performance board 4 without the exclusive OR circuit 40 is attached, the outputs of the drivers 21a to 21d can be directly output to the DUT 6. You can

As described above, the exclusive OR circuit 40 converts the output of the test head 2 into a high-speed signal, and the DUT
6, the DUT 6 can be tested at high speed. Therefore, an increase in test cost can be suppressed.

Further, Japanese Unexamined Patent Publication No. 11-295397 discloses an IC tester which can output a high frequency signal by using an exclusive OR circuit without advanced design, but it is designed in advance. Is. Therefore, since the size of the test head is fixed, the size of the circuit to be mounted is also limited, and when the exclusive OR circuit is used to increase the speed, the number of DUT pins that can be tested is also limited. That is, both the low speed DUT and the high speed DUT can be tested only with the same number of pins. On the other hand, in this embodiment, the exclusive OR circuit 40 is mounted on the performance board 4 and can be easily attached to and detached from the test head 2. Therefore, in the case of the low-speed DUT 6, it is possible to test with a large number of pins (a large number of DUTs 6). At the same time, although the number of pins that can be tested is limited, the high-speed DUT 6 can also be tested. That is, an increase in test cost can be suppressed.

When the DUT 6 is, for example, a D / A converter, the most significant bit of the digital input section is slower than the other bits, so the output from the test head 2 is directly input to the DUT 6. The other bits are input via the exclusive OR circuit 40. In other words, the DUT that needs high speed
Higher speed can be achieved by supporting only 6 pins.

The present invention is not limited to this, and the exclusive OR circuit 40 includes EXOR gates 41-41.
Although an example in which the driver 43 and the driver 44 are used is shown, EXOR
A configuration in which only the gate 41 is provided and an exclusive OR signal by the outputs of the drivers 21a and 21b is applied to the DUT 6 may be used. That is, the exclusive-OR circuit 40 only needs to output the exclusive-OR from the outputs of a plurality of drivers, and the driver 44 is not necessarily required if the voltage adjustment is unnecessary.

Although an example in which the exclusive OR circuit 40 is mounted on the performance board 4 has been shown, the DUT board 5
It may be mounted on the.

The DUT 6 may be directly attached to the performance board 4 without providing the DUT board 5.

[0027]

According to the present invention, since the output of the test head is converted into a high-speed signal by the exclusive OR circuit and is given to the test object, the test of the test object can be performed at high speed. Therefore, an increase in test cost can be suppressed.

Further, since the adapter device can be easily attached to and detached from the test head, it can be tested for a large number of pins in the case of a low speed test object, and the number of pins that can be tested is limited, but the high speed test object Can also be tested. That is, an increase in test cost can be suppressed.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the device shown in FIG.

FIG. 3 is a diagram showing a configuration of a conventional IC tester.

[Explanation of symbols] 2 test head 4 Performance board 5 DUT board 6 DUT 40 Exclusive OR circuit

Claims (2)

[Claims] 1. An adapter device for an IC tester, which is detachably electrically connected to a test head and electrically connected to an object to be tested, wherein a plurality of digital signals from the test head are exclusive-ORed. An adapter device for an IC tester, comprising an exclusive OR circuit for outputting to the device under test. 2. The adapter device for an IC tester according to claim 1, wherein the exclusive OR circuit is mounted on a performance board or a DUT board.