JP2000111616A - Test method of logical circuit and test device of logical circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To always accurately judge whether or not short circuit failure is caused in an external terminal of an integrated circuit. SOLUTION: A test method and a test device are constituted so as to judge whether or not short-circuit failure is caused in an external terminal 102 on the basis of output signal levels of a first buffer circuit 4 having first input threshold value voltage and a second buffer circuit 6 having second input threshold value voltage different from the first input threshold value voltage by impressing high level and low level voltages on the external terminal 102 being a test circuit point through an output buffer circuit 104 in a switching system. Thus, even if abnormality cannot be rightly detected due to a fluctuation in the input threshold value voltages in the output signal levels of the buffer circuits where a signal level of the external terminal 102 is a level close to the input threshold value voltage of one buffer circuit, the abnormality can be rightly detected by the output signal level of another one buffer circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a test method and a test apparatus for testing whether an external terminal of a logic integrated circuit is short-circuited to a ground line or a power supply line inside the integrated circuit.

[0002]

2. Description of the Related Art FIG.
It is a block diagram showing an example of a conventional test circuit of SI (large scale integrated circuit). The external terminal 102 is connected to the L
A high-level and low-level voltage signal is applied to the external terminal 102 through an output buffer circuit 104, and the external terminal 102 is connected to the internal terminal of the LSI based on the signal level of the external terminal 102. It is determined whether or not a short circuit fault has occurred.

When a test input signal is supplied to an external terminal 102, a low-level selection signal 110 is input to a control terminal 108 of a selector 106. As a result, the test input signal 112 is supplied to the register 114 through the selector 106, and is held in the register 114 in synchronization with the first clock 116 input to the register 114. This test input signal 112 is further supplied to a register 118,
The register 118 captures and holds the data in synchronization with the second clock 120 supplied to the register 118. Then, the test input signal 112 is supplied to the external terminal 102 through the buffer 4.

On the other hand, when detecting the signal level of the external terminal 102, the selector 106 outputs a high-level selection signal 1
Give 10 As a result, the test result signal 124 from the external terminal 102 is transferred to the register 114 through the selector 106.
And is held in the register 114 in synchronization with the first clock 116. The test result signal 124 held in the register 114 is output through the output terminal 122.

The high-level test input signal 112
To obtain a high-level test result signal 124 and to provide a low-level test input signal 112,
If the low-level test result signal 124 is obtained, it means that no short-circuit fault has occurred. On the other hand, if the signal level of the test result signal 124 is low even though the high-level test input signal 112 is supplied, the failure that the external terminal 102 is short-circuited to the ground side has occurred. Become. In addition, even though the low-level test input signal 112 is supplied, the test result signal 1
If the signal level of the signal 24 is high, it means that a failure has occurred in which the external terminal 102 is short-circuited to the power supply side. Note that the selector 106 is configured by an analog switching element, and an input signal is output as it is. Therefore, if the input signal is a voltage intermediate between the high level and the low level, it is output as a signal of the intermediate voltage.

[0006]

By the way, the selector 1
Whether the test result signal 124 supplied to the register 114 through 06 is at a high level or a low level is determined by whether or not the voltage of the test result signal 124 exceeds the input threshold voltage of the register 114. That is, when the voltage of the test result signal 124 is higher than the input threshold voltage, the register 114 holds the high-level signal on the assumption that the test result signal 124 is at the high level, and outputs the signal to the output terminal 122. On the other hand, when the voltage of the test result signal 124 is lower than the input threshold voltage, the register 114 holds the low-level signal assuming that the test result signal 124 is at the low level, and outputs the signal to the output terminal 122.

However, there is a variation in the input threshold voltage of the register 114 due to the specification of the transistor constituting the input section of the register. FIG. 9 is a graph showing input characteristics A, B, and C of three types of registers of the same type as an example. In the figure, the horizontal axis represents the input voltage, and the vertical axis represents the output voltage of the register input section inside the register. As can be seen from FIG. 9, in any of the registers, when the input voltage is in the range of Vin1, the signal levels of the output signals are all low level (L). When the input voltage is in the range of Vin3, the signal levels of the output signals are all high level (H). However, when the input voltage is approximately in the range of Vin2, the output signal level becomes high or low depending on the register even if the input voltage is the same.

The signal level of the test result signal 124 may fall in the range of the above-mentioned Vin which is intermediate between the high level and the low level depending on the degree of the short-circuit fault or the like. Since the output test result signal 124 changes depending on the characteristics of the register 114, it is difficult to correctly determine the presence or absence of a short-circuit failure. The present invention has been made to solve such a problem, and an object of the present invention is to provide a method of testing a logic circuit capable of always correctly determining whether or not a short circuit fault has occurred at a test circuit point such as the external terminal. An object of the present invention is to provide a logic circuit test device.

[0009]

In order to achieve the above object, a method of testing a logic circuit according to the present invention applies a high-level voltage and a low-level voltage to a test circuit point through an output buffer circuit, and provides a first input threshold value. Connecting an input terminal of a first buffer circuit having a voltage to the test circuit point;
An input terminal of a second buffer circuit having a second input threshold voltage different from the input threshold voltage is connected to the test circuit point, and the test is performed based on output signal levels of the first and second buffer circuits. It is characterized in that it is determined whether or not the circuit point is abnormal. Further, a test apparatus for a logic circuit according to the present invention includes an output buffer circuit for applying high-level and low-level voltages to test circuit points based on a test input signal, and an input terminal having a first input threshold voltage, A first buffer circuit connected to a test circuit point, and a second buffer circuit having a second input threshold voltage different from the first input threshold voltage and having an input terminal connected to the test circuit point And characterized in that:

In the present invention, a high-level voltage and a low-level voltage are applied to the test circuit point through the output buffer circuit, and the first buffer circuit having the first input threshold voltage and the first buffer circuit having a first input threshold voltage different from the first input threshold voltage. It is determined whether the test circuit point is abnormal based on the output signal level of the second buffer circuit having the input threshold voltage of 2. Therefore,
Even if the signal level at the test circuit point is close to the first input threshold voltage and an abnormality cannot be correctly detected due to variation in the input threshold voltage of the first buffer circuit, the first
The abnormality can be correctly detected based on the output signal level of the second buffer circuit having the second input threshold voltage different from the input threshold voltage. Conversely, when the signal level at the test circuit point is close to the second input threshold voltage and the second
Even if the abnormality cannot be correctly detected due to the variation of the input threshold voltage of the buffer circuit of the above, the abnormality is correctly detected by the output signal level of the first buffer circuit having the first input threshold voltage different from the second input threshold voltage. Can be detected.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an example of a test apparatus for a logic circuit according to the present invention, FIGS. 2 to 5 are timing charts showing the operation of the test apparatus for a logic circuit in FIG. 1, and FIG. 5 is a graph illustrating input characteristics of a buffer circuit included in the test device.
Hereinafter, an example of a logic circuit test apparatus of the present invention will be described with reference to these drawings, and at the same time, an embodiment of a logic circuit test method according to the present invention will be described.
In FIG. 1, the same elements as those in FIG. 8 are denoted by the same reference numerals.

As shown in FIG. 1, a test apparatus 2 for a logic circuit according to the present embodiment applies high-level and low-level voltages to an external terminal 102, which is a test circuit point, based on a test input signal 112. Output buffer circuit 104
A first buffer circuit 4 having a first input threshold voltage and having an input terminal connected to a test circuit point; and an input terminal having a second input threshold voltage higher than the first input threshold voltage. And a second buffer circuit 6 connected to the test circuit point.

FIG. 6 is a graph similar to that of FIG. 9 described above, showing the input characteristics of the first and second buffer circuits 4 and 6, the horizontal axis represents the input voltage, and the vertical axis represents the input voltage inside each buffer circuit. The output voltage of each section is shown. FIG. 6 shows the first
The input characteristics 1A, 1B, and 1C of three types of buffer circuits are shown for the buffer circuit 4 of FIG.
, Input characteristics 2A, 2B of three types of buffer circuits,
2C is shown. The first input threshold voltage, which is the input threshold voltage of the first buffer circuit 4, is in the range of the input voltage Vin2, and the second input threshold voltage, which is the input threshold voltage of the second buffer circuit 6, is higher than that. High input voltage Vi
n3. However, as in the case of the above-described register 114, there is a deviation in each characteristic due to variations in the buffer circuit, and the first and second input threshold voltages vary.

As can be seen from FIG. 6, in the case of the first buffer circuit 4, when the input voltage is in the range of Vin1, the signal levels of the output signals are all low (L).
On the other hand, when the input voltage is in the range of Vin3 and Vin4, the signal levels of the output signals are all high level (H). However, when the input voltage is substantially in the range of Vin2, the output signal level becomes high or low due to the buffer circuit even if the input voltage is the same because of the variation of the input threshold voltage. .

In the case of the second buffer circuit 6, when the input voltage is in the range of Vin1 and Vin2, the signal levels of the output signals are all low (L), while
When the input voltage is in the range of Vin4, the signal levels of the output signals are all high level (H). However, when the input voltage is approximately in the range of Vin3, the output signal level becomes high or low due to the buffer circuit even if the input voltage is the same because of the variation of the input threshold voltage. .

The logic circuit test apparatus 2 also includes a selector 8 for selecting and outputting one of the output signals of the first and second buffer circuits 4 and 6 and the test input signal 112, and an output of the selector 8. Register 1 for holding signal
14, and a register 118 for holding an output signal of the register 114 as a signal to be supplied to the output buffer circuit 104. And the register 114
Is supplied with a first clock 116 having a substantially constant cycle, the first register holds the input signal in synchronization with the first clock 116, and the second register has the first cycle A second clock 120 that is substantially the same as the clock 116 and has a different phase from the first clock 116 is supplied, and the second register holds the input signal in synchronization with the second clock 120.

Next, the operation of the test apparatus 2 for a logic circuit thus configured will be described with reference to the timing charts of FIGS. First, an operation when the high-level test input signal 112 is applied to the external terminal 102 will be described. As shown in FIG. 2, the selector 8 is first supplied with a signal whose value is “00” in binary as a 2-bit selection signal 10. In FIG. 2, SEL1 is an upper bit of the selection signal 10, and SEL0 is a selection signal 1
This is the lower bit of 0. The selector 8 thereby selects the test input signal 112 and outputs it to the register 114. As shown in FIG. 2, a first clock 116 having a constant period is supplied to the register 114, and the register 114 captures and holds the output signal of the selector 8 in synchronization with the rise of the first clock 116. .

At a timing T, when the test input signal 112 is set to a high level in order to supply the test input signal 112 of a high level to the external terminal 102, the register 1
14 captures and holds this signal at the next rising timing A of the first clock 116. As a result, the high level test input signal 112
And output to the output terminal 122. In addition,
The original test input signal 112 input to the selector 8 is thereafter returned to a low level.

On the other hand, as shown in FIG. 2, the register 118 is supplied with a second clock 120 having the same cycle as that of the first clock 116 and having a different phase. Captures and holds the input signal in synchronization with the rising edge of Therefore, the high-level test input signal 112 held by the register 114 as described above is captured and held by the register 118 at the next rising timing B of the second clock 120. The high-level test input signal 112 is supplied to the external terminal 102 which is a test circuit point through the output buffer circuit 104.

At timing B, the upper bit of the selection signal 10 is changed to "1", and the selector 8 selects the signal from the first buffer circuit 4 and supplies it to the register 114. Register 114 provides this signal to first clock 116
At the next rising timing C, and hold it.
Output to the output terminal 122.

Here, when no short-circuit fault has occurred in the external terminal 102, the signal level of the external terminal 102 becomes the test input signal 11 supplied from the output buffer circuit 104.
2, the first buffer circuit 4
Outputs a high-level signal, so that the timing C
Thereafter, the test result signal 12 output from the output terminal 122
Also becomes a high level as shown by the dotted line in FIG.

On the other hand, when the external terminal 102 has a short-circuit fault, the signal level of the external terminal 102 changes in four ways. That is, as shown in [Table 1], first, when the external terminal 102 is short-circuited to the ground, the signal level of the external terminal 102 is completely low level (L), and when the signal level of the external terminal 102 is low and high. In some cases, the signal level becomes an intermediate level, and becomes a signal level within the input voltage range Vin2 shown in FIG. Hereinafter, the former is called a low-level short circuit, and the latter is called a low-level intermediate short circuit. Also, the external terminal 102
Is short-circuited to the power supply, the signal level of the external terminal 102 becomes completely high level (H), or becomes a level intermediate between the low level and the high level, and is within the input voltage range Vin3 shown in FIG. Signal level. Hereinafter, the former is called a high-level short circuit, and the latter is called a high-level intermediate short circuit.

[0023]

[Table 1]

When the failure state of the external terminal 102 is a short-circuited low level, the signal level of the external terminal 102 becomes the signal level within the input voltage range Vin1, and the output signal of the first buffer circuit 4 becomes the low level. (See [Table 1]). At this time, the test result signal 12 also becomes low level. However, when the failure state of the external terminal 102 is a low-level intermediate short circuit, the signal level of the external terminal 102 falls within the input voltage range Vin2, so that the output signal of the first buffer circuit 4 may be low. , May become high level. The same applies to the test result signal 12 at this time, and the occurrence of a short circuit cannot be detected.

On the other hand, when the failure state of the external terminal 102 is a high-level short circuit, the signal level of the external terminal 102 falls within the input voltage range Vin4, so that the output signal of the first buffer circuit 4 becomes the high level. At this time, the test result signal 12 also becomes high level. However, the external terminal 102
Is normal, the output signal of the first buffer circuit 4 is at the high level, so that the occurrence of the high-level short circuit cannot be detected at this stage. Therefore, "(H)" is displayed in [Table 1]. When the failure state of the external terminal 102 is a high-level intermediate short-circuit, the signal level of the external terminal 102 enters the input voltage range Vin3, the output signal of the first buffer circuit 4 becomes high level, and the test result signal 12 also goes high. Therefore, in this case, similarly to the case of the high-level short-circuit, it cannot be detected that the high-level intermediate short-circuit has occurred.

Next, a similar test is performed using the second buffer circuit 6. Therefore, as shown in the timing chart of FIG. 3, instead of changing the upper bit of the selection signal 10 to “1” at the timing B, the lower bit is changed to “1”. As a result, the selector 8 selects the output signal of the second buffer circuit 6 after the timing B and outputs it to the register 114.

When the failure state of the external terminal 102 is a low-level short circuit, the signal level of the external terminal 102 becomes the signal level within the input voltage range Vin1, and the output signal of the second buffer circuit 6 becomes low level. (See [Table 1]). When the failure state of the external terminal 102 is a low-level intermediate short-circuit, the signal level of the external terminal 102 falls within the input voltage range Vin2, and this signal level is the second threshold voltage that is the input threshold voltage of the second buffer circuit 6. Since the voltage is lower than the input threshold voltage, the output signal of the second buffer circuit 6 becomes low level.

On the other hand, when the failure state of the external terminal 102 is short-circuited at the high level, the signal level of the external terminal 102 falls within the input voltage range Vin4, so that the output signal of the second buffer circuit 6 becomes the high level, and the test result is obtained. The signal 12 also goes high. However, even when the external terminal 102 is normal, the output signal of the second buffer circuit 6 is at a high level, so that a high-level short circuit cannot be detected at this stage. Further, when the failure state of the external terminal 102 is a high-level intermediate short circuit, the signal level of the external terminal 102 falls within the input voltage range Vin3, so that the output signal of the second buffer circuit 6 may be at a high level. , On the contrary, it may become low level. Therefore, occurrence of a short-circuit failure cannot be detected.

As can be seen from Table 1 above, when the test input signal 112 is at the high level, the high-level short circuit and the high-level short-circuit can occur regardless of whether the first or second buffer circuit 4 or 6 is used. Although a high-level intermediate short circuit cannot be detected, if any of the output signals of the first and second buffer circuits 4 and 6 is at a low level, ie, the first and second buffer circuits 4 and 6 When the test result signal 12 output from the output terminal 122 at any time after being switched by the selector 8 is at a low level, it can be determined that a low-level short-circuit or a low-level intermediate short-circuit has occurred. .

Next, the operation when the low-level test input signal 112 is applied to the external terminal 102 will be described. FIG.
As shown in (1), first, a signal whose value is "00" in binary is supplied to the selector 8 as a 2-bit selection signal 10. The selector 8 thereby selects the low-level test input signal 112 and outputs it to the register 114. The register 114 captures and holds this signal at the subsequent rising timing A of the first clock 116. As a result, the low level test input signal 112
And output to the output terminal 122. Then, the register 118 captures and holds the low-level test input signal 112 held by the register 114 at the subsequent timing B of the rising edge of the second clock 120. The low-level test input signal 112 held by the register 118 is supplied to the external terminal 102 which is a test circuit point through the output buffer circuit 104.

At timing B, the upper bit of the selection signal 10 is changed to "1", and the selector 8 selects the signal from the first buffer circuit 4 and supplies it to the register 114. Register 114 provides this signal to first clock 116
At the next rising timing C, and hold it.
Output to the output terminal 122.

If no short-circuit fault has occurred in the external terminal 102, the signal level of the external terminal 102 is equal to the test input signal 11 supplied from the output buffer circuit 104.
2, the first buffer circuit 4
Outputs a low-level signal, so that the timing C
Thereafter, the test result signal 12 output from the output terminal 122
Also becomes a low level as shown by a dotted line in FIG.

On the other hand, when the external terminal 102 has a short-circuit fault, the signal level of the
It changes according to the fault condition. First, the external terminal 10
2 is a low-level short circuit, the external terminal 102
Becomes the signal level within the input voltage range Vin1, and the output signal of the first buffer circuit 4 becomes low level (see [Table 1]). At this time, the test result signal 12 also becomes low level. However, test input signal 1
Since 12 is also at a low level, a short-circuit fault cannot be detected. However, when the failure state of the external terminal 102 is a low-level intermediate short circuit, the signal level of the external terminal 102 falls within the input voltage range Vin2, so that the output signal of the first buffer circuit 4 may be low. , May become high level. The same applies to the test result signal 12 at this time, and the occurrence of a short circuit cannot be detected.

On the other hand, when the failure state of the external terminal 102 is a high-level short circuit, the signal level of the external terminal 102 falls within the input voltage range Vin4, so that the output signal of the first buffer circuit 4 is at the high level. At this time, the test result signal 12 also becomes high level. And the external terminal 10
When the fault state of No. 2 is a high-level intermediate short circuit, the signal level of the external terminal 102 enters the input voltage range Vin3, and the output signal of the first buffer circuit 4 becomes high level.
The test result signal 12 also becomes high level.

Next, a similar test is performed using the second buffer circuit 6. Therefore, as shown in the timing chart of FIG. 5, instead of changing the upper bit of the selection signal 10 to "1" at the timing B, the lower bit is changed to "1". As a result, the selector 8 selects the output signal of the second buffer circuit 6 after the timing B and outputs it to the register 114.

When the failure state of the external terminal 102 is a low-level short circuit, the signal level of the external terminal 102 becomes a signal level within the input voltage range Vin1, and the output signal of the second buffer circuit 6 becomes low. Level. However, since the test input signal 112 is also at the low level, it is not possible to determine the presence or absence of the short-circuit failure from this. When the failure state of the external terminal 102 is a low-level intermediate short-circuit, the signal level of the external terminal 102 is set to the input voltage range Vi.
n2, the signal level of the second buffer circuit 6
Is lower than the second input threshold voltage, which is the input threshold voltage of the second buffer circuit 6, and the output signal of the second buffer circuit 6 is at the low level. However, since the test input signal 112 is also at the low level, it is not possible to determine the presence or absence of the short-circuit failure from this.

On the other hand, when the failure state of the external terminal 102 is a high-level short circuit, the signal level of the external terminal 102 falls within the input voltage range Vin4, so that the output signal of the second buffer circuit 6 becomes high level, The result signal 12 also goes high. Further, when the failure state of the external terminal 102 is a high-level intermediate short circuit, the signal level of the external terminal 102 falls within the input voltage range Vin3, so that the output signal of the second buffer circuit 6 may be at a high level. , On the contrary, it may become low level. Therefore, occurrence of a short-circuit failure cannot be detected.

As can be seen from Table 1 above, when the test input signal 112 is at a low level, low-level short-circuiting occurs regardless of whether the first or second buffer circuit 4 or 6 is used. Although a low-level intermediate short circuit cannot be detected, if any of the output signals of the first and second buffer circuits 4 and 6 is at a high level, that is, the first and second buffer circuits 4 and 6 If the test result signal 12 output from the output terminal 122 at any time after being switched by the selector 8 is at a high level, it can be determined that a high-level short-circuit or a high-level intermediate short-circuit has occurred. . Therefore, in the present embodiment, all four short-circuit fault states of the external terminal 102 can be correctly detected.

Next, a second embodiment of the present invention will be described. FIG. 7 is a block diagram showing the second embodiment. The logic circuit test device 14 differs from the logic circuit test device 2 in that an output circuit of the first and second buffer circuits 4 and 6 includes an AND circuit 16, an OR circuit 18, and a selector 20. That is, the selector 8 is replaced by the selector 22. Both the AND circuit 16 and the OR circuit 18 receive the output signals of the first and second buffer circuits 4 and 6 as inputs. The selector 20 selects the output signal of the OR circuit 18 when the signal level of the test input signal 112 is low and outputs it to the selector 22. When the signal level of the test input signal 112 is high, the AND circuit 16 output signals are selected and output to the selector 22. Then, the selector 22
One of the test input signal 112 and the output signal of the selector 20 is selected based on the signal level of the selection signal 24 and output to the register 114.

Next, the operation of the test apparatus 14 for a logic circuit configured as described above will be described. First, when the test input signal 112 is set to a high level, if a low-level short circuit or a low-level intermediate short circuit of the external terminal 102 has occurred, as described above, the first and second buffer circuits 4 and 6 At least one of the output signals is at a low level. Therefore, at this time, the output signal of the AND circuit 16 always becomes low level, and this low level signal is output to the output terminal 122 through the selector 22 and the register 114.
This is output as a test result signal 12.

On the other hand, when the test input signal 112 is set to the low level and the high level short circuit or the high level intermediate short circuit of the external terminal 102 occurs, as described above, the first and second buffer circuits 4 , 6 are at a high level. Therefore, at this time, the output signal of the OR circuit 18 always goes to a high level, and this high-level signal is output as the test result signal 12 from the output terminal 122 through the selector 22 and the register 114.

Therefore, in the second embodiment, it is not necessary to perform the test twice, that is, the test using the first buffer circuit 4 and the test using the second buffer circuit 6, and the test is simply performed. All tests can be completed only by switching the signal level of the test input signal 112 once. That is, the second
In this embodiment, in addition to the same effect as the first embodiment, a new effect that the time required for the test can be shortened is obtained.

[0043]

As described above, the logic circuit test method of the present invention achieves the above object by applying high-level and low-level voltages to a test circuit point through an output buffer circuit, and applying a first input to the test circuit point. An input terminal of a first buffer circuit having a threshold voltage is connected to the test circuit point, and an input terminal of a second buffer circuit having a second input threshold voltage different from the first input threshold voltage is tested. The test circuit is connected to a circuit point, and it is determined whether or not the test circuit point is abnormal based on output signal levels of the first and second buffer circuits. Further, a test apparatus for a logic circuit according to the present invention includes an output buffer circuit for applying high-level and low-level voltages to test circuit points based on a test input signal, and an input terminal having a first input threshold voltage, A first buffer circuit connected to a test circuit point, and a second buffer circuit having a second input threshold voltage different from the first input threshold voltage and having an input terminal connected to the test circuit point And characterized in that:

In the present invention, a high-level voltage and a low-level voltage are applied to the test circuit point through the output buffer circuit, and the first buffer circuit having the first input threshold voltage and the first input threshold voltage different from the first input threshold voltage. It is determined whether the test circuit point is abnormal based on the output signal level of the second buffer circuit having the input threshold voltage of 2. Therefore,
Even if the signal level at the test circuit point is close to the first input threshold voltage and an abnormality cannot be correctly detected due to variation in the input threshold voltage of the first buffer circuit, the first
The abnormality can be correctly detected based on the output signal level of the second buffer circuit having the second input threshold voltage different from the input threshold voltage. Conversely, when the signal level at the test circuit point is close to the second input threshold voltage and the second
Even if the abnormality cannot be correctly detected due to the variation of the input threshold voltage of the buffer circuit of the above, the abnormality is correctly detected by the output signal level of the first buffer circuit having the first input threshold voltage different from the second input threshold voltage. Can be detected. Therefore, in the present invention, a short-circuit fault can always be correctly detected regardless of what short-circuit fault occurs at the test circuit point.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of a test apparatus for a logic circuit according to the present invention.

FIG. 2 is a timing chart showing an operation of the test apparatus for a logic circuit in FIG. 1;

FIG. 3 is a timing chart showing an operation of the test apparatus of the logic circuit of FIG. 1;

FIG. 4 is a timing chart showing an operation of the test apparatus of the logic circuit of FIG. 1;

FIG. 5 is a timing chart showing the operation of the test apparatus for the logic circuit of FIG. 1;

FIG. 6 is a graph showing input characteristics of a buffer circuit included in the test apparatus for the logic circuit of FIG. 1;

FIG. 7 is a block diagram showing a second embodiment.

FIG. 8 is a block diagram showing an example of a conventional test circuit of an LSI using a boundary scan.

FIG. 9 is a graph showing input characteristics of three types of registers of the same type.

[Explanation of symbols]

2... Logic circuit test apparatus, 4... First buffer circuit, 6... 2nd buffer circuit, 8.
... Selection signal, 12... Test result signal, 14... Logic circuit test device, 16... AND circuit, 18... OR circuit, 20... Selector, 22.
Selection signal, 102 external terminal, 104 output buffer circuit, 106 selector, 108 control terminal, 1
10 ... selection signal, 112 ... test input signal, 114 ...
... Register, 116... First clock, 118... Register, 120... Second clock, 122... Output terminal, 124.

Claims (9)

[Claims] 1. A high-level and low-level voltage is applied to a test circuit point through an output buffer circuit, and an input terminal of a first buffer circuit having a first input threshold voltage is connected to the test circuit point; An input terminal of a second buffer circuit having a second input threshold voltage different from the first input threshold voltage is connected to the test circuit point, and based on output signal levels of the first and second buffer circuits A method for testing a logic circuit, comprising determining whether the test circuit point is abnormal. 2. A second input threshold voltage is higher than the first input threshold voltage, and one of the output signals of the first and second buffer circuits when a high-level voltage is applied to the test circuit point. Is low, it is determined that the test circuit point is abnormal. When a low-level voltage is applied to the test circuit point, one of the output signals of the first and second buffer circuits is at a high level. 2. The method according to claim 1, wherein it is determined that the test circuit point is abnormal in the case. 3. An output buffer circuit for applying high-level and low-level voltages to a test circuit point based on a test input signal, and an input terminal having a first input threshold voltage and connected to the test circuit point. A first buffer circuit, and a second buffer circuit having a second input threshold voltage different from the first input threshold voltage and having an input terminal connected to the test circuit point. Characteristic logic circuit test equipment. 4. A selector for selecting and outputting one of the output signals of the first and second buffer circuits, a first register for holding an output signal of the selector as a signal representing a test result, The test apparatus for a logic circuit according to claim 3, further comprising: 5. The test apparatus according to claim 4, further comprising a second register for holding the test input signal supplied to an output buffer circuit. 6. The selector selects and outputs one of an output signal of the first and second buffer circuits and a test input signal, and an output signal of the first register is a second register. 6. The test apparatus for a logic circuit according to claim 5, wherein the test signal is supplied to the test circuit. 7. A first clock having a substantially constant period is supplied to the first register, and the first register holds an input signal in synchronization with the first clock, and The second register is supplied with a second clock having a cycle substantially the same as that of the first clock and having a different phase from the first clock, and the second register is inputted in synchronization with the second clock. 7. The test apparatus for a logic circuit according to claim 6, wherein the test signal is held. 8. An AND circuit that receives output signals of the first and second buffer circuits as inputs, an OR circuit that receives output signals of the first and second buffer circuits as inputs, and the test input. 4. The logic circuit according to claim 3, further comprising a selector that selects one of the output signals of the AND circuit and the OR circuit based on a signal level of the signal and outputs the selected signal as a signal representing a test result. Test equipment. 9. The test circuit according to claim 3, wherein the test circuit point is an external terminal of an integrated circuit in which a logic circuit is incorporated.
A test apparatus for a logic circuit according to claim 1.