JP2008211170A - Substrate for packaging semiconductor element, its manufacturing method and semiconductor device - Google Patents

Substrate for packaging semiconductor element, its manufacturing method and semiconductor device Download PDF

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JP2008211170A
JP2008211170A JP2007302458A JP2007302458A JP2008211170A JP 2008211170 A JP2008211170 A JP 2008211170A JP 2007302458 A JP2007302458 A JP 2007302458A JP 2007302458 A JP2007302458 A JP 2007302458A JP 2008211170 A JP2008211170 A JP 2008211170A
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electrode
semiconductor element
outer peripheral
peripheral portion
substrate
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Kazuhiro Matsuo
一博 松尾
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Kyocera Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0102Calcium [Ca]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01046Palladium [Pd]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701Low temperature co-fired ceramic [LTCC]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/146Mixed devices
    • H01L2924/1461MEMS

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a substrate for packaging a semiconductor element, which improves the bonding strength of a bump electrode by an ultrasonic bonding, and to provide a manufacturing method therefor and a semiconductor device. <P>SOLUTION: The substrate 19 for packaging semiconductor elements has a packaging section 11, where electrode pads 12 are formed for packaging a semiconductor element 21 having the bump electrode 23 on a plurality of electrode terminals 22 formed on the lower surface thereof, on the upper surface of an insulating substrate 11. The bump electrode 23 is brought into contact with the electrode pad 12, and ultrasonic waves are applied from the upper surface of the semiconductor element 21 for joining the bump electrode 23 to the electrode pad 12. In the electrode pad 12, a center part 12a in the region brought into contact with the bump electrode 23 is lower than the peripheral part 12b, and an annular gap 12c is provided between the center part 12a and the peripheral part 12b. The center part 12a and the peripheral part 12b of the electrode pad 12 are engaged with the bump electrode 23, and a stress at joining can be relaxed by the gap 12c, thus joining strength and packaging reliability can be improved. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、絶縁基板の上面に形成された電極パッドに、半導体素子の下面に形成された電極端子に備えられた突起電極が、この突起電極を振動させる超音波が半導体素子に印加されることにより接合される半導体素子実装用基板、およびその半導体素子実装用基板の製造方法、ならびにその半導体素子実装用基板を用いてなる半導体装置に関するものである。   According to the present invention, a bump electrode provided on an electrode terminal formed on a lower surface of a semiconductor element is applied to an electrode pad formed on an upper surface of an insulating substrate, and ultrasonic waves that vibrate the bump electrode are applied to the semiconductor element. The present invention relates to a semiconductor element mounting substrate to be bonded by the above, a method for manufacturing the semiconductor element mounting substrate, and a semiconductor device using the semiconductor element mounting substrate.

回路基板や半導体素子収納用パッケージ等に用いられる配線基板である半導体素子実装用基板に半導体素子等の電子部品を搭載実装する方法の一つとして、いわゆるフリップチップ実装法がある。   There is a so-called flip-chip mounting method as one method for mounting and mounting an electronic component such as a semiconductor element on a semiconductor element mounting board which is a wiring board used for a circuit board, a semiconductor element storage package or the like.

この実装法は、一般的には、半導体素子の電極端子上にワイヤボンディング技術等によって金等から成る突起電極を設け、一方、この半導体素子が実装される半導体素子実装用基板にはその突起電極に対向する位置に電極パッドを設けておき、これら半導体素子の金等の突起電極と半導体素子実装用基板の電極パッドとを位置合わせして半導体素子実装用基板に半導体素子を載置し、突起電極を電極パッドに当接させた後に突起電極と電極パッドとを接合することにより、半導体素子を半導体素子実装用基板にいわゆるフェースダウンで実装するものである。   In this mounting method, generally, a protruding electrode made of gold or the like is provided on an electrode terminal of a semiconductor element by wire bonding technology or the like, while the protruding electrode is provided on a semiconductor element mounting substrate on which the semiconductor element is mounted. An electrode pad is provided at a position opposite to the semiconductor element, the protruding electrode such as gold of the semiconductor element is aligned with the electrode pad of the semiconductor element mounting substrate, the semiconductor element is placed on the semiconductor element mounting substrate, and the protrusion is The semiconductor element is mounted on the semiconductor element mounting substrate in a so-called face-down manner by bonding the protruding electrode and the electrode pad after bringing the electrode into contact with the electrode pad.

このようなフリップチップ実装法においては、半導体素子実装用基板の電極パッドと半導体素子の突起電極とを接合する方法として、半導体素子実装用基板に載置した半導体素子の上面から超音波を印加して突起電極を左右方向(ほぼ平面状の電極パッドの表面に平行な方向)に振動させ、突起電極と電極パッドとの当接界面付近で金等の金属を部分的に溶融させる超音波ボンディングにより接合する実装方法がある。
特開2006−128487号公報 特開2006−319211号公報 特開2002−222828号公報
In such a flip chip mounting method, an ultrasonic wave is applied from the upper surface of the semiconductor element mounted on the semiconductor element mounting substrate as a method of bonding the electrode pad of the semiconductor element mounting substrate and the protruding electrode of the semiconductor element. By ultrasonic bonding, the protruding electrode is vibrated in the left-right direction (a direction parallel to the surface of the substantially planar electrode pad), and a metal such as gold is partially melted near the contact interface between the protruding electrode and the electrode pad. There is a mounting method to join.
JP 2006-128487 JP 2006-319211 A Japanese Patent Laid-Open No. 2002-222828

しかしながら、上記のような従来の実装方法における突起電極と電極パッドとの接続方法には、以下のような問題点があった。   However, the connection method between the protruding electrode and the electrode pad in the conventional mounting method as described above has the following problems.

すなわち、フリップチップ実装を行なう場合に、突起電極の高さが非常に低いため、半導体素子実装用基板の凹凸や電極パッドの厚さ(高さ)ばらつきが原因となり、複数の突起電極のうち一部の突起電極の接続が行なえず、その結果、その半導体素子が実装不良となることがあるという問題点があった。   That is, when flip chip mounting is performed, the height of the protruding electrode is very low, which causes unevenness of the substrate for mounting a semiconductor element and variations in the thickness (height) of the electrode pad. As a result, there is a problem that the semiconductor element may be defective in mounting.

このような実装不良を防ぐためには、半導体素子の全ての突起電極が半導体素子実装用基板の電極パッドと接続されることが必要であり、そのためには、突起電極の高さばらつきを少なくするとともに、半導体素子実装用基板の平坦度を良くし、電極パッドの厚さ(高さ)ばらつきを少なくする必要がある。ただし、突起電極の高さばらつきは、実装時にこれらを押し潰すこととなるから、半導体素子実装用基板の平坦度や電極パッドの厚さ(高さ)ばらつきほどには重要とならない。   In order to prevent such mounting defects, it is necessary that all the protruding electrodes of the semiconductor element be connected to the electrode pads of the substrate for mounting the semiconductor element. To that end, the variation in the height of the protruding electrodes is reduced. Therefore, it is necessary to improve the flatness of the semiconductor element mounting substrate and to reduce the variation in the thickness (height) of the electrode pads. However, the variation in the height of the protruding electrode is not as important as the variation in the flatness of the semiconductor element mounting substrate and the thickness (height) of the electrode pad because they are crushed during mounting.

従って、実装不良を防止するためには、半導体素子実装用基板には実装面にできるだけ凹凸の無い平坦度の良好なものを用いて、電極パッドを始めとする配線パターンを厚さ(高さ)ばらつきを抑えて形成することが望ましいと考えられている。   Therefore, in order to prevent mounting defects, the semiconductor element mounting substrate should be as flat as possible with as little unevenness as possible on the mounting surface, and the thickness (height) of the wiring pattern including the electrode pads can be reduced. It is considered desirable to form the film while suppressing variations.

ところで、半導体素子の突起電極と半導体素子実装用基板の電極パッドとを超音波ボンディングする超音波フリップチップ実装においては、実装面が凹凸の無い平坦度の良好な半導体素子実装用基板、特に電極パッドが平坦な半導体素子実装用基板を用いてフリップチップ実装で半導体素子を実装すると、環境温度や半導体素子から発生する熱などにより熱膨張が起こり、半導体素子と半導体素子実装用基板との熱膨張係数の差が原因となって接続部分に基板に水平方向の応力が生じることになる。   By the way, in the ultrasonic flip chip mounting in which the bump electrode of the semiconductor element and the electrode pad of the substrate for mounting the semiconductor element are ultrasonically bonded, the mounting surface of the semiconductor element mounting substrate having excellent flatness with no unevenness, particularly the electrode pad. When a semiconductor element is mounted by flip chip mounting using a flat semiconductor element mounting substrate, thermal expansion occurs due to environmental temperature or heat generated from the semiconductor element, and the thermal expansion coefficient between the semiconductor element and the semiconductor element mounting substrate Due to this difference, horizontal stress is generated on the substrate at the connection portion.

また、突起電極は、半導体素子に対してワイヤボンディング法等により1つの突起電極毎に個別に超音波で接合され、さらにフリップチップ実装時に半導体素子の上面から一括で超音波が印加されているため、半導体素子(電極端子)に対する接合強度は比較的強いものの、半導体素子実装用基板の電極パッドとの間では、フリップチップ実装時に半導体素子の上から一括で超音波が印加されているだけなので比較的弱い接合強度となっている。   In addition, the protruding electrodes are individually bonded to the semiconductor element by an ultrasonic wave for each protruding electrode by a wire bonding method or the like, and further, ultrasonic waves are collectively applied from the upper surface of the semiconductor element during flip chip mounting. Although the bonding strength to the semiconductor element (electrode terminal) is relatively strong, comparison with the electrode pad of the semiconductor element mounting substrate is only applied in a lump from the top of the semiconductor element during flip chip mounting. Weak joint strength.

従って、実装後に温度サイクルを重ねることにより、最も弱い接合部分である半導体素子実装用基板の電極パッドと半導体素子の突起電極との接合界面から接合が外れて回路が断線する場合があるという問題点があった。   Therefore, by repeating the temperature cycle after mounting, the circuit may be disconnected due to the disconnection from the bonding interface between the electrode pad of the semiconductor element mounting substrate, which is the weakest bonding part, and the protruding electrode of the semiconductor element. was there.

本発明は上記従来技術における問題点に鑑みてなされたものであり、その目的は、半導体素子の突起電極の電極パッドに対する超音波ボンディングによる接合強度を高め、実装信頼性を向上した半導体素子実装用基板、およびその半導体素子実装用基板の製造方法、ならびにその半導体素子実装用基板を用いてなる信頼性の高い半導体装置を提供することにある。   The present invention has been made in view of the above-described problems in the prior art, and its object is to increase the bonding strength by ultrasonic bonding to the electrode pad of the protruding electrode of the semiconductor element and improve the mounting reliability. An object of the present invention is to provide a substrate, a method for manufacturing the semiconductor element mounting substrate, and a highly reliable semiconductor device using the semiconductor element mounting substrate.

本発明の半導体素子実装用基板は、絶縁基板の上面に、下面に複数の電極端子が形成されて該電極端子に突起電極を備えた半導体素子を実装するための、前記電極端子とそれぞれ対向する複数の電極パッドが形成された実装部を有して成り、前記電極パッドに前記突起電極を当接させて前記半導体素子の上面から超音波を印加して前記突起電極を前記電極パッドに接合する半導体素子実装用基板であって、前記電極パッドは、前記突起電極が当接する領域の中央部が外周部よりも低く、かつ前記中央部と前記外周部との間に環状に隙間が設けられていることを特徴とするものである。   The substrate for mounting a semiconductor element of the present invention is opposed to the electrode terminal for mounting a semiconductor element having a plurality of electrode terminals formed on the lower surface and having a protruding electrode on the upper surface of the insulating substrate. A mounting portion having a plurality of electrode pads is formed, and the protruding electrodes are brought into contact with the electrode pads, and ultrasonic waves are applied from the upper surface of the semiconductor element to bond the protruding electrodes to the electrode pads. A substrate for mounting a semiconductor element, wherein the electrode pad has a lower central portion of a region where the protruding electrode contacts lower than an outer peripheral portion, and an annular gap is provided between the central portion and the outer peripheral portion. It is characterized by being.

また、本発明の半導体素子実装用基板は、上記構成において、前記隙間は、前記超音波による前記突起電極の左右方向の振動と交差する側が他の部位よりも広いことを特徴とするものである。   Further, the semiconductor element mounting substrate of the present invention is characterized in that, in the above configuration, the gap is wider on the side intersecting with the left-right vibration of the protruding electrode due to the ultrasonic wave than other portions. .

また、本発明の半導体素子実装用基板は、上記構成において、前記電極パッドは、下地導体層の上に前記中央部と前記外周部とで厚みの異なるめっき層が被着されていることを特徴とするものである。   Moreover, the substrate for mounting a semiconductor element of the present invention is characterized in that, in the above configuration, the electrode pad has a plating layer having a thickness different from that of the central portion and the outer peripheral portion deposited on a base conductor layer. It is what.

本発明の半導体素子実装用基板の製造方法は、絶縁基板の上面に、下面に複数の電極端子が形成されて該電極端子に突起電極を備えた半導体素子を実装するための、前記突起電極がそれぞれ当接されるとともに前記半導体素子の上面から超音波が印加されて接合される複数の電極パッドとなる下地導体層を形成する工程と、前記下地導体層の表面に、前記突起電極が当接する領域の中央部が外周部よりも低くなるとともに、前記中央部と前記外周部との間に環状の隙間が設けられるように、前記突起電極が当接するめっき層を被着させて前記電極パッドを形成する工程とを備えることを特徴とするものである。   According to the method for manufacturing a substrate for mounting a semiconductor element of the present invention, the protruding electrode for mounting a semiconductor element having a plurality of electrode terminals formed on the lower surface of the insulating substrate and having a protruding electrode on the electrode terminal is provided. A step of forming a base conductor layer to be abutted and a plurality of electrode pads to be joined by applying ultrasonic waves from the upper surface of the semiconductor element; and the protruding electrode abuts on the surface of the base conductor layer The electrode pad is attached by depositing a plating layer on which the protruding electrode abuts so that the central portion of the region is lower than the outer peripheral portion and an annular gap is provided between the central portion and the outer peripheral portion. And a forming step.

また、本発明の半導体素子実装用基板の製造方法は、上記製造方法において、前記めっき層を被着させて前記電極パッドを形成する工程の前に、前記下地導体層を、前記中央部および前記外周部に対応する部分が前記隙間を挟んで電気的に独立するように形成するとともに、前記絶縁基板に、前記下地導体層の前記外周部に対応する部分のみから前記絶縁基板の外縁にかけてめっき用引き出し線を形成する工程を備えることを特徴とするものである。   Further, in the method for manufacturing a semiconductor element mounting substrate according to the present invention, in the manufacturing method described above, before the step of depositing the plating layer and forming the electrode pad, the base conductor layer is formed at the center and the substrate. A portion corresponding to the outer peripheral portion is formed so as to be electrically independent across the gap, and the insulating substrate is plated only from a portion corresponding to the outer peripheral portion of the base conductor layer to an outer edge of the insulating substrate. The method includes a step of forming a lead line.

また、本発明の半導体素子実装用基板の製造方法は、上記製造方法において、前記めっき層を被着させて前記電極パッドを形成する工程の前に、前記下地導体層を、前記中央部および前記外周部に対応する部分が前記隙間を挟んで電気的に独立するように形成するとともに、前記絶縁基板に、前記下地導体層の前記中央部および前記外周部に対応する部分のうち少なくとも前記中央部に対応する部分から前記絶縁基板の外縁にかけて第1のめっき用引き出し線を形成する工程と、前記外周部に対応する部分のみから前記絶縁基板の外縁にかけて第2のめっき用引き出し線を形成する工程とを備えることを特徴とするものである。   Further, in the method for manufacturing a semiconductor element mounting substrate according to the present invention, in the manufacturing method described above, before the step of depositing the plating layer and forming the electrode pad, the base conductor layer is formed at the center and the substrate. A portion corresponding to the outer peripheral portion is formed so as to be electrically independent with the gap interposed therebetween, and at least the central portion of the insulating substrate on the central portion of the base conductor layer and the outer peripheral portion. Forming a first lead wire for plating from the portion corresponding to the outer edge of the insulating substrate, and forming a second lead wire for plating from the portion corresponding to the outer peripheral portion to the outer edge of the insulating substrate. Are provided.

本発明の半導体装置は、絶縁基板の上面に、下面に複数の電極端子が形成されて該電極端子に突起電極を備えた半導体素子を実装するための、前記電極端子とそれぞれ対向する複数の電極パッドが形成された実装部を有して成る半導体素子実装用基板と、下面に複数の電極端子が形成されて該電極端子に突起電極を備えるとともに、超音波ボンディングにより前記突起電極が前記電極パッドに接合されて前記実装部に実装された半導体素子とを備え、前記突起電極と前記電極パッドとの接合領域の中央部と外周部との間に環状の隙間を有していることを特徴とするものである。   A semiconductor device according to the present invention includes a plurality of electrodes facing each of the electrode terminals for mounting a semiconductor element in which a plurality of electrode terminals are formed on the upper surface of the insulating substrate and the electrode terminals are provided with protruding electrodes. A substrate for mounting a semiconductor element having a mounting portion on which a pad is formed, a plurality of electrode terminals formed on the lower surface, and provided with a protruding electrode on the electrode terminal, and the protruding electrode is connected to the electrode pad by ultrasonic bonding And a semiconductor element mounted on the mounting portion, and an annular gap is provided between a central portion and an outer peripheral portion of a bonding region between the protruding electrode and the electrode pad. To do.

また、本発明の半導体装置は、上記構成において、前記環状の隙間は、前記超音波ボンディングの際に印加された超音波による前記突起電極の左右方向の振動と交差する側が他の部位よりも広いことを特徴とするものである。   In the semiconductor device according to the present invention, in the above configuration, the annular gap is wider on the side intersecting the left-right vibration of the protruding electrode due to the ultrasonic wave applied at the time of the ultrasonic bonding than other portions. It is characterized by this.

また、本発明の半導体装置は、上記構成において、前記電極パッドは、下地導体層の上に前記中央部と前記外周部とで厚みの異なるめっき層が、前記中央部が前記外周部に比べて低くなるように被着されていることを特徴とするものである。   In the semiconductor device according to the present invention, the electrode pad has a plating layer having a different thickness between the central portion and the outer peripheral portion on the underlying conductor layer, and the central portion is more in comparison with the outer peripheral portion. It is characterized by being deposited so as to be lowered.

本発明の半導体素子実装用基板によれば、電極パッドは、突起電極が当接する領域の中央部が外周部よりも低く、かつその中央部と外周部との間に環状に隙間が設けられていることから、超音波エネルギーで振動する半導体素子の突起電極と、電極パッドの中央部の上面および外周部の内側面から上面にかけた部分とがお互いに噛み合うようになり、また突起電極の振動する範囲が電極パッドの外周部の内側面等で制限されることで、フリップチップ実装における突起電極の位置ずれ等の接合不良の発生を効果的に抑制することができる。   According to the substrate for mounting a semiconductor element of the present invention, the electrode pad has a lower central portion of the region where the protruding electrode contacts than the outer peripheral portion, and an annular gap is provided between the central portion and the outer peripheral portion. Therefore, the protruding electrode of the semiconductor element that vibrates with ultrasonic energy and the upper surface of the central portion of the electrode pad and the portion extending from the inner surface to the upper surface of the outer peripheral portion come into mesh with each other, and the protruding electrode vibrates. Since the range is limited by the inner surface of the outer peripheral portion of the electrode pad, it is possible to effectively suppress the occurrence of bonding failure such as misalignment of the protruding electrode in flip chip mounting.

また、突起電極と接続パッドの外周部の内側面との接合面が水平面に対して直交または傾斜することから、突起電極と接続パッドの接合部分に作用する水平方向の応力に対して接合強度を向上させることができる。   In addition, since the bonding surface between the protruding electrode and the inner side surface of the outer peripheral portion of the connection pad is orthogonal or inclined with respect to the horizontal plane, the bonding strength against the horizontal stress acting on the bonding portion between the protruding electrode and the connection pad is increased. Can be improved.

また、電極パッドの中央部と外周部との間に隙間が設けられていることから、超音波ボンディング時において、突起電極と電極パッドとの接合面付近で、突起電極内に生じる内部応力を、例えば突起電極の、隙間に面する部分での微小な変形等により効果的に緩和することができる。   In addition, since a gap is provided between the central portion and the outer peripheral portion of the electrode pad, internal stress generated in the protruding electrode near the bonding surface between the protruding electrode and the electrode pad at the time of ultrasonic bonding, For example, the protrusion electrode can be effectively relaxed by a minute deformation or the like in a portion facing the gap.

そのため、絶縁基板の上面に水平な方向の応力に対しても強い接合構造とすることができるとともに、応力の残留等に起因する突起電極の機械的な破壊等を効果的に防止することができる、実装信頼性の向上した半導体素子実装用基板を提供することができる。   Therefore, it is possible to provide a joint structure that is strong against stress in the horizontal direction on the upper surface of the insulating substrate, and it is possible to effectively prevent mechanical destruction of the protruding electrode caused by residual stress. In addition, it is possible to provide a semiconductor element mounting substrate with improved mounting reliability.

また、本発明の半導体素子実装用基板によれば、上記構成において、隙間は、超音波による突起電極の左右方向の振動と交差する側が他の部位よりも広い場合には、突起電極と電極パッドとの接合される範囲(接合面)のうち、超音波による振動に伴う突起電極の振動幅が大きいために接合面が長く(広く)なる傾向のある側において、隙間を広く取ることができる。そのため、その広い接合面に生じる可能性のあるより強い内部応力をさらに効果的に緩和することができる。従って、この場合には、実装信頼性をより向上させる上で有効な半導体素子実装用基板を提供することができる。   Further, according to the substrate for mounting a semiconductor element of the present invention, in the above configuration, when the gap intersects with the vibration in the horizontal direction of the protruding electrode by the ultrasonic wave is wider than the other part, the protruding electrode and the electrode pad In the range (joint surface) to be joined, a gap can be widened on the side where the joint surface tends to be long (wide) due to the large vibration width of the protruding electrode due to the vibration caused by the ultrasonic waves. Therefore, it is possible to more effectively relieve stronger internal stress that may occur on the wide joint surface. Therefore, in this case, it is possible to provide a semiconductor element mounting substrate effective in further improving the mounting reliability.

また、本発明の半導体素子実装用基板によれば、上記構成において、電極パッドは、下地導体層の上に中央部と外周部とで厚みの異なるめっき層が被着されている場合には、例えば数μm程度の厚さで精度よく形成することができるとともにその厚さの調節が容易なめっき層により、中央部および外周部の厚さの調節ができる。そのため、中央部が外周部よりも低い電極パッドがより高い精度で形成された半導体素子実装用基板を提供することができる。   Further, according to the semiconductor element mounting substrate of the present invention, in the above configuration, the electrode pad has a plating layer having a thickness different between the central portion and the outer peripheral portion on the underlying conductor layer. For example, the thickness of the central portion and the outer peripheral portion can be adjusted by a plating layer that can be accurately formed with a thickness of about several μm and the thickness can be easily adjusted. Therefore, it is possible to provide a semiconductor element mounting substrate in which an electrode pad having a central portion lower than the outer peripheral portion is formed with higher accuracy.

また、本発明の半導体素子実装用基板の製造方法によれば、上記各工程を備えることから、メタライズ層や金属箔により絶縁基板の実装部に形成された下地導体層の表面に、例えばマスキング等の手段を併用して、中央部が外周部よりも低くなるとともに、中央部と外周部との間に環状の隙間が設けられるように、突起電極が当接するめっき層を被着させて電極パッドを形成することにより、突起電極が当接する領域の中央部が外周部よりも低く、かつ中央部と外周部との間に環状に隙間が設けられている電極パッドを有する半導体素子実装用基板を、確実に精度よく製作することができる。   Further, according to the method for manufacturing a substrate for mounting a semiconductor element of the present invention, since the above steps are included, the surface of the underlying conductor layer formed on the mounting portion of the insulating substrate by a metallized layer or metal foil is masked, for example. In combination with the above means, an electrode pad is formed by depositing a plating layer on which the protruding electrode abuts so that the central portion is lower than the outer peripheral portion and an annular gap is provided between the central portion and the outer peripheral portion. Forming a semiconductor element mounting substrate having an electrode pad in which the central portion of the region where the protruding electrode abuts is lower than the outer peripheral portion and an annular gap is provided between the central portion and the outer peripheral portion. It can be manufactured accurately and reliably.

また、本発明の半導体素子実装用基板の製造方法によれば、上記製造方法において、めっき層を被着させて電極パッドを形成する工程の前に、下地導体層を、中央部および外周部に対応する部分が隙間を挟んで電気的に独立するように形成するとともに、絶縁基板に、下地導体層の外周部に対応する部分のみから絶縁基板の外縁にかけてめっき用引き出し線を形成する工程を備える場合には、前述した工程による、突起電極が当接する領域の中央部が外周部よりも低く、かつ中央部と外周部との間に環状に隙間が設けられている電極パッドを有する半導体素子実装用基板を製造する方法を、より容易で生産性の高い製造方法とすることができる。   Further, according to the method for manufacturing a substrate for mounting a semiconductor element of the present invention, in the above manufacturing method, before the step of forming the electrode pad by depositing the plating layer, the base conductor layer is placed on the central portion and the outer peripheral portion. Forming a corresponding portion so as to be electrically independent with a gap, and forming a lead wire for plating on the insulating substrate from only the portion corresponding to the outer peripheral portion of the base conductor layer to the outer edge of the insulating substrate. In this case, the semiconductor element mounting having the electrode pad in which the central portion of the region where the protruding electrode abuts is lower than the outer peripheral portion and an annular gap is provided between the central portion and the outer peripheral portion by the above-described process. The manufacturing method of the manufacturing substrate can be made easier and more productive.

すなわち、隙間を挟んで電気的に独立し、電極パッドの中央部および外周部に対応する部分が隙間を挟んで電気的に独立するように形成された下地導体層は、外周部に対応する部分のみに電解めっき法によりめっき層を被着させることができる。また、中央部に対応する部分を含む下地導体層の全体には、無電解めっき法によりめっき層を被着させることが可能であり、中央部に対応する部分にも所定の厚さでめっき層を被着させることができる。そのため、例えば無電解めっき法により被着されるめっき層に加えて、電解めっき法によるめっき層の被着が可能な外周部に対応する部分は、中央部に対応する部分よりもめっき層を厚く被着させることができる。また、この場合には、マスキング等の工程が不要であり、例えば、めっき用の電流を供給するためのめっき用の治具の端子をめっき用引き出し線に接続するだけで、外周部に対応する部分のみに厚くめっき層を被着させることができる。そのため、突起電極が当接する領域の中央部が外周部よりも低い電極パッドの形成が容易である。   That is, the underlying conductor layer formed such that the portions corresponding to the central portion and the outer peripheral portion of the electrode pad are electrically independent with the gap therebetween, and the portions corresponding to the outer peripheral portion are electrically Only a plating layer can be applied by electrolytic plating. In addition, it is possible to deposit a plating layer on the entire base conductor layer including a portion corresponding to the central portion by an electroless plating method, and a plating layer having a predetermined thickness is also applied to the portion corresponding to the central portion. Can be applied. Therefore, for example, in addition to the plating layer deposited by the electroless plating method, the portion corresponding to the outer peripheral portion where the plating layer can be deposited by the electrolytic plating method is thicker than the portion corresponding to the central portion. Can be deposited. Further, in this case, a process such as masking is not necessary, and for example, it corresponds to the outer peripheral portion only by connecting the terminal of the plating jig for supplying the plating current to the lead wire for plating. A thick plating layer can be deposited only on the portion. Therefore, it is easy to form an electrode pad in which the central portion of the region where the protruding electrode contacts is lower than the outer peripheral portion.

また、本発明の半導体素子実装用基板の製造方法によれば、上記製造方法において、めっき層を被着させて電極パッドを形成する工程の前に、下地導体層を、中央部および外周部に対応する部分が隙間を挟んで電気的に独立するように形成するとともに、絶縁基板に、下地導体層の中央部および外周部に対応する部分のうち少なくとも中央部に対応する部分から絶縁基板の外縁にかけて第1のめっき用引き出し線を形成する工程と、外周部に対応する部分のみから前記絶縁基板の外縁にかけて第2のめっき用引き出し線を形成する工程とを備えることから、前述した工程による、突起電極が当接する領域の中央部が外周部よりも低く、かつ中央部と外周部との間に環状に隙間が設けられている電極パッドを有する半導体素子実装用基板を製造する方法を、より容易で生産性の高い製造方法とすることができる。   Further, according to the method for manufacturing a substrate for mounting a semiconductor element of the present invention, in the above manufacturing method, before the step of forming the electrode pad by depositing the plating layer, the base conductor layer is placed on the central portion and the outer peripheral portion. The corresponding portion is formed so as to be electrically independent with a gap, and the outer edge of the insulating substrate from the portion corresponding to at least the central portion of the portion corresponding to the central portion and the outer peripheral portion of the underlying conductor layer is formed on the insulating substrate. A step of forming the first lead wire for plating and a step of forming the second lead wire for plating from only the portion corresponding to the outer peripheral portion to the outer edge of the insulating substrate. Manufactures a substrate for mounting semiconductor elements having an electrode pad in which the central part of the area where the protruding electrode contacts is lower than the outer peripheral part and an annular gap is provided between the central part and the outer peripheral part The that way, it can be more easily and highly productive manufacturing method.

すなわち、隙間を挟んで電気的に独立し、電極パッドの中央部および外周部に対応する部分が隙間を挟んで電気的に独立するように形成された下地導体層は、中央部に対応する部分および外周部に対応する部分のそれぞれに別個に電解めっき法によりめっき層を被着させることができる。また、中央部に対応する部分を含む下地導体層の全体には、第1のめっき用引き出し線を介してめっき用の電流を供給することが可能であり、少なくとも中央部に所定の厚さでめっき層を被着させることができる。また、下地導体層のうち外周部に対応する部分のみに、第2のめっき用引き出し線を介して、より厚くめっき層を被着させることができる。また、この場合には、マスキング等の工程が不要であり、例えば、めっき用の電流を供給するためのめっき用の治具の端子を異なる引き出し線に接続するだけで、めっき層が被着される部分(中央部や外周部に対応する部分)を選択することができる。そのため、電極パッドのうち、より高い、つまりめっき層をより厚く被着させる必要のある外周部のみに電流を供給することができるため、突起電極が当接する領域の中央部が外周部よりも低い電極パッドの形成が容易である。   That is, the underlying conductor layer formed so that the portions corresponding to the central portion and the outer peripheral portion of the electrode pad are electrically independent with a gap therebetween is electrically And a plating layer can be separately deposited on each of the portions corresponding to the outer peripheral portion by electrolytic plating. Further, it is possible to supply a plating current to the entire underlying conductor layer including the portion corresponding to the central portion via the first plating lead wire, and at least a predetermined thickness in the central portion. A plating layer can be deposited. In addition, a thicker plating layer can be applied to only the portion corresponding to the outer peripheral portion of the base conductor layer via the second lead wire for plating. Further, in this case, a process such as masking is not required. For example, the plating layer is deposited simply by connecting the terminal of the plating jig for supplying the plating current to different lead wires. Part (part corresponding to the central part or the outer peripheral part) can be selected. Therefore, since the current can be supplied only to the outer peripheral portion of the electrode pad that is higher, that is, the plating layer needs to be deposited thicker, the central portion of the region where the protruding electrode contacts is lower than the outer peripheral portion. The electrode pad can be easily formed.

本発明の半導体装置によれば、上記構成を備え、超音波ボンディングされた突起電極と電極パッドとの接合領域の中央部と外周部との間に環状の隙間を有していることから、超音波印加時において突起電極と電極パッドとの接合面付近で突起電極内に生じていた内部応力が、例えば突起電極の隙間部分での微細な変形等により効果的に緩和されて突起電極の内部等に残留していないものとすることができる。   According to the semiconductor device of the present invention, since it has the above-described configuration and has the annular gap between the central portion and the outer peripheral portion of the bonding region between the ultrasonic bonded electrode and the electrode pad, The internal stress generated in the protruding electrode in the vicinity of the bonding surface between the protruding electrode and the electrode pad when the sound wave is applied is effectively relieved by, for example, minute deformation in the gap portion of the protruding electrode, and the inside of the protruding electrode. It can be assumed that there is no residue.

そのため、絶縁基板の上面に水平な方向の応力に対しても強い接合構造とすることができるとともに、応力の残留等に起因する突起電極の機械的な破壊等を効果的に防止することができる、長期の実装信頼性の向上した半導体装置を提供することができる。   Therefore, it is possible to provide a joint structure that is strong against stress in the horizontal direction on the upper surface of the insulating substrate, and it is possible to effectively prevent mechanical destruction of the protruding electrode caused by residual stress. A semiconductor device with improved long-term mounting reliability can be provided.

また、本発明の半導体装置によれば、上記構成において、環状の隙間は、超音波ボンディングの際に印加される超音波による突起電極の左右方向の振動と交差する側が他の部位よりも広い場合には、突起電極と電極パッドの接合される範囲(接合面)のうち、振動に伴う突起電極の振動幅が大きいために接合面が長く(広く)なる傾向のある側において、隙間を広く取ることができる。そのため、その広い接合面に生じる可能性のあるより強い内部応力をさらに効果的に緩和することができる。従って、この場合には、長期の実装信頼性をさらに向上させる上で有効な半導体装置を提供することができる。   Further, according to the semiconductor device of the present invention, in the above configuration, when the annular gap is wider than the other part on the side intersecting the left-right vibration of the protruding electrode due to the ultrasonic wave applied at the time of ultrasonic bonding In the area where the protruding electrode and the electrode pad are bonded (bonding surface), a gap is widened on the side where the bonding electrode tends to be long (wide) due to the large vibration width of the protruding electrode due to vibration. be able to. Therefore, it is possible to more effectively relieve stronger internal stress that may occur on the wide joint surface. Therefore, in this case, it is possible to provide a semiconductor device that is effective in further improving long-term mounting reliability.

また、本発明の半導体装置によれば、上記構成において、電極パッドは、下地導体層の上に中央部と外周部とで厚みの異なるめっき層が被着されている場合には、例えば数μm程度の厚さで精度よく形成することができるとともにその厚さの調節が容易なめっき層により、中央部および外周部の厚さの調節ができる。そのため、中央部が外周部よりも低い電極パッドがより高い精度で形成され、電極パッドと突起電極との間で十分な隙間を有する、より信頼性の高い半導体装置を提供することができる。また、半導体装置としての生産性を向上させる上で有効である。   Further, according to the semiconductor device of the present invention, in the above configuration, the electrode pad has a thickness of, for example, several μm when a plating layer having a thickness different between the central portion and the outer peripheral portion is deposited on the base conductor layer. The thickness of the central portion and the outer peripheral portion can be adjusted by the plating layer that can be formed with a certain degree of accuracy with high accuracy and the thickness can be easily adjusted. Therefore, it is possible to provide a more reliable semiconductor device in which an electrode pad whose central portion is lower than the outer peripheral portion is formed with higher accuracy, and a sufficient gap is provided between the electrode pad and the protruding electrode. Further, it is effective in improving the productivity as a semiconductor device.

本発明の半導体素子実装用基板およびその製造方法ならびに半導体装置について、添付の図面を参照しつつ説明する。   A substrate for mounting a semiconductor element, a manufacturing method thereof, and a semiconductor device of the present invention will be described with reference to the accompanying drawings.

(半導体素子実装用基板および半導体装置)
まず、図1を参照しつつ本発明の半導体素子実装用基板およびその半導体素子実装用基板に半導体素子を実装してなる本発明の半導体装置について説明する。図1(a)は本発明の半導体素子実装用基板の実施の形態の一例を示す平面図であり、図1(b)は(a)の半導体素子実装用基板に半導体素子を実装する、本発明の半導体装置の断面図である。なお、図を見やすくするために、図1(b)では半導体素子と半導体素子実装用基板とを離して示している。
(Semiconductor element mounting substrate and semiconductor device)
First, a semiconductor element mounting substrate of the present invention and a semiconductor device of the present invention formed by mounting a semiconductor element on the semiconductor element mounting substrate will be described with reference to FIG. FIG. 1A is a plan view showing an example of an embodiment of a substrate for mounting a semiconductor element of the present invention, and FIG. It is sectional drawing of the semiconductor device of invention. In order to make the drawing easier to see, FIG. 1B shows the semiconductor element and the semiconductor element mounting substrate separated from each other.

図1において11は絶縁基板、12は電極パッドであり、絶縁基板11の上面の実装部11aに電極パッド12が形成されて半導体素子実装用基板19が基本的に形成されている。また、21は半導体素子、22は半導体素子21の下面に形成され、それぞれが突起電極23を備える複数の電極端子である。半導体素子搭載用基板19の実装部11aに半導体素子21が搭載されるとともに、突起電極23が電極パッド12と接合されることにより、半導体装置30が基本的に構成されている。   In FIG. 1, reference numeral 11 denotes an insulating substrate, and 12 denotes an electrode pad. The electrode pad 12 is formed on a mounting portion 11 a on the upper surface of the insulating substrate 11 to basically form a semiconductor element mounting substrate 19. Reference numeral 21 denotes a semiconductor element, and reference numeral 22 denotes a plurality of electrode terminals formed on the lower surface of the semiconductor element 21, each having a protruding electrode 23. The semiconductor device 30 is basically configured by mounting the semiconductor element 21 on the mounting portion 11 a of the semiconductor element mounting substrate 19 and joining the protruding electrode 23 to the electrode pad 12.

電極パッド12は、突起電極23にそれぞれ対向して形成されており、突起電極23が接合される範囲のうち中央部12aが外周部12bよりも低く、中央部12aと外周部12bとの間に環状に隙間12cが設けられている。   The electrode pads 12 are formed so as to face the protruding electrodes 23, respectively, and the central portion 12a is lower than the outer peripheral portion 12b in the range where the protruding electrodes 23 are joined, and between the central portion 12a and the outer peripheral portion 12b. An annular gap 12c is provided.

半導体素子実装用基板19に搭載される半導体素子21は、例えば半導体集積回路素子(IC,LSI)やマイクロマシン(いわゆるMEMS素子)等であり、シリコン等の半導体基板(符号なし)の主面に集積回路やスイッチング機構等の可動部分等の機能部分(図示せず)が形成されている。この半導体基板の例えば機能部分が形成されている主面に、機能部分と電気的に接続された複数の電極端子22が形成され、電極端子22は、それぞれ突起電極23を備えている。   The semiconductor element 21 mounted on the semiconductor element mounting substrate 19 is, for example, a semiconductor integrated circuit element (IC, LSI), a micromachine (so-called MEMS element) or the like, and is integrated on the main surface of a semiconductor substrate (not indicated) such as silicon. Functional parts (not shown) such as movable parts such as circuits and switching mechanisms are formed. For example, a plurality of electrode terminals 22 electrically connected to the functional part are formed on the main surface of the semiconductor substrate on which the functional part is formed, and each electrode terminal 22 includes a protruding electrode 23.

突起電極23は、金や錫−鉛系はんだ,錫−銀系はんだ等の金属材料からなる。突起電極23は、例えば金からなる場合であれば、金からなるボンディングワイヤを電極端子22の表面に接合するとともに球状や円錐状等の所定の形状に加圧成形することや、めっき法で被着させること等の、いわゆるバンプ形成技術により形成される。   The protruding electrode 23 is made of a metal material such as gold, tin-lead solder, or tin-silver solder. If the protruding electrode 23 is made of, for example, gold, a bonding wire made of gold is bonded to the surface of the electrode terminal 22 and pressed into a predetermined shape such as a spherical shape or a conical shape, or coated by a plating method. It is formed by a so-called bump forming technique such as attaching.

絶縁基板11は、例えば四角板状に形成され、上面に半導体素子21が、いわゆるフリップ実装により実装される実装部11aを有している。絶縁基板11は、この実施の形態の例では平板状であるが、上面に半導体素子21を収容する凹部(キャビティ)(図示せず)を有し、凹部の底面を実装部11aとしたものでもよい。   The insulating substrate 11 is formed in, for example, a square plate shape, and has a mounting portion 11a on which the semiconductor element 21 is mounted by so-called flip mounting. The insulating substrate 11 has a flat plate shape in the example of this embodiment, but has a recess (cavity) (not shown) for housing the semiconductor element 21 on the top surface, and the bottom surface of the recess is the mounting portion 11a. Good.

絶縁基板11は、酸化アルミニウム質焼結体やガラスセラミック焼結体,窒化アルミニウム質焼結体,ムライト質焼結体等のセラミック焼結体、エポキシ樹脂、ポリイミド樹脂等の有機樹脂、または酸化アルミニウム等の無機粉末をエポキシ樹脂等の有機樹脂で結合してなる複合材料等の電気絶縁材料により形成されている。   The insulating substrate 11 is an aluminum oxide sintered body, a glass ceramic sintered body, a ceramic sintered body such as an aluminum nitride sintered body, a mullite sintered body, an organic resin such as an epoxy resin or a polyimide resin, or an aluminum oxide. Etc. are formed of an electrically insulating material such as a composite material formed by bonding an inorganic powder such as an epoxy resin with an organic resin.

絶縁基板11の実装部11aには、半導体素子21の下面の複数の突起電極23に対向するように、複数の電極パッド12が形成されている。   A plurality of electrode pads 12 are formed on the mounting portion 11 a of the insulating substrate 11 so as to face the plurality of protruding electrodes 23 on the lower surface of the semiconductor element 21.

この電極パッド12は、突起電極23を接合させて半導体素子21を実装するためのものであり、また、半導体素子21の電極端子22を外部の電気回路(図示せず)に電気的に接続させる導電路の一部として機能する。この場合、例えば、電極パッド12を、電極パッド12から絶縁基板11の側面や下面等の外表面にかけて形成された配線導体(図示せず)を介して実装部11aの外側に電気的に導出させておく。すなわち、半導体素子21の突起電極23を半導体素子実装用基板19の電極パッド12に接合するとともに、配線導体のうち絶縁基板11の外表面に露出している部分を外部の電気回路に電気的に接続することにより、半導体素子21の電極端子22が、突起電極23,電極パッド12および配線導体を介して外部の電気回路と電気的に接続される。   The electrode pad 12 is for mounting the semiconductor element 21 by bonding the protruding electrode 23, and electrically connecting the electrode terminal 22 of the semiconductor element 21 to an external electric circuit (not shown). It functions as a part of the conductive path. In this case, for example, the electrode pad 12 is electrically led out to the outside of the mounting portion 11a through a wiring conductor (not shown) formed from the electrode pad 12 to an outer surface such as a side surface or a lower surface of the insulating substrate 11. Keep it. That is, the protruding electrode 23 of the semiconductor element 21 is bonded to the electrode pad 12 of the semiconductor element mounting substrate 19, and the portion of the wiring conductor exposed on the outer surface of the insulating substrate 11 is electrically connected to an external electric circuit. By connecting, the electrode terminal 22 of the semiconductor element 21 is electrically connected to an external electric circuit through the protruding electrode 23, the electrode pad 12, and the wiring conductor.

なお、電極パッド12や配線導体は、タングステン,モリブデン,マンガン,銅,銀,パラジウム,金等の金属材料からなり、メタライズ層や蒸着層,金属箔,めっき層等の形態で絶縁基板11に形成される。   The electrode pad 12 and the wiring conductor are made of a metal material such as tungsten, molybdenum, manganese, copper, silver, palladium, or gold, and are formed on the insulating substrate 11 in the form of a metallized layer, a vapor deposition layer, a metal foil, a plating layer, or the like. Is done.

このような、突起電極23の電極パッド12に対する接合は、本発明においては超音波ボンディングにより行なわれる。超音波ボンディングによる突起電極23と電極パッド12との接合は、例えば、突起電極23が電極パッド12に対向するように位置合わせして半導体素子12を実装部11aに載置するとともに電極パッド12に突起電極23を当接させて、半導体素子12の上面から超音波を印加し、突起電極23と電極パッド12とを超音波接合することにより行なわれる。この場合、印加された超音波のエネルギーで突起電極23が振動(主として左右方向(絶縁基板11の上面や半導体素子21の下面に平行な方向)の往復運動)して電極パッド12との当接面で摩擦熱が発生し、突起電極23と電極パッド12との当接面に局部的な溶融が生じて接合が行なわれる。   Such bonding of the protruding electrode 23 to the electrode pad 12 is performed by ultrasonic bonding in the present invention. The bonding between the protruding electrode 23 and the electrode pad 12 by ultrasonic bonding is performed, for example, by aligning the protruding electrode 23 so as to face the electrode pad 12 and placing the semiconductor element 12 on the mounting portion 11a. The protruding electrode 23 is brought into contact with each other, ultrasonic waves are applied from the upper surface of the semiconductor element 12, and the protruding electrode 23 and the electrode pad 12 are ultrasonically bonded. In this case, the protruding electrode 23 vibrates (mainly the reciprocating motion in the left-right direction (the direction parallel to the upper surface of the insulating substrate 11 and the lower surface of the semiconductor element 21)) by the energy of the applied ultrasonic waves and comes into contact with the electrode pad 12. Frictional heat is generated on the surface, and local melting occurs on the contact surface between the protruding electrode 23 and the electrode pad 12, and bonding is performed.

なお、印加される超音波は、例えば突起電極23が金からなる場合であれば、振動数が約20〜100kHzの超音波が適当である。また、超音波を半導体素子21の上面から印加するときに、その半導体素子21を上面から下方向に加圧して、超音波エネルギーを効果的に当接面に伝えるようにしてもよい。   For example, when the protruding electrode 23 is made of gold, an ultrasonic wave having an oscillation frequency of about 20 to 100 kHz is appropriate. Further, when ultrasonic waves are applied from the upper surface of the semiconductor element 21, the semiconductor element 21 may be pressed downward from the upper surface to effectively transmit ultrasonic energy to the contact surface.

また、本発明の半導体素子実装用基板19において、電極パッド12は、突起電極23が当接する領域の中央部12aが外周部12bよりも低く、かつ中央部12aと外周部12bとの間に環状に隙間12cが設けられている。   In the semiconductor element mounting substrate 19 of the present invention, the electrode pad 12 has an annular portion between the central portion 12a and the outer peripheral portion 12b, and the central portion 12a of the region where the protruding electrode 23 abuts is lower than the outer peripheral portion 12b. Is provided with a gap 12c.

このように、電極パッド12について、突起電極23が当接する領域の中央部12aが外周部12bよりも低く、かつその中央部12aと外周部12bとの間に環状に隙間12cが設けられていることから、超音波エネルギーで振動する半導体素子21の突起電極23と、電極パッド12の中央部12aの上面および外周部12bの内側面から上面にかかる部分とがお互いに噛み合うようになり、また突起電極23の振動する範囲が電極パッド12の外周部12bの内側面等で制限されることで、フリップチップ実装における突起電極23の位置ずれ等の接合不良の発生をなくすことができる。   As described above, in the electrode pad 12, the central portion 12a of the region where the protruding electrode 23 abuts is lower than the outer peripheral portion 12b, and the annular gap 12c is provided between the central portion 12a and the outer peripheral portion 12b. Therefore, the protruding electrode 23 of the semiconductor element 21 that vibrates with ultrasonic energy and the upper surface of the central portion 12a of the electrode pad 12 and the portion that extends from the inner surface to the upper surface of the outer peripheral portion 12b come into mesh with each other, and the protrusion Since the range in which the electrode 23 vibrates is limited by the inner surface of the outer peripheral portion 12b of the electrode pad 12, it is possible to eliminate the occurrence of bonding failure such as misalignment of the protruding electrode 23 in flip chip mounting.

また、突起電極23と接続パッド12の外周部12bの内側面との接合面が水平面に対して直交または傾斜することから、突起電極23と接続パッド12との接合部分に作用する水平方向の応力に対して接合強度を向上させることができる。   Further, since the bonding surface between the protruding electrode 23 and the inner surface of the outer peripheral portion 12b of the connection pad 12 is orthogonal or inclined with respect to the horizontal plane, the horizontal stress acting on the bonding portion between the protruding electrode 23 and the connection pad 12 In contrast, the bonding strength can be improved.

また、電極パッド12の中央部12aと外周部12bとの間に環状に隙間12cが設けられていることから、超音波ボンディング時において、突起電極23と電極パッド12との接合面付近で、突起電極23内に生じる内部応力を、例えば突起電極23の、隙間12cに面した部分での微小な変形等により効果的に緩和することができる。   Further, since the annular gap 12c is provided between the central portion 12a and the outer peripheral portion 12b of the electrode pad 12, a protrusion is formed near the joint surface between the protruding electrode 23 and the electrode pad 12 during ultrasonic bonding. The internal stress generated in the electrode 23 can be effectively relieved by, for example, minute deformation of the protruding electrode 23 at the portion facing the gap 12c.

そのため、絶縁基板11に水平な方向の応力に対しても強い接合構造とすることができるとともに、応力の残留等に起因する突起電極23の機械的な破壊等を効果的に防止することができる、実装信頼性の向上した半導体素子実装用基板19を提供することができる。   Therefore, it is possible to make the joint structure strong against the stress in the horizontal direction on the insulating substrate 11, and it is possible to effectively prevent mechanical destruction of the protruding electrode 23 due to residual stress and the like. Thus, the semiconductor element mounting substrate 19 with improved mounting reliability can be provided.

また、隙間12cは、突起電極23の、電極パッド12との接合面付近で生じる内部応力を突起電極23の全周にわたって有効に緩和させるために、円環状や楕円環状等の環状に設けられる。隙間12cは、全周にわたって同じ幅である必要はなく、部分的に幅が異なるものでもよい。   Further, the gap 12 c is provided in an annular shape such as an annular shape or an elliptical shape in order to effectively relieve internal stress generated in the vicinity of the joint surface of the protruding electrode 23 with the electrode pad 12 over the entire circumference of the protruding electrode 23. The gap 12c does not have to have the same width over the entire circumference, and may be partially different in width.

なお、電極パッド12の中央部12aと外周部12bとの高さの差は、突起電極23との当接および接合を容易かつ強固なものとするために、突起電極23の先端(下端)部分が中央部12aの上面に当接したときに、その突起電極23の先端部分に隣接する部分が外周部12bの内側面から上面にかかる部分に当接するような寸法に設定するとよい。   Note that the difference in height between the central portion 12a and the outer peripheral portion 12b of the electrode pad 12 is such that the tip (lower end) portion of the protruding electrode 23 is formed in order to make contact and bonding with the protruding electrode 23 easy and strong. Is set to a size such that when the electrode contacts the upper surface of the central portion 12a, the portion adjacent to the tip of the protruding electrode 23 contacts the portion on the upper surface from the inner surface of the outer peripheral portion 12b.

例えば、突起電極23が、直径が約150〜200μmの球状または半球状で、平面視したときの電極パッド12の外形寸法が突起電極23と同程度の場合であれば、電極パッド12は中央部12aと外周部12bとの高さの差が10〜20μmになるように形成すればよい。   For example, if the protruding electrode 23 has a spherical or hemispherical shape with a diameter of about 150 to 200 μm and the external dimensions of the electrode pad 12 when viewed in plan are approximately the same as the protruding electrode 23, the electrode pad 12 has a central portion. What is necessary is just to form so that the difference of the height of 12a and the outer peripheral part 12b may be 10-20 micrometers.

このような、中央部12aと外周部12bとの高さの差が10〜20μmの電極パッド12は、例えば電極パッド12の絶縁基板11に対する接合強度や半導体素子実装用基板19の生産性,経済性等を考慮して、中央部12aの高さを10〜15μm程度とし、外周部12bの高さを20〜35μm程度として形成する。   Such an electrode pad 12 having a height difference of 10 to 20 μm between the central portion 12a and the outer peripheral portion 12b is, for example, the bonding strength of the electrode pad 12 to the insulating substrate 11, the productivity of the semiconductor element mounting substrate 19, and the economy. In consideration of the properties, the height of the central portion 12a is set to about 10 to 15 μm, and the height of the outer peripheral portion 12b is set to about 20 to 35 μm.

また、電極パッド12の隙間12cは、突起電極23の内部応力を緩和させる上では幅が広いほど効果が高いものの、広くしすぎると突起電極23との接合面積自体が小さくなりすぎ、かえって実装信頼性を向上させることが難しくなる傾向がある。そのため、隙間12cの幅は、例えば、電極パッド12の外形が直径150〜200μmの円形状または1辺の長さが150〜200μmの四角形状で、その内側に円環状に隙間12cが形成されているような場合には、隙間12cは10〜50μm程度の幅で設けることが好ましい。   The gap 12c between the electrode pads 12 is more effective in reducing the internal stress of the bump electrode 23. However, if the gap 12c is too wide, the bonding area itself with the bump electrode 23 becomes too small. Tend to be difficult to improve. Therefore, the width of the gap 12c is, for example, a circular shape with an outer shape of the electrode pad 12 having a diameter of 150 to 200 μm or a square shape with a side length of 150 to 200 μm, and the gap 12c is formed in an annular shape on the inside. In such a case, the gap 12c is preferably provided with a width of about 10 to 50 μm.

また、このような半導体素子実装用基板19において、隙間12cは、超音波による突起電極23の左右方向の振動と交差する側が他の部位よりも広い場合には、突起電極23と電極パッド12との接合される範囲(接合面)のうち、接合面が長く(広く)なる傾向のある側において隙間12cを広く取ることができる。そのため、その広い接合面に生じる可能性のある、より強い内部応力をさらに効果的に緩和することができる。従って、この場合には、実装信頼性を向上させる上でより有効な半導体素子実装用基板19を提供することができる。   Further, in such a semiconductor element mounting substrate 19, when the gap 12 c is wider than the other part on the side intersecting the left-right vibration of the protruding electrode 23 due to the ultrasonic wave, the protruding electrode 23 and the electrode pad 12 The gap 12c can be widened on the side where the joining surface tends to be long (wide) in the joining range (joining surface). Therefore, it is possible to more effectively relieve stronger internal stress that may occur on the wide joint surface. Therefore, in this case, the semiconductor element mounting substrate 19 that is more effective in improving the mounting reliability can be provided.

例えば、前述したような、直径150〜200μmの円形状または1辺の長さが150〜200μmの四角形状の外形で、中央部12aの高さが10〜15μm程度、外周部12bの高さが20〜35μm程度であるとともに、平面視したときの中央部12aが直径40μm程度の円形状の電極パッド12の場合であれば、隙間12cの幅は、超音波の振動方向の両端側において40〜50μm程度とし、その他の部位において10〜30μm程度として、両者の差を20〜30μm程度とする。   For example, as described above, a circular outer shape with a diameter of 150 to 200 μm or a rectangular outer shape with a side length of 150 to 200 μm, the height of the central portion 12a is about 10 to 15 μm, and the height of the outer peripheral portion 12b is If the central portion 12a when viewed in plan is a circular electrode pad 12 having a diameter of about 40 μm, the width of the gap 12c is 40 to 40 at both ends in the ultrasonic vibration direction. The difference between the two is about 20-30 μm, with about 50 μm being about 10-30 μm at other sites.

なお、図1(a)では、長方形状の電極パッド12の長辺方向に超音波の印加による振動が加わる例であり、隙間12cが両短辺側で広くなっている例を示している。   FIG. 1A shows an example in which vibration due to application of ultrasonic waves is applied in the long side direction of the rectangular electrode pad 12, and an example in which the gap 12c is wide on both short sides.

また、このような半導体素子実装用基板19において、電極パッド12は、下地導体層13(13a,13b)の上に中央部12aと外周部12bとで厚みの異なるめっき層14(14a,14b)が被着されている場合には、例えば数μm程度の厚さで精度よく形成することができるとともに、その厚さの調節が容易なめっき層14(14a,14b)により中央部12aおよび外周部12の高さの調節ができる。そのため、中央部12aが外周部12bよりも低い電極パッド12がより高い精度で形成された半導体素子実装用基板19を提供することができる。   Further, in such a semiconductor element mounting substrate 19, the electrode pad 12 is formed on the base conductor layer 13 (13a, 13b) with the plating layer 14 (14a, 14b) having a thickness different between the central portion 12a and the outer peripheral portion 12b. Can be accurately formed with a thickness of, for example, several μm, and the central portion 12a and the outer peripheral portion can be formed by the plating layer 14 (14a, 14b) whose thickness can be easily adjusted. 12 height adjustments are possible. Therefore, it is possible to provide the semiconductor element mounting substrate 19 in which the electrode pads 12 having the central portion 12a lower than the outer peripheral portion 12b are formed with higher accuracy.

下地導体層13(13a,13b)は、例えば、タングステンやモリブデン,マンガン,銅,銀,パラジウム,金等の金属材料からなる。このような下地導体層13(13a,13b)は、例えばメタライズ層や金属箔,めっき層等の形態で絶縁基板11の実装部11aに形成される。   The underlying conductor layer 13 (13a, 13b) is made of a metal material such as tungsten, molybdenum, manganese, copper, silver, palladium, or gold. Such a base conductor layer 13 (13a, 13b) is formed on the mounting portion 11a of the insulating substrate 11 in the form of, for example, a metallized layer, a metal foil, or a plated layer.

また、めっき層14(14a,14b)は、ニッケルや銅,金,パラジウム等の金属材料からなり、電解めっき法や無電解めっき法等のめっき法で下地導体層13(13a,13b)の表面に被着される。   The plating layer 14 (14a, 14b) is made of a metal material such as nickel, copper, gold, palladium, and the surface of the underlying conductor layer 13 (13a, 13b) by a plating method such as an electrolytic plating method or an electroless plating method. To be attached.

そして、半導体素子実装用基板19の実装部11aに形成されている電極パッド12に半導体素子21の突起電極23を接合して半導体素子21を実装部11aに実装し、必要に応じて半導体素子21を蓋体や封止樹脂等の封止手段(図示せず)で気密封止することにより、本発明の半導体装置が製作される。なお、前述したように、半導体素子21と半導体素子実装用基板12とを離して描いているが、実際には、半導体装置30において、半導体素子21の突起電極23が半導体素子実装用基板19の電極パッド12の中央部12aおよび外周部12bに当接し、中央部12aと外周部12bとの間に隙間12cを有した状態で接合されている。   Then, the protruding electrode 23 of the semiconductor element 21 is bonded to the electrode pad 12 formed on the mounting portion 11a of the semiconductor element mounting substrate 19, and the semiconductor element 21 is mounted on the mounting portion 11a. Is hermetically sealed with a sealing means (not shown) such as a lid or a sealing resin, whereby the semiconductor device of the present invention is manufactured. As described above, the semiconductor element 21 and the semiconductor element mounting substrate 12 are drawn apart from each other. However, in actuality, in the semiconductor device 30, the protruding electrode 23 of the semiconductor element 21 is formed on the semiconductor element mounting substrate 19. The electrode pad 12 is in contact with the central portion 12a and the outer peripheral portion 12b, and is joined with a gap 12c between the central portion 12a and the outer peripheral portion 12b.

図1(b)に示す半導体装置30は、本発明の半導体装置の実施の形態の一例である。この半導体装置30は、絶縁基板11の上面に、下面に複数の電極端子22が形成されてその電極端子22に突起電極23を備えた半導体素子21を実装するための、電極端子22とそれぞれ対向する複数の電極パッド12が形成された実装部11aを有して成る半導体素子実装用基板19と、下面に複数の電極端子22が形成されてその電極端子22に突起電極23を備えるとともに、超音波ボンディングにより突起電極23が電極パッド12に接合されて実装部11aに実装された半導体素子21とを備えている。また、この半導体装置30は、突起電極23と電極パッド12との接合領域の中央部12aと外周部12bとの間に環状の隙間12cを有している。   A semiconductor device 30 shown in FIG. 1B is an example of an embodiment of a semiconductor device of the present invention. The semiconductor device 30 is opposed to the electrode terminals 22 for mounting a semiconductor element 21 having a plurality of electrode terminals 22 formed on the lower surface of the insulating substrate 11 and having protruding electrodes 23 on the electrode terminals 22. A semiconductor element mounting substrate 19 having a mounting portion 11a on which a plurality of electrode pads 12 are formed, a plurality of electrode terminals 22 formed on the lower surface, and a protruding electrode 23 on the electrode terminal 22; The protruding electrode 23 is joined to the electrode pad 12 by sonic bonding, and the semiconductor element 21 is mounted on the mounting portion 11a. Further, the semiconductor device 30 has an annular gap 12c between the central portion 12a and the outer peripheral portion 12b of the bonding region between the protruding electrode 23 and the electrode pad 12.

半導体装置30は、上記構成を備え、超音波ボンディングされた突起電極23と電極パッド12との接合領域の中央部12aと外周部12bとの間に環状の隙間12cを有していることから、超音波印加時において、突起電極23と電極パッド12との接合面付近で、突起電極23内に生じていた内部応力が、例えば突起電極23の隙間12cに面する部分での微細な変形等により効果的に緩和されて、突起電極23の内部等に残留していないものとすることができる。   Since the semiconductor device 30 has the above-described configuration and has an annular gap 12c between the central portion 12a and the outer peripheral portion 12b of the bonding region between the ultrasonic bonded bump electrode 23 and the electrode pad 12, When ultrasonic waves are applied, the internal stress generated in the protruding electrode 23 in the vicinity of the bonding surface between the protruding electrode 23 and the electrode pad 12 is caused by, for example, minute deformation in a portion facing the gap 12c of the protruding electrode 23. It can be effectively relaxed and not left inside the protruding electrode 23 or the like.

そのため、絶縁基板11に水平な方向の応力に対しても強い接合構造とすることができるとともに、応力の残留等に起因する突起電極23の機械的な破壊等を効果的に防止することができる、長期の実装信頼性の向上した半導体装置30を提供することができる。   Therefore, it is possible to make the joint structure strong against the stress in the horizontal direction on the insulating substrate 11, and it is possible to effectively prevent mechanical destruction of the protruding electrode 23 due to residual stress and the like. The semiconductor device 30 with improved long-term mounting reliability can be provided.

また、この半導体装置30は、環状の隙間12cは、超音波ボンディングの際に印加される超音波による突起電極23の左右方向の振動と交差する側の幅が他の部位における幅よりも広い場合には、次のような効果がある。   Further, in the semiconductor device 30, the annular gap 12c is such that the width on the side intersecting with the vibration in the left-right direction of the protruding electrode 23 by the ultrasonic wave applied at the time of ultrasonic bonding is wider than the width at the other part. Has the following effects.

すなわち、突起電極23と電極パッド12の接合される範囲(接合面)のうち、振動に伴う突起電極23の振動幅が大きいために接合面が長く(広く)なる傾向のある側(振動する左右方向の側)において、隙間12cを広く取ることが好ましい。これにより、その広い接合面に生じる可能性のあるより強い内部応力をさらに効果的に緩和することができる。従って、この場合には、長期の実装信頼性をさらに向上させる上で有効な半導体装置30を提供することができる。   That is, in the range (bonding surface) where the protruding electrode 23 and the electrode pad 12 are bonded, the bonding electrode tends to become longer (wider) because the vibration width of the protruding electrode 23 due to vibration is large (the vibrating left and right sides). On the direction side), it is preferable to widen the gap 12c. Thereby, it is possible to more effectively relieve the stronger internal stress that may occur on the wide joint surface. Therefore, in this case, it is possible to provide the semiconductor device 30 effective in further improving long-term mounting reliability.

また、本発明の半導体装置30は、電極パッド12は、下地導体層13(13a,13b)の上に中央部12aと外周部12bとで厚みの異なるめっき層14(14a,14b)が被着されている場合には、例えば数μm程度の厚さで精度よく形成することができるとともに、その厚さの調節が容易なめっき層14(14a,14b)により中央部12aおよび外周部12bの厚さの調節ができる。そのため、中央部12aが外周部12bよりも低い電極パッド12をより高い精度で形成することができ、電極パッド12と突起電極23との間で十分な隙間12cを有するより信頼性の高い半導体装置30を提供することができる。また、電極パッド12の高さの精度が高く、電極パッド12の中央部12aおよび外周部12bに突起電極23をより容易に精度よく当接させることができるため、電極パッド12と突起電極23との超音波ボンディングによる接合がより容易に行なえるので、半導体装置30としての生産性を向上させる上で有効である。   Further, in the semiconductor device 30 of the present invention, the electrode pad 12 is coated with the plating layers 14 (14a, 14b) having different thicknesses at the central portion 12a and the outer peripheral portion 12b on the underlying conductor layer 13 (13a, 13b). In this case, for example, the thickness of the central portion 12a and the outer peripheral portion 12b can be accurately formed with a thickness of about several μm and the thickness of the central portion 12a and the outer peripheral portion 12b can be easily adjusted by the plating layer 14 (14a, 14b). You can adjust the height. Therefore, the electrode pad 12 having the central portion 12a lower than the outer peripheral portion 12b can be formed with higher accuracy, and a more reliable semiconductor device having a sufficient gap 12c between the electrode pad 12 and the protruding electrode 23. 30 can be offered. Further, since the height accuracy of the electrode pad 12 is high, and the protruding electrode 23 can be brought into contact with the central portion 12a and the outer peripheral portion 12b of the electrode pad 12 more easily and accurately, the electrode pad 12 and the protruding electrode 23 Since the bonding by the ultrasonic bonding can be performed more easily, it is effective in improving the productivity as the semiconductor device 30.

(半導体素子実装用基板の製造方法)
本発明の半導体素子実装用基板19の製造方法を、図2を参照しつつ説明する。図2(a)および(b)は、それぞれ図1に示す半導体素子実装用基板19の製造方法の実施の形態の一例を工程順に示す断面図である。図2において図1と同様の部位には同様の符号を付している。
(Manufacturing method of semiconductor element mounting substrate)
A method for manufacturing the semiconductor element mounting substrate 19 of the present invention will be described with reference to FIG. FIGS. 2A and 2B are cross-sectional views showing an example of an embodiment of a method for manufacturing the semiconductor element mounting substrate 19 shown in FIG. In FIG. 2, the same parts as those in FIG.

まず、図2(a)に示すように、絶縁基板11の上面に、下面に複数の電極端子22が形成されて電極端子22に突起電極23を備えた半導体素子21を実装するための、突起電極23がそれぞれ当接されるとともに半導体素子21の上面から超音波が印加されて接合される複数の電極パッド12となる下地導体層13(13a,13b)を形成する。   First, as shown in FIG. 2A, a protrusion for mounting a semiconductor element 21 having a plurality of electrode terminals 22 formed on the lower surface of the insulating substrate 11 and having a protruding electrode 23 on the electrode terminal 22 is mounted. Underlying conductor layers 13 (13a, 13b) to be a plurality of electrode pads 12 to be bonded are formed by contacting the electrodes 23 and applying ultrasonic waves from the upper surface of the semiconductor element 21.

絶縁基板11は、前述のように、セラミック材料や有機樹脂,無機粉末と有機樹脂との複合材料等の電気絶縁材料により形成されている。   As described above, the insulating substrate 11 is formed of an electrically insulating material such as a ceramic material, an organic resin, or a composite material of an inorganic powder and an organic resin.

絶縁基板11は、例えば酸化アルミニウム質焼結体からなる場合には以下のようにして製作することができる。まず、酸化アルミニウム,酸化珪素,酸化カルシウム,酸化マグネシウム等の原料粉末に適当な有機バインダ,溶剤を添加混合して泥漿状のセラミックスラリーを作製し、このセラミックスラリーをドクターブレード法やカレンダーロール法等のシート成形技術を採用してシート状となすことによって、複数のセラミックグリーンシート(図示せず)を形成する。しかる後、セラミックグリーンシートを所定の順に上下に積層するとともに、還元雰囲気中で約1600℃の高温で焼成することによって、絶縁基板11が製作される。   When the insulating substrate 11 is made of, for example, an aluminum oxide sintered body, it can be manufactured as follows. First, an appropriate organic binder and solvent are added to and mixed with raw material powders such as aluminum oxide, silicon oxide, calcium oxide, and magnesium oxide to produce a slurry ceramic slurry, and this ceramic slurry is subjected to a doctor blade method, a calender roll method, etc. A plurality of ceramic green sheets (not shown) are formed by adopting the sheet forming technique to form a sheet. Thereafter, the ceramic green sheets are laminated in a predetermined order and fired at a high temperature of about 1600 ° C. in a reducing atmosphere, whereby the insulating substrate 11 is manufactured.

また、絶縁基板11は、有機樹脂からなる場合であれば、例えばエポキシ樹脂やポリイミド樹脂等の樹脂材料の未硬化物をガラス布に塗布してシート状に加工した後、熱や光(紫外線)を加えて硬化させることにより製作される。また、硬化した樹脂材料を基材とし、その表面にエポキシ樹脂等の有機樹脂の未硬化物の塗布および硬化を順次繰り返すことにより、多層の絶縁基板11として製作してもよい。   Further, if the insulating substrate 11 is made of an organic resin, for example, an uncured resin material such as an epoxy resin or a polyimide resin is applied to a glass cloth and processed into a sheet shape, and then heat or light (ultraviolet) is used. It is manufactured by adding and curing. Alternatively, a multilayer insulating substrate 11 may be manufactured by using a cured resin material as a base material and sequentially applying and curing an uncured organic resin such as an epoxy resin on the surface.

電極パッド12となる下地導体層13(13a,13b)は、タングステンやモリブデン,マンガン,銅,銀,パラジウム,金等の金属材料からなり、メタライズ層や蒸着層,金属箔,めっき層等の形態で絶縁基板11に形成される。   The underlying conductor layer 13 (13a, 13b) to be the electrode pad 12 is made of a metal material such as tungsten, molybdenum, manganese, copper, silver, palladium, or gold, and forms such as a metallized layer, a vapor deposition layer, a metal foil, or a plating layer Thus, the insulating substrate 11 is formed.

下地導体13(13a,13b)は、例えばタングステンのメタライズ層からなる場合であれば、タングステン粉末に有機溶剤、樹脂バインダ等を添加して作製した金属ペーストを、絶縁基板11となるセラミックグリーンシートの表面に、スクリーン印刷法等の印刷法で所定パターンに印刷することにより形成することができる。   If the base conductor 13 (13a, 13b) is made of, for example, a tungsten metallized layer, a metal paste prepared by adding an organic solvent, a resin binder, or the like to tungsten powder is used for the ceramic green sheet serving as the insulating substrate 11. The surface can be formed by printing a predetermined pattern by a printing method such as a screen printing method.

また、下地導体層13(13a,13b)は、例えば銅の金属箔(銅箔)からなる場合であれば、硬化した有機樹脂からなる絶縁基板11の表面に銅箔を、接着剤を用いて被着させた後、エッチング加工を施して所定パターンに加工することにより形成することができる。   Further, if the underlying conductor layer 13 (13a, 13b) is made of, for example, copper metal foil (copper foil), a copper foil is used on the surface of the insulating substrate 11 made of a cured organic resin, and an adhesive is used. After the deposition, the film can be formed by etching and processing into a predetermined pattern.

このような下地導体層13(13a,13b)を、実装部11aに実装される半導体素子21の下面の突起電極23とそれぞれ対向して当接されるような位置に形成するには、例えば、絶縁基板11の外縁や、絶縁基板11の上面にあらかじめ形成した位置決めマーク(図示せず)等を基準にして、スクリーン印刷用の版面を絶縁基板11に対して位置合わせすること等の位置決め方法を用いることができる。   In order to form such a base conductor layer 13 (13a, 13b) at a position where it contacts and faces the protruding electrode 23 on the lower surface of the semiconductor element 21 mounted on the mounting portion 11a, for example, A positioning method such as aligning the screen printing plate with the insulating substrate 11 with reference to the outer edge of the insulating substrate 11 or a positioning mark (not shown) formed in advance on the upper surface of the insulating substrate 11. Can be used.

また、下地導体層13(13a,13b)は、メタライズ層や蒸着層,金属箔,めっき層を組み合わせて形成するようにしてもよい。この場合には、例えば、前述のような方法でメタライズ層や金属箔からなる第1層(符号なし)を絶縁基板11の表面に形成した後、メタライズ層や金属箔の表面に、ニッケルや金,銅,パラジウム等のめっき層を電解めっき法や無電解めっき法で第2層(符号なし)として被着させることにより下地導体層13(13a,13b)が形成される。   The underlying conductor layer 13 (13a, 13b) may be formed by combining a metallized layer, a vapor deposition layer, a metal foil, and a plating layer. In this case, for example, after the first layer (not indicated) made of a metallized layer or metal foil is formed on the surface of the insulating substrate 11 by the method as described above, nickel or gold is formed on the surface of the metallized layer or metal foil. The base conductor layer 13 (13a, 13b) is formed by depositing a plating layer of copper, palladium, etc. as a second layer (no symbol) by an electrolytic plating method or an electroless plating method.

なお、この実施の形態の例では、電極パッド12の中央部12aと外周部12bとが、絶縁基板11の表面に達する隙間12cにより分離した例を示しているため、下地導体層13(13a,13b)は中央部12aに対応する部分13aと外周部12bに対応する部分13bとに分かれているが、下地導体層13(13a,13b)はつながった1つのパターン(円形状や楕円形状,四角形状等)で形成してもよい。   In the example of this embodiment, since the central portion 12a and the outer peripheral portion 12b of the electrode pad 12 are separated by the gap 12c reaching the surface of the insulating substrate 11, the underlying conductor layer 13 (13a, 13a, 13b) is divided into a portion 13a corresponding to the central portion 12a and a portion 13b corresponding to the outer peripheral portion 12b, but the underlying conductor layer 13 (13a, 13b) is one connected pattern (circular shape, elliptical shape, square shape). It may be formed in a shape or the like.

また、絶縁基板11に前述したような配線導体を形成する場合には、配線導体は、下地導体層13(13a,13b)と同様の材料を用い、同様の方法で絶縁基板11に被着させて形成することができる。   When the wiring conductor as described above is formed on the insulating substrate 11, the wiring conductor is made of the same material as that of the underlying conductor layer 13 (13a, 13b) and is attached to the insulating substrate 11 by the same method. Can be formed.

次に、図2(b)に示すように、下地導体層13(13a,13b)の表面に、突起電極23が当接する領域の中央部12aが外周部12bよりも低くなるとともに、その中央部12aと外周部12bとの間に環状の隙間12cが設けられるように、突起電極(図2では図示せず)が当接するめっき層14(14a,14b)を被着させて電極パッド12を形成する。   Next, as shown in FIG. 2B, the central portion 12a of the region where the protruding electrode 23 abuts on the surface of the underlying conductor layer 13 (13a, 13b) is lower than the outer peripheral portion 12b, and the central portion The electrode pad 12 is formed by depositing a plating layer 14 (14a, 14b) against which the protruding electrode (not shown in FIG. 2) abuts so that an annular gap 12c is provided between the outer periphery 12b and the outer periphery 12b. To do.

下地導体層13(13a,13b)の表面に、突起電極が当接する領域の中央部12aが外周部12bよりも低くなるとともに、その中央部12aと外周部12bとの間に環状の隙間12cが設けられるようにめっき層14(14a,14b)を被着させるには、例えば、下地導体層13(13a,13b)の中央部12aに対応する部分13aと外周部12bに対応する部分13bとの両方に一定の厚さで第1のめっき層(符号なし)を被着させた後、中央部12aに対応する部分を樹脂材料等でマスキングして、外周部12bに対応する部分13bのみに第2のめっき層(符号なし)を追加して被着させる等の方法を用いることができる。   On the surface of the underlying conductor layer 13 (13a, 13b), the central portion 12a of the region where the protruding electrodes abut is lower than the outer peripheral portion 12b, and an annular gap 12c is formed between the central portion 12a and the outer peripheral portion 12b. In order to deposit the plating layer 14 (14a, 14b) so as to be provided, for example, a portion 13a corresponding to the central portion 12a of the underlying conductor layer 13 (13a, 13b) and a portion 13b corresponding to the outer peripheral portion 12b are provided. After depositing the first plating layer (no symbol) on both sides with a constant thickness, the portion corresponding to the central portion 12a is masked with a resin material or the like, and only the portion 13b corresponding to the outer peripheral portion 12b is masked. For example, a method of adding and depositing two plating layers (without reference numerals) can be used.

また、下地導体層13(13a,13b)を、つながった1つのパターンで形成した場合には、隙間12cに対応する部分をマスキングしておいて、めっき層14(14a,14b)を被着させればよい。   Further, when the underlying conductor layer 13 (13a, 13b) is formed in a single connected pattern, the portion corresponding to the gap 12c is masked and the plating layer 14 (14a, 14b) is deposited. Just do it.

また、隙間12cに対応する狭い部分にマスキングすることは難しいので、次のようにして電極パッド12を形成してもよい。まず、図3(a)に示すように、つながった1つのパターンで形成された下地導体層13の外周から中央部12aに対応する部分の外周までの範囲を光硬化性樹脂等からなるマスキング材Mでマスキングして第1のめっき層14aを被着させる。その後、マスキング材Mを除去する。次に、図3(b)に示すように、下地導体層13の中心(中央)から外周部12bに対応する部分の内周までの範囲をマスキング材Mでマスキングして第2のめっき層14bを、中央部12aよりも外周部12bが高くなるように被着させる。そして、図3(c)に示すように、マスキング材Mを溶剤等で除去することにより、外周部12bが中央部12aより高い(中央部12aが外周部12bよりも低い)電極パッド12が形成される。なお、図3(a)〜(c)は、それぞれ本発明の半導体素子実装用基板の製造方法の実施の形態の他の例を工程順に示す断面図である。図3において図2と同様の部位には同様の符号を付している。   Further, since it is difficult to mask a narrow portion corresponding to the gap 12c, the electrode pad 12 may be formed as follows. First, as shown in FIG. 3 (a), a masking material made of a photo-curing resin or the like in a range from the outer periphery of the underlying conductor layer 13 formed by one connected pattern to the outer periphery of the portion corresponding to the central portion 12a. Mask with M to deposit the first plating layer 14a. Thereafter, the masking material M is removed. Next, as shown in FIG. 3B, the range from the center (center) of the underlying conductor layer 13 to the inner periphery of the portion corresponding to the outer peripheral portion 12b is masked with a masking material M, and the second plating layer 14b. Is attached such that the outer peripheral portion 12b is higher than the central portion 12a. Then, as shown in FIG. 3C, by removing the masking material M with a solvent or the like, the outer peripheral portion 12b is higher than the central portion 12a (the central portion 12a is lower than the outer peripheral portion 12b), thereby forming the electrode pad 12. Is done. FIGS. 3A to 3C are cross-sectional views showing other examples of the embodiment of the method for manufacturing a semiconductor element mounting substrate according to the present invention in the order of steps. 3, parts similar to those in FIG. 2 are denoted by the same reference numerals.

なお、被着させるめっき層14(14a,14b)は、ニッケル,銅,金等の金属材料からなるものが適している。このようなめっき層14(14a,14b)を被着させておくことにより、電極パッド12の酸化腐蝕を効果的に防止することができるとともに、半導体素子21の突起電極23の超音波ボンディングによる接合がより容易かつ強固に行なえる。   The plating layer 14 (14a, 14b) to be deposited is suitably made of a metal material such as nickel, copper, or gold. By depositing such a plating layer 14 (14a, 14b), it is possible to effectively prevent the oxidative corrosion of the electrode pad 12, and to join the protruding electrode 23 of the semiconductor element 21 by ultrasonic bonding. Is easier and more robust.

また、上記製造方法において、めっき層14(14a,14b)を被着させて電極パッド12を形成する工程の前に、例えば図4(a)に示すように、下地導体層13(13a,13b)を、中央部12aおよび外周部12bに対応する部分13a,13bが隙間12cを挟んで電気的に独立するように形成するとともに、絶縁基板11に、下地導体層13(13a,13b)の外周部12bに対応する部分のみから絶縁基板11の外縁にかけてめっき用引き出し線15を形成する工程を備える場合には、前述した工程による、突起電極23が当接する領域の中央部12aが外周部12bよりも低く、かつ中央部12aと外周部12bとの間に環状に隙間12cが設けられている電極パッド12を有する半導体素子実装用基板19を製造する方法を、より容易で生産性の高い製造方法とすることができる。   In the above manufacturing method, before the step of forming the electrode pad 12 by depositing the plating layer 14 (14a, 14b), for example, as shown in FIG. 4A, the underlying conductor layer 13 (13a, 13b) is formed. ) Are formed so that the portions 13a and 13b corresponding to the central portion 12a and the outer peripheral portion 12b are electrically independent with the gap 12c interposed therebetween, and the outer periphery of the underlying conductor layer 13 (13a and 13b) is formed on the insulating substrate 11. In the case of providing the step of forming the lead wire 15 for plating from only the portion corresponding to the portion 12b to the outer edge of the insulating substrate 11, the central portion 12a of the region where the protruding electrode 23 abuts from the outer peripheral portion 12b by the above-described step. And a method for manufacturing a semiconductor element mounting substrate 19 having an electrode pad 12 having a low gap and an annular gap 12c provided between the central portion 12a and the outer peripheral portion 12b. It can be.

すなわち、隙間12cを挟んで電気的に独立し、電極パッド12の中央部12aおよび外周部12bに対応する部分が隙間12cを挟んで電気的に独立するように形成された下地導体層13(13a,13b)は、図4(b)に示すように、外周部12bに対応する部分13bのみに電解めっき法によりめっき層14bbを被着させることができる。また、中央部に対応する部分13aを含む下地導体層13の全体には、図4(c)に示すように、無電解めっき法によりめっき層14a,14baを被着させることが可能であり、中央部12aに対応する部分13aにも所定の厚さでめっき層14aを被着させることができる。   That is, the underlying conductor layer 13 (13a) is formed such that the gap 12c is electrically independent and the portions corresponding to the central portion 12a and the outer peripheral portion 12b of the electrode pad 12 are electrically independent across the gap 12c. , 13b), as shown in FIG. 4 (b), the plating layer 14bb can be applied only to the portion 13b corresponding to the outer peripheral portion 12b by the electrolytic plating method. In addition, as shown in FIG. 4C, plating layers 14a and 14ba can be deposited on the entire base conductor layer 13 including the portion 13a corresponding to the central portion by an electroless plating method. The plating layer 14a can be applied to the portion 13a corresponding to the central portion 12a with a predetermined thickness.

そのため、例えば無電解めっき法により被着されるめっき層14baに加えて電解めっき法によるめっき層14bbの被着も可能な外周部12bに対応する部分13bには、中央部12aに対応する部分13aよりもめっき層14b(14ba,14bb)を厚く(高く)被着させることができる。また、外周部12bに対応する部分13bに無電解めっき層14baを被着させなくても、電解めっきの条件(時間や電流密度等)を調整すれば、電解めっき法だけで十分に厚い(高い)めっき層(図示せず)を形成することも容易である。   Therefore, for example, in addition to the plating layer 14ba deposited by the electroless plating method, the portion 13b corresponding to the outer peripheral portion 12b on which the plating layer 14bb can be deposited by the electrolytic plating method includes the portion 13a corresponding to the central portion 12a. It is possible to deposit the plating layer 14b (14ba, 14bb) thicker (higher) than that. Further, even if the electroless plating layer 14ba is not deposited on the portion 13b corresponding to the outer peripheral portion 12b, if the conditions (time, current density, etc.) of the electroplating are adjusted, the electroplating method alone is sufficiently thick (high) It is also easy to form a plating layer (not shown).

また、この場合には、マスキング等の工程が不要であり、例えば、めっき用の電流を供給するためのめっき用の治具の端子(図示せず)をめっき用引き出し線15に接続するだけで、下地導体層13(13a,13b)のうち外周部12bに対応する部分13bのみに厚くめっき層14bを被着させることができる。そのため、突起電極23が当接する領域の中央部12aが外周部12bよりも低い電極パッド12の形成が容易である。なお、図4(a)〜(c)は、図1に示す半導体素子実装用基板19の製造方法の実施の形態の他の例について工程順に要部を拡大して示す断面図である。図4において図1と同様の部位には同様の符号を付している。   Further, in this case, a process such as masking is not required. For example, a plating jig terminal (not shown) for supplying a plating current is simply connected to the lead wire 15 for plating. The thick plating layer 14b can be applied only to the portion 13b corresponding to the outer peripheral portion 12b of the underlying conductor layer 13 (13a, 13b). Therefore, it is easy to form the electrode pad 12 in which the central portion 12a of the region where the protruding electrode 23 abuts is lower than the outer peripheral portion 12b. FIGS. 4A to 4C are cross-sectional views showing enlarged main parts in order of processes in another example of the embodiment of the method for manufacturing the semiconductor element mounting substrate 19 shown in FIG. 4, parts similar to those in FIG. 1 are denoted by the same reference numerals.

めっき用引き出し線15は、前述した下地導体層13(13a,13b)と同様の材料を用い、同様の方法で形成することができる。また、絶縁基板11に配線導体を形成する場合であれば、配線導体と同時に(例えば同じスクリーン印刷用の版面を用いて)形成して、半導体素子実装用基板19の生産性を良好に確保するようにしてもよい。   The lead wire 15 for plating can be formed by the same method using the same material as that of the base conductor layer 13 (13a, 13b) described above. In the case where a wiring conductor is formed on the insulating substrate 11, it is formed simultaneously with the wiring conductor (for example, using the same screen printing plate) to ensure good productivity of the semiconductor element mounting substrate 19. You may do it.

無電解めっき法によるめっきは、例えばニッケルめっき層であれば、硫酸ニッケルや塩化ニッケル等のニッケルの供給源となるニッケル化合物と、次亜リン酸ナトリウムやジメチルアミンボラン(DMAB)等の還元剤とを主成分とし、錯化剤や安定剤,pH調整剤等が添加された無電解ニッケルめっき液を用いて行なうことができる。   For electroless plating, for example, if it is a nickel plating layer, a nickel compound such as nickel sulfate or nickel chloride and a reducing agent such as sodium hypophosphite or dimethylamine borane (DMAB) Can be carried out using an electroless nickel plating solution containing, as a main component, and a complexing agent, stabilizer, pH adjuster and the like.

この場合、還元剤として次亜リン酸ナトリウムを用いた無電解めっき液により被着されるめっき層14a,14ba(ニッケル)は、共析するリン成分の作用により、その硬度(マイクロビッカース硬度)が約600〜700と高く、電解めっき法により被着されるめっき層14bb(ニッケル)の硬度(約400〜500)に比べて硬い。そのため、電極パッド12と突起電極23との超音波ボンディングによる接合の際に加えられる超音波エネルギーの減衰をより小さく抑えることができ、接合強度を高める上で有効である。   In this case, the plating layers 14a and 14ba (nickel) deposited by the electroless plating solution using sodium hypophosphite as the reducing agent have a hardness (micro Vickers hardness) due to the action of the eutectoid phosphorus component. It is as high as about 600 to 700, and is harder than the hardness (about 400 to 500) of the plating layer 14bb (nickel) deposited by the electrolytic plating method. For this reason, attenuation of ultrasonic energy applied when the electrode pad 12 and the protruding electrode 23 are bonded by ultrasonic bonding can be further reduced, which is effective in increasing the bonding strength.

なお、この方法で半導体素子実装用基板19を製作した場合には、電極パッド12の中央部12aと外周部12bとが電気的に独立するため、いずれか一方が突起電極23(電極端子22)を外部の電気回路に電気的に接続する導電路として機能し、他方が接合の強度を補強する補強用のパッドとして機能するものとすることができる。   When the semiconductor element mounting substrate 19 is manufactured by this method, since the central portion 12a and the outer peripheral portion 12b of the electrode pad 12 are electrically independent, one of them is the protruding electrode 23 (electrode terminal 22). Can function as a conductive path that is electrically connected to an external electric circuit, and the other functions as a reinforcing pad that reinforces the strength of the joint.

また、この製造方法の場合に、電解めっき法によるめっき層14bbを被着させた後、めっき用引き出し線15の露出部分を、絶縁基板11の表面から研磨等の方法で除去する工程を追加するようにしてもよい。   Further, in the case of this manufacturing method, after the plating layer 14bb is deposited by the electrolytic plating method, a step of removing the exposed portion of the lead wire 15 for plating from the surface of the insulating substrate 11 by a method such as polishing is added. You may do it.

また、図4では、先に電解めっき層14bbを下地導体層13のうち外周部に対応する部分13bに被着させた例を示しているが、先に無電解めっき法によるめっき層14ba,14aを下地導体層13(13a,13b)の全域または中央部に対応する部分13aのみに被着させた後、外周部に対応する部分13bのみに電解めっき法によるめっき層14bbを被着させるようにしてもよい。   FIG. 4 shows an example in which the electrolytic plating layer 14bb is first deposited on the portion 13b corresponding to the outer peripheral portion of the underlying conductor layer 13, but the plating layers 14ba and 14a by the electroless plating method are first shown. Is applied to only the portion 13a corresponding to the entire region or the central portion of the base conductor layer 13 (13a, 13b), and then the plating layer 14bb by the electrolytic plating method is applied only to the portion 13b corresponding to the outer peripheral portion. May be.

また、上記製造方法において、めっき層14(14a,14b)を被着させて電極パッド12を形成する工程の前に、例えば図5(a)に示すように、下地導体層13(13a,13b)を、中央部12aおよび外周部12bに対応する部分13a,13bが隙間12cを挟んで電気的に独立するように形成するとともに、絶縁基板11に、下地導体層13(13a,13b)の中央部12aおよび外周部12bに対応する部分13a,13bのうち少なくとも中央部12aに対応する部分13aから絶縁基板11の外縁にかけて第1のめっき用引き出し線16aを形成する工程と、外周部12bに対応する部分13bのみから絶縁基板11の外縁にかけて第2のめっき用引き出し線16bを形成する工程とを備える場合には、前述した工程による、突起電極23が当接する領域の中央部12aが外周部12bよりも低く、かつ中央部12aと外周部12bとの間に環状に隙間12cが設けられている電極パッド12を有する半導体素子実装用基板19を製造する方法を、より容易で生産性の高い製造方法とすることができる。   In the above manufacturing method, before the step of forming the electrode pad 12 by depositing the plating layer 14 (14a, 14b), for example, as shown in FIG. 5A, the underlying conductor layer 13 (13a, 13b) is formed. ) Are formed so that the portions 13a and 13b corresponding to the central portion 12a and the outer peripheral portion 12b are electrically independent with the gap 12c interposed therebetween, and the center of the underlying conductor layer 13 (13a and 13b) is formed on the insulating substrate 11. Forming a first lead wire 16a for plating from at least the portion 13a corresponding to the central portion 12a to the outer edge of the insulating substrate 11 among the portions 13a and 13b corresponding to the portion 12a and the outer peripheral portion 12b, and corresponding to the outer peripheral portion 12b And forming a second lead wire 16b for plating from only the portion 13b to the outer edge of the insulating substrate 11, the central portion 12a of the region in contact with the protruding electrode 23 is the outer peripheral portion 12b. Lower and central The method of manufacturing a semiconductor element mounting board 19 having an electrode pad 12 a gap 12c is provided annularly between the 12a and the outer peripheral portion 12b, can be more easily and highly productive manufacturing method.

すなわち、隙間12cを挟んで電気的に独立し、電極パッド12の中央部12aおよび外周部12bに対応する部分が隙間12cを挟んで電気的に独立するように形成された下地導体層13(13a,13b)は、図5(b)および(c)に示すように、中央部12aに対応する部分および外周部12bに対応する部分13a,13bのそれぞれに、別個に電解めっき法によりめっき層14(14a,14b)を被着させることができる。また、中央部12aに対応する部分を含む下地導体層13(13a,13b)の全体には、第1のめっき用引き出し線16aを介してめっき用の電流を供給し、少なくとも中央部12aに対応する部分13aに所定の厚さでめっき層14aを被着させることができる。そして、下地導体層13(13a,13b)のうち外周部12bに対応する部分13bのみに、第2のめっき用引き出し線16bを介して、より厚くめっき層14bを被着させることができる。そのため、外周部12bを中央部12aよりも高く(めっき層14bを厚く)することが容易である。なお、図5(a)〜(c)は、図1に示す半導体素子実装用基板19の製造方法の実施の形態の他の例について工程順に要部を拡大して示す断面図である。図5において図1と同様の部位には同様の符号を付している。図5では、下地導体層13(13a,13b)のうち中央部に対応する部分13aに先にめっき層14aを被着させる例を示しているが、外周部に対応する部分13bに先にめっき層14bを被着させてもよい。   That is, the underlying conductor layer 13 (13a) is formed such that the gap 12c is electrically independent and the portions corresponding to the central portion 12a and the outer peripheral portion 12b of the electrode pad 12 are electrically independent across the gap 12c. , 13b), as shown in FIGS. 5 (b) and 5 (c), a plating layer 14 is separately formed on the portion corresponding to the central portion 12a and the portions 13a, 13b corresponding to the outer peripheral portion 12b by electrolytic plating. (14a, 14b) can be deposited. In addition, the entire base conductor layer 13 (13a, 13b) including the portion corresponding to the central portion 12a is supplied with a plating current via the first plating lead wire 16a, and corresponds to at least the central portion 12a. The plating layer 14a can be applied to the portion 13a to be formed with a predetermined thickness. Then, a thicker plating layer 14b can be applied only to the portion 13b corresponding to the outer peripheral portion 12b of the underlying conductor layer 13 (13a, 13b) via the second lead wire 16b for plating. Therefore, it is easy to make the outer peripheral part 12b higher than the central part 12a (thickening the plating layer 14b). 5 (a) to 5 (c) are cross-sectional views showing enlarged main portions in order of processes in another example of the embodiment of the method for manufacturing the semiconductor element mounting substrate 19 shown in FIG. 5, parts similar to those in FIG. 1 are denoted by the same reference numerals. FIG. 5 shows an example in which the plating layer 14a is first deposited on the portion 13a corresponding to the center portion of the underlying conductor layer 13 (13a, 13b), but the plating is first applied to the portion 13b corresponding to the outer peripheral portion. Layer 14b may be deposited.

第1および第2のめっき用引き出し線16a,16bは、前述した下地導体層13(13a,13b)と同様の材料を用い、同様の方法で形成することができる。また、絶縁基板11に配線導体を形成する場合であれば、配線導体と同時に(例えば同じスクリーン印刷用の版面を用いて)形成して、半導体素子実装用基板19の生産性を良好に確保するようにしてもよい。   The first and second lead wires 16a and 16b for plating can be formed by the same method using the same material as the above-described base conductor layer 13 (13a and 13b). In the case where a wiring conductor is formed on the insulating substrate 11, it is formed simultaneously with the wiring conductor (for example, using the same screen printing plate) to ensure good productivity of the semiconductor element mounting substrate 19. You may do it.

この場合にも、マスキング等の工程が不要であり、例えば、めっき用の電流を供給するためのめっき用の治具の端子を、異なる引き出し線に接続するだけで、めっき層14(14a,14b)が被着される部分(中央部12aや外周部12bに対応する部分)を選択することができる。従って、この製造方法の場合には、電極パッド12のうち、より高い、つまりめっき層14bをより厚く被着させる必要のある外周部12bに対応する部分13bのみに電流を供給することができるため、突起電極23が当接する領域の中央部12aが外周部12bよりも低い電極パッド12の形成が容易である。   Also in this case, a process such as masking is not necessary. For example, the plating layer 14 (14a, 14b) can be obtained by simply connecting a terminal of a plating jig for supplying a plating current to a different lead wire. ) Can be selected (parts corresponding to the central part 12a and the outer peripheral part 12b). Therefore, in the case of this manufacturing method, current can be supplied only to the portion 13b corresponding to the outer peripheral portion 12b that is higher in the electrode pad 12, that is, the plating layer 14b needs to be deposited thicker. Thus, it is easy to form the electrode pad 12 in which the central portion 12a of the region where the protruding electrode 23 abuts is lower than the outer peripheral portion 12b.

この方法で半導体素子実装用基板19を製作した場合にも、電極パッド12の中央部12aと外周部12bとが電気的に独立するため、いずれか一方が突起電極23(電極端子22)を外部の電気回路に電気的に接続する導電路として機能し、他方が接合の強度を補強する補強用のパッドとして機能するものとすることができる。   Even when the semiconductor element mounting substrate 19 is manufactured by this method, since the central portion 12a and the outer peripheral portion 12b of the electrode pad 12 are electrically independent, one of them has the protruding electrode 23 (electrode terminal 22) externally. It is possible to function as a conductive path that is electrically connected to the electrical circuit, and the other functions as a reinforcing pad that reinforces the strength of the joint.

なお、この製造方法の場合に、めっき層14(14a,14b)を被着させた後、第1および第2の引き出し線16a,16bの露出部分を、絶縁基板11の表面から研磨等の方法で除去する工程を追加するようにしてもよい。   In the case of this manufacturing method, after the plating layer 14 (14a, 14b) is deposited, the exposed portions of the first and second lead lines 16a, 16b are polished from the surface of the insulating substrate 11 or the like. It is also possible to add a process to be removed by.

また、このような半導体素子実装用基板19を、半導体素子実装用基板19となる基板領域が複数縦横の並びに配列された四角板状の多数個取り基板(図示せず)の形態で製作するようにしておいて、多数個取り基板の外周の異なる辺にそれぞれ第1および第2のめっき用引き出し線(図示せず)を、第1は第1で、第2は第2で、それぞれまとめて引き出して形成するようにしてもよい。   Further, such a semiconductor element mounting substrate 19 is manufactured in the form of a square plate-like multi-piece substrate (not shown) in which a plurality of substrate regions to be the semiconductor element mounting substrate 19 are arranged vertically and horizontally. The first and second lead wires for plating (not shown) are respectively arranged on different sides of the outer periphery of the multi-chip substrate, the first being the first and the second being the second, respectively. It may be formed by drawing.

その際には、四角形状の多数個取り基板の4辺のうち対向し合う2辺ずつに、第1および第2のめっき用引き出し線をそれぞれ引き出して形成するようにしてもよい。この場合には、めっき用の治具(いわゆるラック)の導通ピンで多数個取り基板の対向する2辺を上下から挟んで多数個取り基板を保持するとともに、所定の第1または第2のめっき用引き出し線を選択して外部の電源と容易かつ確実に、例えば人為的な間違った導通等の不具合の発生を低減させて、導通させることができる。そのため、めっき工程の作業性の向上が可能で、さらに生産性に優れた製造方法とすることができる。   In this case, the first and second lead lines for plating may be formed by being drawn out on each of two opposing sides of the four sides of the quadrangular multi-piece substrate. In this case, the multi-cavity substrate is held by sandwiching two opposing sides of the multi-cavity substrate from above and below with a conduction pin of a plating jig (so-called rack), and the predetermined first or second plating is performed. It is possible to select a lead-out line for electrical connection with an external power source easily and reliably, for example, by reducing the occurrence of problems such as artificially incorrect conduction. Therefore, the workability of the plating process can be improved, and the manufacturing method can be further improved in productivity.

なお、電極パッド12を、中央部12aと外周部12bとが隙間12cを挟んで分割されている(隙間12cが絶縁基板11の上面まで達している)とともに、その中央部12aと外周部12bとが隙間12cを挟んで電気的に独立しているようにした製造方法を採用したときには、電極パッド12は、例えば前述した配線導体との電気的な接続が中央部12aのみで行なわれているものとして形成してもよい。この場合には、電極パッド12のうち突起電極23(電極端子22)を外部の電気回路に接続するための導電路として機能するのは中央部12aのみであり、外周部12bは突起電極23と電極パッド12との接合を前述のように補強するものとして機能する。   The electrode pad 12 is divided into a central portion 12a and an outer peripheral portion 12b across a gap 12c (the gap 12c reaches the upper surface of the insulating substrate 11), and the central portion 12a and the outer peripheral portion 12b When the manufacturing method is adopted such that the electrode pad 12 is electrically independent with the gap 12c interposed therebetween, the electrode pad 12 is, for example, electrically connected to the above-described wiring conductor only at the central portion 12a. You may form as. In this case, only the central portion 12a functions as a conductive path for connecting the protruding electrode 23 (electrode terminal 22) of the electrode pad 12 to an external electric circuit, and the outer peripheral portion 12b is connected to the protruding electrode 23. It functions to reinforce the bonding with the electrode pad 12 as described above.

酸化アルミニウム質焼結体により絶縁基板を作製し、その表面に、外形が直径200μmの円形状の電極パッドを、タングステンのメタライズ層およびニッケル/金めっき層を順次被着させることにより形成して、半導体素子実装用基板を作製した。この半導体素子実装用基板を用いて、超音波ボンディングによる半導体素子の実装信頼性を試験した。また、比較例として、同様の絶縁基板に、同様の外形で突起電極が接合される面が平坦な電極パッドを形成してなる従来技術の半導体素子実装用基板を準備した。   An insulating substrate is made of an aluminum oxide sintered body, and a circular electrode pad having an outer diameter of 200 μm is formed on the surface thereof by sequentially depositing a tungsten metallization layer and a nickel / gold plating layer, A substrate for mounting a semiconductor element was produced. Using this semiconductor element mounting substrate, the mounting reliability of the semiconductor element by ultrasonic bonding was tested. Further, as a comparative example, a conventional semiconductor element mounting substrate was prepared in which an electrode pad having a similar outer shape and a flat surface on which a protruding electrode is bonded is formed on a similar insulating substrate.

絶縁基板は、酸化アルミニウムを主原料とし、酸化ケイ素,酸化マグネシウム,酸化カルシウムを添加して作製した原料粉末を有機溶剤,有機バインダとともに混練した後、ドクターブレード法によりシート状に成形して複数のセラミックグリーンシートを作製し、このセラミックグリーンシートを積層した後1600℃で焼成することにより作製した。   The insulating substrate is made of aluminum oxide as a main raw material, and a raw material powder prepared by adding silicon oxide, magnesium oxide and calcium oxide is kneaded with an organic solvent and an organic binder, and then molded into a sheet shape by a doctor blade method. A ceramic green sheet was prepared, and this ceramic green sheet was laminated and then fired at 1600 ° C.

絶縁基板は、1辺の長さが25mmの正方形の板状で、厚さを2mmとして作製し、上面の中央部の、1辺の長さが15mmの正方形状の範囲を半導体素子の実装部として、ここに電極パッドを形成した。   The insulating substrate is a square plate with a side length of 25 mm and a thickness of 2 mm. The square area with a side length of 15 mm in the center of the upper surface is the mounting area of the semiconductor element. The electrode pad was formed here.

電極パッドは、中央部が直径40μmの円形状で、その外側に幅40μmの隙間を有し、その隙間の外側が外周部として半導体素子の突起電極に当接されるものとして形成した。隙間は幅50μmの円環状で形成し、個々の電極パッド全体の外形は、1辺の長さが200μm(0.2mm)の正方形状とした。隙間は、絶縁基板の上面に達するように形成して、中央部と外周部とを電気的に独立させて形成した。   The electrode pad was formed to have a circular shape with a diameter of 40 μm at the center, a gap with a width of 40 μm on the outside, and the outside of the gap as an outer peripheral part in contact with the protruding electrode of the semiconductor element. The gap was formed in an annular shape having a width of 50 μm, and the entire outer shape of each electrode pad was a square shape having a side length of 200 μm (0.2 mm). The gap was formed so as to reach the upper surface of the insulating substrate, and the central portion and the outer peripheral portion were made electrically independent.

各電極パッドは、中央部の高さを約15μmとし、外周部の高さを約35μmとした。このうち中央部は、厚さが約10μmのタングステンのメタライズ層の表面に、厚さが約4μmのニッケルめっき層と、厚さが約1μmの金めっき層とを順次被着させて形成した。また、外周部は、厚さが約10μmのタングステンのメタライズ層の表面に、厚さが約24μmのニッケルめっき層と、厚さが約1μmの金めっき層とを順次被着させて形成した。外周部のニッケルめっき層は、めっき層内の応力を緩和するために2層(厚さ4μmの1次めっき層と厚さ20μmの2次めっき層)に分けて被着させた。   Each electrode pad had a central part height of about 15 μm and an outer peripheral part height of about 35 μm. The central portion was formed by sequentially depositing a nickel plating layer having a thickness of about 4 μm and a gold plating layer having a thickness of about 1 μm on the surface of a tungsten metallization layer having a thickness of about 10 μm. The outer peripheral portion was formed by sequentially depositing a nickel plating layer having a thickness of about 24 μm and a gold plating layer having a thickness of about 1 μm on the surface of a tungsten metallization layer having a thickness of about 10 μm. The nickel plating layer at the outer peripheral portion was deposited in two layers (a primary plating layer having a thickness of 4 μm and a secondary plating layer having a thickness of 20 μm) in order to relieve stress in the plating layer.

なお、タングステンのメタライズ層は、タングステンの金属ペーストをスクリーン印刷法でセラミックグリーンシートの表面に印刷し、絶縁基板との同時焼成により形成した。また、ニッケルめっき層はワット浴を用いた電解めっき法により形成し、金めっき層はシアン系の金めっき浴を用いた電解めっき法により形成した。   The tungsten metallized layer was formed by printing tungsten metal paste on the surface of the ceramic green sheet by screen printing and co-firing with an insulating substrate. The nickel plating layer was formed by an electrolytic plating method using a watt bath, and the gold plating layer was formed by an electrolytic plating method using a cyan-based gold plating bath.

それぞれの実装部には、16×16個の並びで256個の電極パッドを形成した。   In each mounting part, 256 electrode pads were formed in a 16 × 16 array.

実装信頼性は、突起電極と電極パッドとを超音波ボンディングした後、温度サイクル試験(−40〜+120℃、1000サイクル)を施して接合部分に熱応力を繰り返し加えた後、接合部分の剥がれを外観で確認することにより行なった。試料数は、半導体素子実装用基板10個(電極パッドの数は256×10=2560個)とした。   The mounting reliability is determined by ultrasonic bonding the bump electrode and electrode pad, and then applying a thermal cycle test (−40 to + 120 ° C, 1000 cycles) to repeatedly apply thermal stress to the bonded portion, and then peeling the bonded portion. This was done by checking the appearance. The number of samples was 10 semiconductor device mounting substrates (the number of electrode pads was 256 × 10 = 2560).

なお、比較例として、上記のように隙間の無い1辺の長さが200μm(0.2mm)の正方形状の電極パッドを形成した半導体素子実装用基板を作製し、試験数は本発明の半導体素子実装用基板と同じにして試験を行なった。   As a comparative example, a semiconductor element mounting substrate on which a square electrode pad having a side length of 200 μm (0.2 mm) with no gap was formed as described above was manufactured. The test was performed in the same manner as the mounting substrate.

その結果、本発明の半導体素子実装用基板では、突起電極と電極パッドとの間に剥がれが発生せず、接続状態に異常が見られなかったのに対し、比較例においては、約5%の電極パッドで突起電極の電極パッドからの剥がれが見られた。これにより、本発明の半導体素子実装用基板および半導体装置は、突起電極と電極パッドとの接続強度および実装信頼性が高いことが確認できた。   As a result, in the semiconductor element mounting substrate of the present invention, no peeling occurred between the protruding electrode and the electrode pad, and no abnormality was found in the connection state, whereas in the comparative example, about 5% The protruding electrode peeled off from the electrode pad. Thus, it was confirmed that the semiconductor element mounting substrate and the semiconductor device of the present invention have high connection strength and mounting reliability between the protruding electrode and the electrode pad.

(a)は本発明の半導体素子実装用基板の実施の形態の一例を示す平面図であり、(b)は本発明の半導体素子実装用基板および半導体装置の実施の形態の一例を示す断面図である。(A) is a top view which shows an example of embodiment of the board | substrate for semiconductor element mounting of this invention, (b) is sectional drawing which shows an example of embodiment of the board | substrate for semiconductor element mounting of this invention, and a semiconductor device It is. (a)および(b)は、それぞれ本発明の半導体素子実装用基板の製造方法の実施の形態の一例を工程順に示す断面図である。(A) And (b) is sectional drawing which shows an example of embodiment of the manufacturing method of the board | substrate for a semiconductor element mounting of this invention in order of a process, respectively. (a)〜(c)は、それぞれ本発明の半導体素子実装用基板の製造方法の実施の形態の他の例を工程順に示す要部拡大断面図である。(A)-(c) is the principal part expanded sectional view which shows the other example of embodiment of the manufacturing method of the board | substrate for semiconductor element mounting of this invention in order of a process, respectively. (a)〜(c)は、それぞれ本発明の半導体素子実装用基板の製造方法の実施の形態の他の例を工程順に示す要部拡大断面図である。(A)-(c) is the principal part expanded sectional view which shows the other example of embodiment of the manufacturing method of the board | substrate for semiconductor element mounting of this invention in order of a process, respectively. (a)〜(c)は、それぞれ本発明の半導体素子実装用基板の製造方法の実施の形態の他の例を工程順に示す要部拡大断面図である。(A)-(c) is the principal part expanded sectional view which shows the other example of embodiment of the manufacturing method of the board | substrate for semiconductor element mounting of this invention in order of a process, respectively.

符号の説明Explanation of symbols

11・・・・・・絶縁基板
11a・・・・・実装部
12・・・・・・電極パッド
12a・・・・・中央部
12b・・・・・外周部
12c・・・・・隙間
13・・・・・・下地導体層
13a・・・・・下地導体層のうち中央部に対応する部分
13b・・・・・下地導体層のうち外周部に対応する部分
14・・・・・・めっき層
14a・・・・・中央部のめっき層
14b・・・・・外周部のめっき層
15・・・・・・めっき用引き出し線
16a・・・・・第1のめっき用引き出し線
16b・・・・・第2のめっき用引き出し線
19・・・・・・半導体素子実装用基板
21・・・・・・半導体素子
22・・・・・・電極端子
23・・・・・・突起電極
30・・・・・・半導体装置
11 ・ ・ ・ ・ ・ ・ Insulating substrate
11a ・ ・ ・ ・ ・ Mounting part
12 ・ ・ ・ ・ ・ ・ Electrode pads
12a: Central part
12b ... outer periphery
12c: Clearance
13 ・ ・ ・ ・ ・ ・ Base conductor layer
13a: The portion corresponding to the center of the underlying conductor layer
13b: The portion corresponding to the outer periphery of the underlying conductor layer
14 ・ ・ ・ ・ ・ ・ Plating layer
14a: Plated layer in the center
14b: plating layer on the outer periphery
15 ····· Plating lead wire
16a: First lead wire for plating
16b: Second lead wire for plating
19 ・ ・ ・ ・ ・ ・ Semiconductor element mounting board
21 ・ ・ ・ ・ ・ ・ Semiconductor elements
22 ・ ・ ・ ・ ・ ・ Electrode terminal
23 ・ ・ ・ ・ ・ ・ Projection electrode
30 ・ ・ ・ ・ ・ ・ Semiconductor device

Claims (9)

絶縁基板の上面に、下面に複数の電極端子が形成されて該電極端子に突起電極を備えた半導体素子を実装するための、前記電極端子とそれぞれ対向する複数の電極パッドが形成された実装部を有して成り、前記電極パッドに前記突起電極を当接させて前記半導体素子の上面から超音波を印加して前記突起電極を前記電極パッドに接合する半導体素子実装用基板であって、前記電極パッドは、前記突起電極が当接する領域の中央部が外周部よりも低く、かつ前記中央部と前記外周部との間に環状に隙間が設けられていることを特徴とする半導体素子実装用基板。 A mounting part in which a plurality of electrode pads are formed on the upper surface of the insulating substrate, each of which has a plurality of electrode terminals formed on the lower surface, and a plurality of electrode pads respectively facing the electrode terminals for mounting a semiconductor element having a protruding electrode on the electrode terminal. A substrate for mounting a semiconductor element, wherein the protruding electrode is brought into contact with the electrode pad and ultrasonic waves are applied from the upper surface of the semiconductor element to bond the protruding electrode to the electrode pad, The electrode pad is for mounting a semiconductor element, wherein a central portion of a region where the protruding electrode contacts is lower than an outer peripheral portion, and an annular gap is provided between the central portion and the outer peripheral portion. substrate. 前記隙間は、前記超音波による前記突起電極の左右方向の振動と交差する側が他の部位よりも広いことを特徴とする請求項1記載の半導体素子実装用基板。 2. The substrate for mounting a semiconductor element according to claim 1, wherein the gap is wider on the side intersecting with the left-right vibration of the protruding electrode due to the ultrasonic wave than other portions. 前記電極パッドは、下地導体層の上に前記中央部と前記外周部とで厚みの異なるめっき層が被着されていることを特徴とする請求項1記載の半導体素子実装用基板。 2. The semiconductor element mounting substrate according to claim 1, wherein the electrode pad is provided with a plating layer having a thickness different between the central portion and the outer peripheral portion on a base conductor layer. 絶縁基板の上面に、下面に複数の電極端子が形成されて該電極端子に突起電極を備えた半導体素子を実装するための、前記突起電極がそれぞれ当接されるとともに前記半導体素子の上面から超音波が印加されて接合される複数の電極パッドとなる下地導体層を形成する工程と、
前記下地導体層の表面に、前記突起電極が当接する領域の中央部が外周部よりも低くなるとともに、前記中央部と前記外周部との間に環状の隙間が設けられるように、前記突起電極が当接するめっき層を被着させて前記電極パッドを形成する工程と
を備えることを特徴とする半導体素子実装用基板の製造方法。
A plurality of electrode terminals are formed on the upper surface of the insulating substrate, and the protruding electrodes are mounted on the electrode terminals so as to be mounted on the electrode terminals. Forming a base conductor layer to be a plurality of electrode pads to which sound waves are applied and bonded;
The projecting electrode is formed such that a central portion of a region where the projecting electrode is in contact with the surface of the base conductor layer is lower than an outer peripheral portion, and an annular gap is provided between the central portion and the outer peripheral portion. A method of manufacturing a substrate for mounting a semiconductor element, comprising: depositing a plating layer on which the electrode contacts, and forming the electrode pad.
前記めっき層を被着させて前記電極パッドを形成する工程の前に、
前記下地導体層を、前記中央部および前記外周部に対応する部分が前記隙間を挟んで電気的に独立するように形成するとともに、前記絶縁基板に、前記下地導体層の前記外周部に対応する部分のみから前記絶縁基板の外縁にかけてめっき用引き出し線を形成する工程を備えることを特徴とする請求項4記載の半導体素子実装用基板の製造方法。
Before the step of depositing the plating layer and forming the electrode pad,
The base conductor layer is formed such that portions corresponding to the central portion and the outer peripheral portion are electrically independent with the gap therebetween, and the insulating substrate corresponds to the outer peripheral portion of the base conductor layer. 5. The method of manufacturing a substrate for mounting a semiconductor element according to claim 4, further comprising a step of forming a lead wire for plating from only a portion to an outer edge of the insulating substrate.
前記めっき層を被着させて前記電極パッドを形成する工程の前に、
前記下地導体層を、前記中央部および前記外周部に対応する部分が前記隙間を挟んで電気的に独立するように形成するとともに、前記絶縁基板に、前記下地導体層の前記中央部および前記外周部に対応する部分のうち少なくとも前記中央部に対応する部分から前記絶縁基板の外縁にかけて第1のめっき用引き出し線を形成する工程と、
前記外周部に対応する部分のみから前記絶縁基板の外縁にかけて第2のめっき用引き出し線を形成する工程と
を備えることを特徴とする請求項4記載の半導体素子実装用基板の製造方法。
Before the step of depositing the plating layer and forming the electrode pad,
The base conductor layer is formed such that portions corresponding to the central portion and the outer peripheral portion are electrically independent with the gap therebetween, and the central portion and the outer periphery of the base conductive layer are formed on the insulating substrate. Forming a first lead wire for plating from at least a portion corresponding to the central portion of the portion corresponding to the portion to an outer edge of the insulating substrate;
5. The method of manufacturing a substrate for mounting a semiconductor element according to claim 4, further comprising: forming a second lead wire for plating from only a portion corresponding to the outer peripheral portion to an outer edge of the insulating substrate.
絶縁基板の上面に、下面に複数の電極端子が形成されて該電極端子に突起電極を備えた半導体素子を実装するための、前記電極端子とそれぞれ対向する複数の電極パッドが形成された実装部を有して成る半導体素子実装用基板と、下面に複数の電極端子が形成されて該電極端子に突起電極を備えるとともに、超音波ボンディングにより前記突起電極が前記電極パッドに接合されて前記実装部に実装された半導体素子とを備え、前記突起電極と前記電極パッドとの接合領域の中央部と外周部との間に環状の隙間を有していることを特徴とする半導体装置。 A mounting part in which a plurality of electrode pads are formed on the upper surface of the insulating substrate, each of which has a plurality of electrode terminals formed on the lower surface, and a plurality of electrode pads respectively facing the electrode terminals for mounting a semiconductor element having a protruding electrode on the electrode terminal. A plurality of electrode terminals formed on the lower surface and provided with protruding electrodes, and the protruding electrodes are bonded to the electrode pads by ultrasonic bonding. And a semiconductor element, wherein an annular gap is provided between a central portion and an outer peripheral portion of a bonding region between the protruding electrode and the electrode pad. 前記環状の隙間は、前記超音波ボンディングの際に印加された超音波による前記突起電極の左右方向の振動と交差する側が他の部位よりも広いことを特徴とする請求項7記載の半導体装置。 8. The semiconductor device according to claim 7, wherein the annular gap has a wider side intersecting with the left-right vibration of the protruding electrode due to the ultrasonic wave applied during the ultrasonic bonding. 前記電極パッドは、下地導体層の上に前記中央部と前記外周部とで厚みの異なるめっき層が、前記中央部が前記外周部に比べて低くなるように被着されていることを特徴とする請求項7記載の半導体装置。 The electrode pad is characterized in that a plating layer having a thickness different between the central portion and the outer peripheral portion is deposited on a base conductor layer so that the central portion is lower than the outer peripheral portion. The semiconductor device according to claim 7.
JP2007302458A 2007-01-29 2007-11-22 Substrate for packaging semiconductor element, its manufacturing method and semiconductor device Pending JP2008211170A (en)

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Publication number Priority date Publication date Assignee Title
JP2020161515A (en) * 2019-03-25 2020-10-01 セイコーエプソン株式会社 Photoelectric conversion module, electronic timepiece, electronic apparatus and manufacturing method of photoelectric conversion module

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020161515A (en) * 2019-03-25 2020-10-01 セイコーエプソン株式会社 Photoelectric conversion module, electronic timepiece, electronic apparatus and manufacturing method of photoelectric conversion module

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