JP2008205337A - 樹脂封止型半導体装置 - Google Patents
樹脂封止型半導体装置 Download PDFInfo
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- JP2008205337A JP2008205337A JP2007041770A JP2007041770A JP2008205337A JP 2008205337 A JP2008205337 A JP 2008205337A JP 2007041770 A JP2007041770 A JP 2007041770A JP 2007041770 A JP2007041770 A JP 2007041770A JP 2008205337 A JP2008205337 A JP 2008205337A
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- die pad
- resin
- semiconductor device
- lead
- sealing layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- Lead Frames For Integrated Circuits (AREA)
Abstract
【解決手段】この樹脂封止型半導体装置は、半導体チップ2が固定されたダイパッド11と、ダイパッド11の上面11a側およびダイパッド11の下面11b側の両方から半導体チップを封止する樹脂封止層3と、半導体チップ2と電気的に接続され、インナーリード部12bが樹脂封止層3によって覆われている複数のリード端子12とを備えている。また、ダイパッド11には、リード端子12方向(矢印X方向)に延びるとともに、平面的に見て、リード端子12のインナーリード12b間に配置される放熱片14が形成されている。
【選択図】図1
Description
2 半導体チップ
3 樹脂封止層
4 ボンディングワイヤ
5 接着層
6 はんだ層
7 接着テープ(固定部材)
11、111 ダイパッド
12 リード端子
12a アウターリード部
12b インナーリード部(一方端部)
13 吊りリード
14、114 放熱片
15 ダム部材
16 位置決め孔
31 上部領域
32 下部領域
40 実装基板
Claims (5)
- 半導体チップが固定されたダイパッドと、
前記ダイパッドの一方主面側および前記ダイパッドの他方主面側の両方から前記半導体チップを封止する樹脂封止層と、
前記半導体チップと電気的に接続され、一方端部が前記樹脂封止層によって覆われている複数のリード端子とを備え、
前記ダイパッドには、前記リード端子方向に延びるとともに、平面的に見て、前記リード端子間に配置される放熱片が形成されていることを特徴とする、樹脂封止型半導体装置。 - 前記放熱片は、前記ダイパッドに複数形成されていることを特徴とする、請求項1に記載の樹脂封止型半導体装置。
- 前記放熱片は、平面的に見て、前記リード端子と交互に配置されていることを特徴とする、請求項2に記載の樹脂封止型半導体装置。
- 前記ダイパッドの主面に対して垂直な方向において、
前記ダイパッドと前記リード端子の一方端部とが同じ位置になるように構成されていることを特徴とする、請求項1〜3のいずれか1項に記載の樹脂封止型半導体装置。 - 前記放熱片の配置位置を固定するための固定部材をさらに備えることを特徴とする、請求項1〜4のいずれか1項に記載の樹脂封止型半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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JP2007041770A JP4994883B2 (ja) | 2007-02-22 | 2007-02-22 | 樹脂封止型半導体装置 |
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JP2007041770A JP4994883B2 (ja) | 2007-02-22 | 2007-02-22 | 樹脂封止型半導体装置 |
Publications (2)
Publication Number | Publication Date |
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JP2008205337A true JP2008205337A (ja) | 2008-09-04 |
JP4994883B2 JP4994883B2 (ja) | 2012-08-08 |
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JP2007041770A Active JP4994883B2 (ja) | 2007-02-22 | 2007-02-22 | 樹脂封止型半導体装置 |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012060105A (ja) * | 2010-08-09 | 2012-03-22 | Renesas Electronics Corp | 半導体装置、半導体装置の製造方法、金型、および封止装置 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS53135574A (en) * | 1977-05-02 | 1978-11-27 | Hitachi Ltd | Lead frame |
JPS63174347A (ja) * | 1987-01-13 | 1988-07-18 | Shinko Electric Ind Co Ltd | リ−ドフレ−ム |
JPH0425060A (ja) * | 1990-05-16 | 1992-01-28 | Nec Yamagata Ltd | 半導体装置 |
JPH05243478A (ja) * | 1992-02-28 | 1993-09-21 | Nec Kyushu Ltd | 樹脂封止形半導体装置用リードフレーム |
JP2006191143A (ja) * | 2006-03-13 | 2006-07-20 | Matsushita Electric Ind Co Ltd | 半導体装置 |
-
2007
- 2007-02-22 JP JP2007041770A patent/JP4994883B2/ja active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS53135574A (en) * | 1977-05-02 | 1978-11-27 | Hitachi Ltd | Lead frame |
JPS63174347A (ja) * | 1987-01-13 | 1988-07-18 | Shinko Electric Ind Co Ltd | リ−ドフレ−ム |
JPH0425060A (ja) * | 1990-05-16 | 1992-01-28 | Nec Yamagata Ltd | 半導体装置 |
JPH05243478A (ja) * | 1992-02-28 | 1993-09-21 | Nec Kyushu Ltd | 樹脂封止形半導体装置用リードフレーム |
JP2006191143A (ja) * | 2006-03-13 | 2006-07-20 | Matsushita Electric Ind Co Ltd | 半導体装置 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012060105A (ja) * | 2010-08-09 | 2012-03-22 | Renesas Electronics Corp | 半導体装置、半導体装置の製造方法、金型、および封止装置 |
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