JP2008200536A - Game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a game machine which can execute a proper control processing in the case of abnormal operation by determining whether a means for generating random numbers operates normally or not. <P>SOLUTION: An oscillator 930 generates a clock signal with a prescribed frequency and a counter IC 931 counts the random numbers used for control pertaining to games in a CPU 56 for game control from the clock signal. A monitoring circuit 934 monitors the generation of abnormality in the oscillator 930. The monitoring circuit 934 outputs an abnormality signal for informing the CPU 56 of abnormality pertaining to the update of the random numbers from the result of the monitoring. The CPU 56 executes an error processing from the input of the abnormality signal. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a gaming machine such as a pachinko gaming machine or a slot machine that allows a player to play a predetermined game and give a predetermined gaming value to the player in accordance with the establishment of a specific condition.

  As a gaming machine, a game medium such as a game ball is launched into a game area by a launching device, and when a game medium wins a prize area such as a prize opening provided in the game area, a predetermined number of prize balls are paid out to the player. There is something to be done. Further, a variable display device capable of changing the display state is provided, and is configured to give a predetermined game value to the player when the display result of the special symbol in the variable display device becomes a predetermined specific display mode There is something that was done. In the variable display device, the special symbol starts to fluctuate based on the winning of the game ball at the start winning opening (start winning prize).

  That the display result of the variable display device that displays the special symbol is a combination of a predetermined display mode is usually referred to as “big hit”. Note that the game value is the right that the state of the variable winning ball device provided in the gaming area of the gaming machine is advantageous for a player who is likely to win a ball, or the advantageous state for a player. It is to generate.

  When the big hit occurs, for example, the big winning opening is opened a predetermined number of times, and the game shifts to a big hit gaming state where the hit ball is easy to win. And in each open period, if there is a prize for a predetermined number (for example, 10) of the big prize opening, the big prize opening is closed. And the number of times the special winning opening is opened is fixed to a predetermined number (for example, 16 rounds). An opening time (for example, 29.5 seconds) is determined for each opening, and even if the number of winnings does not reach a predetermined number, the big winning opening is closed when the opening time elapses. Further, when a predetermined condition (for example, winning in the V zone provided in the big prize opening) is not established at the time when the big prize opening is closed, the big hit gaming state is ended.

  When a game ball wins a winning opening provided on the game board, a predetermined number of prize balls are paid out. Since the progress of the game is controlled by the game control means mounted on the main board, the number of prize balls based on the winning is determined by the game control means, and the payout control means for controlling the payout mechanism for paying out the game balls as prizes. Sent to. Hereinafter, the game control means and the other control means may be referred to as electrical component control means, respectively. An electrical component is a component (such as a mechanism component or a circuit) provided in a gaming machine and operates electrically.

  By the way, a “big hit” in a game satisfies a predetermined condition (for example, a start prize which is a variable display start condition), generates a random number used for the big hit determination, and the random value matches a predetermined value determined in advance. It happens when you do. The jackpot determination is performed based on the random number value in the game control microcomputer constituting the game control means, but the generation of the random number value is generated by an external random number generated in a hardware configuration provided outside the game control microcomputer. May be performed in the means.

  The external random number generator includes an oscillator that generates a clock signal having a predetermined frequency, a counter unit that counts the clock signal generated by the oscillator, and a latch unit that extracts and latches (holds) the counter value counted by the counter unit. I have. Specifically, the external random number generator generates a random value as follows. The counter unit counts a clock signal having a predetermined frequency generated by the oscillator. When detecting that a start winning has occurred, the latch unit extracts and latches the counter value counted by the counter unit.

  Further, when the game control microcomputer detects that a start winning has occurred, it reads the counter value latched by the latch unit. Then, the game control microcomputer stores the read counter value in a predetermined area of the RAM. The counter value stored in this way becomes a random value used for the jackpot determination. The game control microcomputer makes a jackpot determination based on a random number value stored in a predetermined area of the RAM.

  However, there is a possibility that an abnormality such as a failure may occur in the external random number generation means. For example, an oscillator may fail and no clock signal may be generated, or a counter unit may fail and no longer count the clock signal normally. In addition, the signal line connecting the start port switch and the latch unit may be disconnected, and the latch unit may not be able to detect the start detection signal from the start port switch. In such a case, the counter value held by the latch unit is always the same value, and if the counter value immediately before the external random number generator is abnormal is “missing”, the big hit determination is always “missed” and “big hit” "Will no longer appear. On the other hand, if it is a “hit” just before an abnormality occurs, it will always be a “hit”. Thus, even when the counter value from the external random number generation means is biased to cause inconvenience in game control, it cannot be easily recognized from the outside.

  As a conventional gaming machine that solves such problems, the monitoring unit monitors the abnormality of the clock signal generated by the oscillator of the external random number generation means, and stops the operation of the CPU (microcomputer) according to the monitoring result of the monitoring unit. There are some (for example, refer to Patent Document 1).

Japanese Patent Laid-Open No. 11-313966 (page 3-9, FIG. 3)

  However, the external random number generation means monitoring device described in Patent Document 1 can only detect an abnormality in an oscillator that generates a clock signal, and has other configurations such as a counter unit and a start port switch. It is not possible to detect an abnormality in the signal line connecting the latch portion and the latch portion. In addition, in current gaming machines where control is complicated, if there is an abnormality in the external random number generation means, if appropriate control processing such as notification of abnormality or stop of game ball payout is not performed, a new There is also a risk of inconvenience.

  The present invention has been made to solve the above-described problems, and determines whether or not the means for generating a random number is operating normally, and if it is operating abnormally, appropriate control processing is performed. It is an object of the present invention to provide a gaming machine that can execute the game.

  A gaming machine according to the present invention is a gaming machine that allows a player to play a predetermined game and give a predetermined game value to the player in accordance with establishment of a predetermined condition, and controls the progress of the game. A computer (for example, CPU 56), a clock signal generating means (oscillator 930) for generating a clock signal with a predetermined frequency (for example, a 20 MHz clock signal), and a game control microcomputer are provided separately, and based on the clock signal. A numerical data updating means (for example, counter IC 931) for updating numerical data (for example, a counter value, that is, a random value) used for control related to the game in the game control microcomputer, and whether or not the updating of the numerical data is stopped. Monitoring means (for example, monitoring circuits 934 and 935) for monitoring. The update abnormality signal is output to notify the microcomputer for game control that the update of numerical data is stopped (for example, failure of the transmitter 930 or the counter 932) when the update of the game is stopped. The control microcomputer executes a predetermined abnormality control process (for example, the process shown in step S33 of FIG. 11 and the process of FIG. 17) based on the input of the update abnormality signal.

  A notification means (for example, a variable display device 9, a speaker 27, a light emitter such as a lamp / LED) is provided for notifying the update abnormality, and the game control microcomputer performs numerical data on the notification means as a predetermined abnormality control process. It is preferable to perform a process (for example, the process shown in step S323 of FIG. 17) for notifying that an update abnormality has occurred that the update of the update has stopped.

  The game control microcomputer is preferably configured to perform a process for stopping the control relating to the game (for example, the process shown in steps S324 to S326 in FIG. 17) as the predetermined abnormality control process.

  The game control microcomputer is preferably configured to perform a process for stopping control related to the provision of a game value related to a game in the abnormality control process.

  The monitoring unit (for example, the monitoring circuit 934) monitors whether or not the updating of the numerical data is stopped by determining whether or not the clock signal from the clock signal generating unit is input to the numerical data updating unit. It may be configured.

  The monitoring means (for example, the monitoring circuit 935) includes numerical data storage means (for example, a storage unit 935B) that stores numerical data updated by the numerical data updating means at a predetermined time point, and numerical data stored this time is stored as numerical data. Numerical data determination means (for example, an abnormality determination circuit 935C) for determining whether or not the numerical data stored in the means (for example, one or a plurality of numerical data stored at an arbitrary number of times) matches. In addition, an update abnormality signal may be output to the game control microcomputer when it is determined by the numerical data determination means that the numerical data is consistent with the predetermined number of times.

  The monitoring means may be configured to determine whether or not the numerical data stored this time matches the numerical data stored last time.

  The monitoring means may be configured to determine whether or not the numerical data stored this time matches the numerical data stored last time and the last time.

  When the monitoring means determines that the numerical data stored this time matches the numerical data stored last time, the numerical data stored this time is stored two times before (or even earlier). It may be configured to determine whether or not they match.

  It is preferable that the numerical data is used for determining whether or not a predetermined game value is given (for example, used for the random value of the jackpot determining random number).

  Variable display means (for example, a variable display device 9) that can change the display state is provided, and variable display of identification information is started based on establishment of a variable display execution condition (for example, occurrence of a start winning), and variable display of identification information An execution condition detecting means (for example, a start port switch 14a) for detecting the establishment of the variable display execution condition that can give a predetermined game value to the player when the display result becomes a specific display result. And the numerical data updating means is configured to output numerical data at the time when the execution condition of the variable display is satisfied based on the execution condition detection means detecting that the execution condition of the variable display is satisfied. It is preferable.

  According to the first aspect of the present invention, the game control microcomputer for controlling the progress of the game, the clock signal generating means for generating the clock signal of the predetermined frequency, and the game control microcomputer are provided separately, and the clock Based on the signal, it is provided with numerical data updating means for updating numerical data used for control related to the game in the game control microcomputer, and monitoring means for monitoring whether or not the updating of the numerical data is stopped. The means outputs an update abnormality signal notifying the updating abnormality that the updating of the numerical data is stopped to the gaming control microcomputer when the updating of the numerical data is stopped. Since the predetermined abnormal time control process is executed based on the input of the signal, the numerical data update means etc. Always determine whether it is operating, and if you have an abnormal operation can execute a suitable control action.

  According to the second aspect of the present invention, there is provided an informing means for informing the updating abnormality, and the gaming control microcomputer performs an updating abnormality in which the updating of the numerical data is stopped in the informing means as a predetermined abnormality time control process. Therefore, it is possible to easily recognize that an update abnormality has occurred.

  In the invention according to claim 3, since the game control microcomputer is configured to perform a process for stopping the control related to the game as the predetermined abnormality control process, when an update abnormality occurs It is possible to prevent a new problem from occurring due to the progress of the game.

  In the invention according to claim 4, the monitoring means monitors whether or not the updating of the numerical data is stopped by determining whether or not the clock signal from the clock signal generating means is input to the numerical data updating means. Thus, it is possible to reliably detect an update abnormality such as a failure of the clock signal generation means.

  In the invention according to claim 5, the monitoring means stores the numerical data updated by the numerical data updating means at a predetermined time point, and the numerical data stored this time is stored in the numerical data storage means. And a numerical data determination means for determining whether or not the numerical data matches the numerical data that has been updated. When the numerical data determination means determines that the numerical data is consistent with a predetermined number of times, an update abnormality signal is output. Since it is configured to output to the game control microcomputer, it is possible to reliably detect an update abnormality such as a failure of the numerical data update means.

  According to the sixth aspect of the present invention, the numerical data is used for determining whether or not a predetermined game value is given, so that the numerical data updating means of the hardware configuration is a numerical value of the software configuration executed by the game control computer. Unlike the data updating means, it does not synchronize with the control related to the game, so that it is less likely that an unauthorized player will recognize the timing at which the numerical value for giving the game value is generated.

Embodiment 1 FIG.
Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
First, the overall configuration of a pachinko gaming machine that is an example of a gaming machine will be described. FIG. 1 is a front view of a pachinko gaming machine as viewed from the front. FIG. 2 is a front view showing the front of the game board. In the following embodiments, a pachinko gaming machine will be described as an example. However, the gaming machine according to the present invention is not limited to a pachinko gaming machine, and can be applied to other gaming machines such as a slot machine.

  The pachinko gaming machine 1 includes an outer frame (not shown) formed in a vertically long rectangular shape and a game frame attached to the inside of the outer frame so as to be openable and closable. Further, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape that is provided in the game frame so as to be opened and closed. The game frame includes a front frame (not shown) installed to be openable and closable with respect to the outer frame, a mechanism plate to which mechanism parts and the like are attached, and various parts attached to them (excluding a game board described later). Is a structure including

  As shown in FIG. 1, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2 is a hitting ball supply tray (upper plate) 3. Under the hitting ball supply tray 3, an extra ball receiving tray 4 for storing game balls that cannot be accommodated in the hit ball supply tray 3 and a hitting operation handle (operation knob) 5 for launching the game balls are provided. A game board 6 is detachably attached to the back surface of the glass door frame 2. The game board 6 is a structure including a plate-like body constituting the game board 6 and various components attached to the plate-like body. A game area 7 is formed on the front surface of the game board 6.

  Near the center of the game area 7, there is provided a variable display device (special symbol display device) 9 including a plurality of variable display portions each variably displaying a symbol as identification information. The variable display device 9 has, for example, three variable display portions (symbol display areas) of “left”, “middle”, and “right”. In addition, the variable display device 9 is provided with four special symbol start memory display areas (start memory display areas) 18 for displaying the number of effective winning balls that have entered the start winning opening 14, that is, the start memory number. Each time there is a valid start prize, the display color changes (for example, changes from blue display to red display), and the start storage display area is increased by one. Each time the variable display of the variable display device 9 is started, the start memory number display area where the display color is changed is reduced by 1 (that is, the display color is returned to the original). In this example, since the symbol display area and the start memory display area are provided separately, the start memory number can be displayed even during variable display. The start memory display area may be provided in a part of the symbol display area. Further, the display of the start memory number may be interrupted during variable display. In this example, the start memory display area is provided in the variable display device 9. However, a display (special symbol start memory display) for displaying the start memory number may be provided separately from the variable display device 9. Good.

  Below the variable display device 9, a variable winning ball device 15 is provided as a start winning port 14. The winning ball that has entered the start winning opening 14 is guided to the back of the game board 6 and detected by the start opening switch 14a. A variable winning ball device 15 that opens and closes is provided below the start winning opening 14. The variable winning ball device 15 is opened by a solenoid 16.

  An open / close plate 20 that is opened by a solenoid 21 in a specific gaming state (big hit state) is provided below the variable winning ball device 15. The opening / closing plate 20 is a means for opening and closing the special winning opening. Of the winning balls guided from the opening / closing plate 20 to the back of the game board 6, the winning ball entering one (V winning area: special area) is detected by the V winning switch 22, and the winning ball from the opening / closing board 20 is counted. 23. On the back of the game board 6, a solenoid 21A for switching the route in the special winning opening is also provided.

  When a game ball wins the gate 32 and is detected by the gate switch 32a, the variable display of the normal symbol display 10 is started. In this embodiment, variable display is performed by alternately lighting the left and right lamps (a symbol can be visually recognized when the lamp is lit). For example, if the right lamp is lit when the variable display ends, it is a win. When the stop symbol on the normal symbol display 10 is a predetermined symbol (winning symbol), the variable winning ball device 15 is opened for a predetermined number of times. In the vicinity of the normal symbol display 10, a normal symbol start memory display 41 having a display unit with four LEDs for displaying the number of winning balls entered into the gate 32 is provided. Each time there is a prize at the gate 32, the normal symbol start memory display 41 increases the number of LEDs to be turned on by one. Then, every time variable display on the normal symbol display 10 is started, the number of LEDs to be lit is reduced by one.

  The gaming board 6 is provided with a plurality of winning holes 29, 30, 33, 39, and winning of the game balls to the winning holes 29, 30, 33 is detected by winning hole switches 29a, 30a, 33a, 39a, respectively. The Each winning opening 29, 30, 33, 39 constitutes a winning area provided in the game board 6 as an area for accepting game media and allowing winning. The start winning opening 14 and the big winning opening also constitute a winning area that accepts game media and allows winning. Decorative lamps 25 blinking and displayed during the game are provided around the left and right sides of the game area 7, and an outlet 26 for absorbing a game ball that has not won a prize is provided at the bottom. Two speakers 27 that emit sound effects are provided on the left and right upper portions outside the game area 7. On the outer periphery of the game area 7, a top frame lamp 28a, a left frame lamp 28b, and a right frame lamp 28c are provided. Further, a decoration LED is installed around each structure (such as a big prize opening) in the game area 7. The top frame lamp 28a, the left frame lamp 28b, the right frame lamp 28c, and the decoration LED are examples of a decorative light emitter provided in the gaming machine.

  In this example, a prize ball LED 51 that is turned on when there is a remaining number of prize balls is provided in the vicinity of the left frame lamp 28b, and a ball that is turned on when the supply ball is blown out in the vicinity of the top frame lamp 28a. An LED 52 is provided. As described above, the pachinko gaming machine 1 of this embodiment is provided with lamps and LEDs as light emitters in various places. Further, FIG. 1 also shows a prepaid card unit (hereinafter referred to as a card unit) 50 that is installed adjacent to the pachinko gaming machine 1 and allows a ball lending by inserting a prepaid card.

  The card unit 50 includes a use indicator lamp 151 that indicates whether or not the card unit 50 is in a usable state, a connection table direction indicator 153 that indicates which side of the pachinko gaming machine 1 corresponds to the card unit 50, a card A card insertion indicator lamp 154 indicating that a card is inserted into the unit 50, a card insertion slot 155 into which a card as a recording medium is inserted, and a card reader / writer mechanism provided on the back surface of the card insertion slot 155 A card unit lock 156 is provided for releasing the card unit 50 when checking the card.

  The game balls launched from the hit ball launching device enter the game area 7 through the hit ball rail, and then descend the game area 7. When the game ball enters the start winning port 14 and is detected by the start port switch 14a, the special symbol starts variable display (variation) on the variable display device 9 if the variable display of the symbol can be started. If the variable display of the symbol cannot be started, the start memory number is increased by one.

  The variable display of the special symbol on the variable display device 9 stops when a certain time has elapsed. If the combination of special symbols at the time of stoppage is a jackpot symbol (specific display result), the game shifts to a jackpot gaming state. That is, the opening / closing plate 20 is opened until a predetermined time elapses or a predetermined number (for example, 10) of game balls wins. When the game ball wins the V winning area while the opening / closing plate 20 is opened and is detected by the V winning switch 22, a continuation right is generated and the opening / closing plate 20 is opened again. The generation of the continuation right is allowed a predetermined number of times (for example, 15 rounds).

  When the combination of special symbols in the variable display device 9 at the time of stopping is a combination of jackpot symbols (probability variation symbols) with probability fluctuations, the probability of the next jackpot increases. That is, it becomes a more advantageous state for the player in the probability variation state.

  When the game ball wins the gate 32, the normal symbol display unit 10 is in a state where the normal symbol is variably displayed. Further, when the stop symbol on the normal symbol display 10 is a predetermined symbol (winning symbol), the variable winning ball device 15 is opened for a predetermined time. Further, in the probability variation state, the probability that the stop symbol in the normal symbol display 10 becomes a winning symbol is increased, and the opening time and the number of times of opening of the variable winning ball device 15 are increased. That is, the opening time and the number of times of opening of the variable winning ball device 15 can be increased when the stop symbol of the normal symbol is a winning symbol or the stop symbol of the special symbol is a probabilistic symbol. Change to an advantageous state. Note that increasing the number of times of opening is a concept including changing from a closed state to an open state.

  Next, the structure of the back surface of the pachinko gaming machine 1 will be described with reference to FIG. 3 and FIG. FIG. 3 is a rear view of the gaming machine as seen from the back side. FIG. 4 is a rear view of the mechanism plate to which various members are attached as viewed from the back side of the gaming machine.

  As shown in FIG. 3, on the back side of the gaming machine, a game in which a variable display control unit 49 including an effect control board 80 on which an effect control means for controlling the variable display device 9 is mounted, a game control microcomputer, and the like are mounted. A control board (main board) 31 is installed. In addition, a payout control board 37 on which a payout control microcomputer for performing ball payout control is mounted is installed. The production control means includes a variable display device 9 provided on the game board 6, various decoration LEDs, a normal symbol start memory display 41, a decoration lamp 25, a top frame lamp 28a provided on the frame side, and a left frame. The lamp 28b and the right frame lamp 28c are controlled to be turned on, and sound generation from the speaker 27 is controlled.

  The effect control means is realized by one effect control microcomputer mounted on the effect control board 80, but various decoration LEDs, normal symbol start memory display 41, and decoration lamp 25 provided on the game board 6. The drive circuit for driving the top frame lamp 28a, the left frame lamp 28b and the right frame lamp 28c provided on the frame side is mounted on a lamp driver board electrically connected to the effect control board 80. Yes. The drive circuit for driving the speaker 27 is mounted on a sound output board that is electrically connected to the effect control board 80.

  Further, a power supply substrate 910 and a touch sensor substrate 91 on which a power supply circuit for generating DC30V, DC21V, DC12V, and DC5V is mounted are provided. Most of the power supply substrate 910 overlaps with the main substrate 31, but there is an exposed portion that is exposed so as not to overlap with the main substrate 31. In the exposed portion, power supply to each electrical component control board (main board 31, production control board 80, payout control board 37) of the gaming machine 1 and each electrical component provided in the gaming machine is executed or cut off. For clearing the backup data stored in the power switch 914 as the power supply permission means and the storage content holding means included in the main board 31 (for example, the backup RAM capable of holding the contents even when the power supply is stopped). A clear switch 921 is provided as an operating means. Further, a replaceable fuse is provided inside the power switch 914 in the exposed portion (inside the substrate).

  On the back side of the gaming machine, a terminal board 160 provided with terminals for outputting various information to the outside of the gaming machine is installed above. The terminal board 160 includes at least a ball break terminal for introducing the output of the ball break detection switch 167 and outputting it externally, a prize ball terminal for outputting prize ball information (prize ball number signal) and a ball. A ball lending terminal for externally outputting lending information (ball lending number signal) is provided. In addition, an information terminal board (information output board) 34 provided with terminals for outputting various information from the main board 31 to the outside of the gaming machine is installed near the center.

  The game balls stored in the storage tank 38 pass through the guide rail 39 and, as shown in FIG. 4, reach the ball payout device covered with the payout case 40A via the curve rod 186. A ball break switch 187 as a game medium break detection means is provided on the upper part of the ball payout device. When the ball break switch 187 detects a ball break, the dispensing operation of the ball dispensing device stops. The ball break switch 187 is a switch for detecting the presence or absence of a game ball in the game ball passage, but the ball break detection switch 167 for detecting the shortage of supply balls in the storage tank 38 is also an upstream portion (storage tank 38). In the vicinity of the head). When the ball break detection switch 167 detects the shortage of game balls, the game machine is replenished to the game machine from the supply mechanism provided on the gaming machine installation island.

  A large number of game balls as prizes based on winning prizes and game balls based on ball lending requests are paid out and the hitting ball supply tray 3 becomes full, and finally game balls are paid out after the game balls reach the contact port 45. The game ball is guided to the surplus ball receiving tray 4 through the surplus ball passage 46. Further, when the game ball is paid out, the sensing lever 47 presses the full tank switch 48 as the storage state detection means, and the full tank switch 48 as the storage state detection means is turned on. In this state, the rotation of the payout motor in the ball payout device stops, the operation of the ball payout device stops, and the driving of the hitting ball launching device also stops.

  As shown in FIG. 4, a ball removal passage 191 is formed on the side of the ball payout device from the curve rod 186 to the discharge port 192 at the lower part of the gaming machine. A ball removal lever 193 is provided above the ball removal passage 191. When the ball removal lever 193 is operated by a game clerk or the like, a game ball passage from the guide rail 39 to the ball removal passage 191 is formed, and the storage tank 38 is provided. The game balls stored inside are discharged from the discharge port 192 to the outside of the gaming machine.

  FIG. 5 is a block diagram illustrating an example of a circuit configuration in the main board 31. FIG. 5 also shows the payout control board 37 and the effect control board 80. The main board 31 includes a basic circuit 53 for controlling the pachinko gaming machine 1 according to a program, a gate switch 32a, a start port switch 14a, a V winning switch 22, a count switch 23, winning port switches 29a, 30a, 33a, 39a, and Basically, a switch circuit 58 that gives a signal from the clear switch 921 to the basic circuit 53, a solenoid 16 that opens and closes the variable winning ball apparatus 15, a solenoid 21 that opens and closes the opening and closing plate 20, and a solenoid 21A that switches the path in the special winning opening. A solenoid circuit 59 that is driven in accordance with a command from the circuit 53 is mounted.

  The gate switch 32a, the start port switch 14a, the V winning switch 22, the count switch 23, the winning port switches 29a, 30a, 33a, 39a, and other switches may be referred to as sensors. That is, the name of the game medium detection means (game ball detection means in this example) that can detect a game ball is not limited. Each of the start port switch 14a, the count switch 23, and the winning port switches 29a, 30a, 33a, and 39a that perform winning detection is also a winning detection means. Note that the winning detection means may be configured to collectively detect the respective game balls that have won separately a plurality of winning openings. In addition, even if a passing gate such as the gate switch 32a is used, if a prize ball is to be paid out, a game ball entering the passing gate becomes a win, and a switch ( For example, the gate switch 32a) serves as a winning detection means. Furthermore, in this embodiment, a game ball won in the V winning area is detected by the V winning switch 22 and also detected by the count switch 23, but may be detected only by the V winning switch 22. When a game ball won in the V prize area is detected only by the V prize switch 22, the number of game balls won in the big prize opening is the sum of the number detected by the V prize switch 22 and the number detected by the count switch 23. become.

  Further, according to the data given from the basic circuit 53, the jackpot information indicating the occurrence of the jackpot, the effective starting information indicating the number of starting winning balls used for starting the variable display of the symbols in the variable display device 9, the probability variation has occurred. An information output circuit 64 for outputting an information output signal such as probability variation information indicating the above to an external device such as a hall computer is mounted.

  The basic circuit 53 includes a ROM 54 for storing a game control program and the like, a RAM 55 as a storage means (variation data storage means for storing fluctuation data) used as a work memory, a CPU 56 for performing control operations according to the program, and an I / O Port part 57 is included. In this embodiment, the ROM 54 and RAM 55 are built in the CPU 56. That is, the CPU 56 is a one-chip microcomputer. The one-chip microcomputer only needs to have at least the RAM 55 built in, and the ROM 54 and the I / O port unit 57 may be externally attached or built in. Since the CPU 56 executes control according to the program stored in the ROM 54, the CPU 56 executes (or performs processing) hereinafter, specifically, the CPU 56 executes control according to the program. is there. The same applies to CPUs mounted on substrates other than the main substrate 31.

  A RAM 55 (may be a CPU built-in RAM) 55 is a backup RAM that is partially or entirely backed up by a backup power source created in the power supply substrate 910. That is, even if the power supply to the gaming machine is stopped, a part or all of the contents of the RAM 55 is saved for a predetermined period. In particular, at least data corresponding to the game state, that is, the control state of the game control means and data indicating the number of unpaid prize balls are stored in the backup RAM. Note that the data according to the control state of the game control means is data necessary for restoring the control state before the occurrence of a power failure or the like based on the data when the power supply is restored after a power failure or the like. .

  The hitting ball launching device for hitting and launching the game ball includes a launch motor 94 controlled by a circuit on the payout control board 37, and the game ball is launched toward the game area 7 by the rotation of the launch motor 94. A drive signal for driving the firing motor 94 is transmitted to the firing motor 94 via the touch sensor substrate 91. The touch sensor detects that the player is touching the operation knob (hitting ball handle) 5, and a signal from the touch sensor is transmitted to the payout control board 37 via the touch sensor board 91. The circuit on the payout control board 37 stops the driving of the firing motor 94 when the signal from the touch sensor indicates an off state.

  In this embodiment, the effect control means mounted on the effect control board 80 performs display control of the normal symbol start memory display 41 and the decoration lamp 25 provided on the game board 6, and the frame side Display control of the top frame lamp 28a, the left frame lamp 28b, and the right frame lamp 28c. The effect control means mounted on the effect control board 80 also performs display control of the variable display device 9 that variably displays special symbols and the normal symbol display 10 that variably displays normal symbols.

  FIG. 6 is a block diagram showing components related to payout, such as the payout control board 37 and the ball payout device 97. As shown in FIG. 6, a payout control CPU 371 is mounted on the payout control board 37. In this embodiment, the payout control CPU 371 is a one-chip microcomputer and has at least a built-in RAM. Further, unlike the RAM 55 on the main board 31, the RAM is not backed up by a power source. The payout control CPU 371, the RAM, the ROM (not shown) storing the payout control program, the I / O port, etc. constitute payout control means.

  Detection signals from the full tank switch 48 and the payout count switch 301 are input to the I / O port 372 f of the payout control board 37 via the relay board 72. Detection signals from the ball break switch 187 and the payout motor position sensor 295 are input to the I / O port 372e of the payout control board 37 via the relay board 72. The payout control CPU 371 of the payout control board 37 performs a ball payout process when the detection signal from the ball shortage switch 187 indicates a ball full state or when the detection signal from the full tank switch 48 indicates a full tank state. Stop. Further, when the detection signal from the full tank switch 48 indicates a full tank state, the ball launching from the ball striking device is stopped.

  When there is a winning, from the output circuit 67 of the main board 31, as a payout command signal, a prize ball REQ signal (prize ball request signal) for making a prize ball payout request and a payout quantity signal indicating the number of prize balls to be paid out. Is output. The payout number signal is composed of 4-bit data (binary 4-digit data) and is output through four signal lines. The payout number signal is input to the I / O port 372e via the input circuit 373A. When a prize ball REQ signal and a payout number signal are input via the I / O port 372e, the payout control CPU 371 controls to drive the ball payout device 97 to pay out the number of game balls indicated by the payout number signal. . A power supply confirmation signal (connection confirmation signal) indicating that the main board 31 is connected is also output from the output circuit 67 of the main board 31. The prize ball REQ signal and the payout number signal correspond to a payout command signal for designating the payout number.

  Further, when the payout control means accepts a payout command signal, it sends a command acceptance signal to the main board 31. The command acceptance signal is transmitted to the main board 31 via the output port 372b of the payout control board 37 and the output circuit 373B. Then, in the main board 31, the data is input to the CPU 56 via the input circuit 68 and the I / O port 57. Further, when the payout control means is executing a prize ball payout process, the payout control means is a payout BUSY signal (a prize ball payout signal indicating that the payout process is in progress via the output port 372b and the output circuit 373B). ). In this embodiment, the command acceptance signal is transmitted when the payout BUSY signal is turned on.

  The payout control CPU 371 receives a prize ball information signal indicating the number of prize balls to be paid out and a ball lending number signal indicating the number of balls to be rented via the output port 372b as a terminal board (the frame external terminal board and the board external terminal board). Output) 160. A driver circuit is provided outside the output port 372b, but is not shown in FIG. Further, door opening information switches 161A and 161B are connected to the terminal board 160 (frame external terminal board).

  Also, the payout control CPU 371 outputs an error signal to the error display LED 374 using a 7-segment LED via the output port 372c. Further, a signal for instructing turning on / off is output to the winning ball LED 51 and the ball running out LED 52 via the output port 372b. A detection signal from an error release switch 375 for releasing the error state is input to the input port 372f of the payout control board 37. The error cancel switch 375 is used to cancel the error state by software reset.

  Further, a drive signal from the payout control board 37 to the payout motor 289 is transmitted to the payout motor 289 in the payout mechanism portion of the ball payout device 97 via the output port 372a and the relay board 72. Although a driver circuit (motor drive circuit) is installed outside the output port 372a, the description is omitted in FIG. The drive signal from the payout control board 37 to the firing motor 94 is transmitted to the firing motor 94 via the output port 372a and the touch sensor board 91.

  The card unit 50 is equipped with a card unit control microcomputer. In addition, the card unit 50 is provided with a usable display lamp 151, a connecting table direction indicator 153, a card insertion display lamp 154, and a card insertion slot 155 (see FIG. 1). A frequency display LED 60, a ball lending LED 61, a ball lending switch 62, and a return switch 63 provided in the vicinity of the hitting ball supply tray 3 are connected to the interface board (relay board) 66.

  A card lending switch signal indicating that the ball lending switch 62 has been operated and a return switch signal indicating that the return switch 63 has been operated are given to the card unit 50 from the interface board 66 in accordance with the player's operation. . Further, a card balance display signal indicating a prepaid card balance and a ball lending display signal are given from the card unit 50 to the interface board 66. Between the card unit 50 and the payout control board 37, a connection signal (VL signal), a unit operation signal (BRDY signal), a ball lending request signal (BRQ signal), a ball lending completion signal (EXS signal), and a pachinko machine operation signal ( PRDY signal) is transmitted / received via the input port 372f and the output port 372d. An interface board 66 is interposed between the card unit 50 and the payout control board 37. Therefore, a signal such as a connection signal (VL signal) is transmitted and received between the card unit 50 and the payout control board 37 via the interface board 66 as shown in FIG.

  When the power of the pachinko gaming machine 1 is turned on, the payout control CPU 371 of the payout control board 37 outputs a PRDY signal to the card unit 50. The card unit control microcomputer outputs a VL signal when the power is turned on. The payout control CPU 371 determines the connected / unconnected state of the card unit 50 according to the input state of the VL signal. When a card is received in the card unit 50, the ball lending switch is operated and a ball lending switch signal is input, the card unit control microcomputer outputs a BRDY signal to the payout control board 37. When a predetermined delay time elapses from this point, the card unit control microcomputer outputs a BRQ signal to the payout control board 37.

  Then, the payout control CPU 371 of the payout control board 37 raises the EXS signal to the card unit 50, and when detecting the fall of the BRQ signal from the card unit 50, drives the payout motor 289 to draw a predetermined number of rental balls. Pay to the player. When the payout is completed, the payout control CPU 371 causes the EXS signal to the card unit 50 to fall. Thereafter, when a BRDY signal from the card unit 50 is not in an ON state, a prize ball payout control is executed when a payout command signal is received from the game control means. The power supply voltage AC24V used in the card unit 50 is supplied from the payout control board 37.

  The power supply from the power supply board 910 to the card unit 50 is performed via the payout control board 37 and the interface board 66. In this example, a fuse for protecting the card unit 50 is provided in a 24 V AC power supply line for the card unit 50 arranged in the interface board 66, and a voltage higher than a predetermined voltage is supplied to the card unit 50. It is prevented.

  In this embodiment, the case where the card unit 50 is installed adjacent to the gaming machine as a separate body from the gaming machine is taken as an example, but the card unit 50 may be integrated with the gaming machine. . Further, the present invention can be applied even in the case where game balls corresponding to the amount of money are lent out in accordance with coin insertion.

  FIG. 7 is a block diagram illustrating a circuit configuration example of the effect control board 80, the lamp driver board 35, and the audio output board 70. In the effect control board 80, the effect control CPU 101 operates in accordance with a program stored in a ROM (not shown), and the input driver 102 and the input port according to a strobe signal (effect control INT signal) from the main board 31. An effect control command is received via 103. The effect control CPU 101 performs display control of the variable display device 9 using the LCD via the output port 104 and the LCD drive circuit 106 based on the effect control command, and controls the output port 104 and the lamp drive circuit 107. Display control of the normal symbol display 10 is performed.

  Further, the production control CPU 101 outputs sound number data to the audio output board 70 via the output port 104 and the output driver 110. A bus (including an address bus, a data bus, and a control signal line such as a write / read signal) that is input / output to / from the effect control CPU 101 is extended to the lamp driver board 35 via the bus driver 105.

  In the lamp driver board 35, a bus that is input to and output from the effect control CPU 101 is connected to the output port 352 and the expansion port 353 via the bus receiver 351. A signal for driving each lamp output from the output port 352 is amplified by the lamp driver 354 and supplied to each lamp. A signal for driving each LED output from the output port 352 is amplified by the LED driving circuit 355 and supplied to each LED. A signal for driving the effect driving means 61 is amplified by the drive circuit 356 and supplied to each lamp.

  In this embodiment, lamps / LEDs and effect driving means provided in the gaming machine are controlled by effect control means including effect control CPU 101 mounted on effect control board 80. Further, data for controlling the variable display device 9, the normal symbol display 10, the lamp / LED and the like are stored in the ROM. The effect control CPU 101 controls the variable display device 9, the normal symbol display 10, the lamp / LED, and the like based on the data stored in the ROM. Then, the lamp / LED and the driving means for presentation are driven via the output port 352 and each drive circuit mounted on the lamp driver board 35. Therefore, when changing the model, if the production control board 80 is replaced with a new one, the model change can be realized without replacing the lamp driver board 35.

  Although the production control board 80, the lamp driver board 35, and the audio output board 70 are independent boards, they are installed in a state of being accommodated in one box on the back side of the gaming machine, for example. Further, the expansion port 353 is installed in consideration of the case where the number of lamps / LEDs and the like is increased when changing the model, but it may not be installed. The drive circuit 356 may not be provided when there are no movable members for production, but when changing the model, considering the case where the movable member for production is installed, the movable for production is provided. It is preferably provided even when no member is present.

  In the audio output board 70, the sound number data from the effect control board 80 is input via the input driver 702 to a voice synthesis IC 703 by a digital signal processor, for example. The voice synthesis IC 703 reads data corresponding to the sound number data from the voice data ROM 704, generates voice and sound effects corresponding to the read data, and outputs them to the amplifier circuit 705. The amplification circuit 705 outputs an audio signal obtained by amplifying the output level of the speech synthesis IC 703 to a level corresponding to the volume set by the volume 706 to the speaker 27.

  The data corresponding to the sound number data stored in the sound data ROM 704 is a collection of data indicating the sound effect or sound output mode in a predetermined time period (for example, a special symbol fluctuation period) in time series. When the voice number IC 703 receives the sound number data, the voice synthesis IC 703 performs sound output control according to the corresponding data in the voice data ROM 704. The sound output control according to the corresponding data is continued until the next sound number data is input. When the next sound number data is input, the speech synthesis IC 703 performs sound output control according to the data in the sound data ROM 704 corresponding to the newly input sound number data.

  In this embodiment, the sound and sound output from the speaker 27 are controlled by the effect control means including the effect control CPU 101, but the effect control means outputs the sound number data to the sound output board 70. . In the audio output board 70, the audio data ROM 704 stores a large amount of data for realizing sounds and sound effects that can appear as the game progresses, and these data are associated with the sound number data. . Therefore, the production control means can realize sound output control only by outputting the sound number data. Note that the sound number data is, for example, 1-byte data and is transferred to the audio output board 70 via a serial signal line or a parallel signal line.

  FIG. 8 is a block diagram showing the configuration of the first embodiment of the CPU 56, reset circuit, power supply monitoring circuit, external random number generation means, and monitoring circuit 934 on the main board 31. The external random number generator generates a random number (see FIG. 12) used for determining a big hit by a CPU (game control microcomputer) 56. The external random number generation means includes an oscillator (OSC) 930 as a clock signal generation means and a counter IC 931 as a numerical data update means, and is provided outside the CPU 56 as shown in FIG.

  The oscillator 930 generates a clock signal having a predetermined frequency (for example, 20 MHz). The clock signal generated by the oscillator 930 is input to the counter 932 of the counter IC 931. The counter IC 931 includes a counter 932 and a latch circuit 933 that are 16-bit binary counters, for example. The counter 932 counts the clock signal generated by the oscillator 930. Note that the counter 932, which is a 16-bit binary counter, is configured, for example, by connecting two 8-bit counters in series. When the latch circuit 933 detects the start detection signal from the start port switch 14a, the latch circuit 933 latches the 16-bit counter value (numerical data) of the counter 932 at that time (for example, the rising edge of the start detection signal). The counter value latched by the latch circuit 933 is a 16-bit random value, that is, a value in the range of 0 to 65535. Note that the latch circuit 933 is composed of, for example, two D flip-flops.

  When the start opening switch 14 a detects a winning ball that has entered the start winning opening 14, the start opening switch 14 a outputs a start detection signal notifying that a start winning has occurred to the latch circuit 933 of the counter IC 931 and also via the input port 572 to the CPU 56. Output to. When detecting the start detection signal from the start port switch 14a, the CPU 56 reads the 16-bit counter value latched by the latch circuit 933. The CPU 56 stores the read 16-bit counter value in a predetermined area of the RAM 55 as a jackpot determination random number described later.

  The CPU 56 detects the detection signal from the switch if the detection signal of each switch including the start port switch 14a is continuously on for a predetermined period (for example, a timer interruption interval described later, that is, 2 ms twice). It is determined that Therefore, the time point when the CPU 56 detects the start detection signal from the start port switch 14a is also after the start detection signal is detected for a predetermined period. The latch circuit 933 latches the counter value when the start detection signal from the start port switch 14a rises. As a result, the CPU 56 can always input the counter value latched based on the detection when the start opening switch 14a detects the game ball.

  FIG. 9 is a block diagram illustrating an internal configuration of the monitoring circuit according to the first embodiment. As shown in FIG. 9, the monitoring circuit 934 includes a counter unit 934A, a storage unit 934B, an abnormality determination circuit 934C, and a timer circuit 934D. Similarly to the counter 932, the counter unit 934A counts the clock signal generated by the oscillator 930. For example, the timer circuit 934D counts clock signals supplied to the CPU 56 and outputs a time-up signal each time the counter value reaches a predetermined value. Therefore, the time-up signal is generated periodically. When the abnormality determination circuit 934C detects the time-up signal from the timer circuit 934D, it extracts the counter value of the counter 934A at that time, stores the extracted counter value in the storage unit 934B, and stores it in the storage unit 934B last time. The counter value is compared with the counter value stored this time. If both counter values match as a result of the comparison, the abnormality determination circuit 934C determines that the oscillator 930 has not normally generated a clock signal and outputs an abnormality signal notifying the abnormality of the oscillator 930 to the CPU 56. To do. Based on the abnormality signal output from the monitoring circuit 934, the CPU 56 executes error processing as will be described later. If the two counter values are different, it is considered that the oscillator 930 is generating the clock signal normally, so the abnormality determination circuit 934C does not output an abnormality signal to the CPU 56.

  It is possible that the counter value stored last time in the storage unit 934B matches the counter value stored this time even though no abnormality has occurred in the oscillator 930. Therefore, in order to more reliably determine the abnormality of the oscillator 930, the abnormality determination circuit 934C outputs an abnormality signal to the CPU 56 when it determines that both counter values coincide continuously for a predetermined number of times (for example, two times or three times). You may comprise so that it may output to.

  Further, the configuration of the monitoring circuit 934 is not limited to the configuration illustrated in FIG. For example, the monitoring circuit 934 includes a timer circuit that is restarted when the counter value of the counter unit 934A is updated. When the timer circuit times out, that is, the counter value of the counter unit 934A is updated over a predetermined period. If not, an abnormal signal may be output to the CPU 56. Furthermore, it is possible to detect the waveform of the clock signal generated by the oscillator 930 and to determine whether the oscillator 930 is abnormal based on the detection result.

  As shown in FIG. 8, a power-off signal from the power supply monitoring circuit (power supply monitoring means) 920, that is, a detection signal from the power supply monitoring means is input to the CPU 56 via the inverting circuit 943 and the input port 572. Therefore, the CPU 56 can confirm the occurrence of the stop of the power supply to the gaming machine by monitoring the input signal of the input port 572.

  The power monitoring circuit 920 includes a power monitoring IC 902. The power monitoring IC 902 detects the occurrence of power supply stoppage to the gaming machine by introducing the VSL voltage and monitoring the VSL voltage. Specifically, when the VSL voltage becomes equal to or lower than a predetermined value (+22 V in this example), a power-off signal is output because power supply is stopped. The power supply voltage to be monitored is preferably higher than the power supply voltage (+5 V in this example) of the circuit element mounted on each electric component control board. In this example, VSL, which is a voltage immediately after being converted from AC to DC, is used.

  The reset circuit 65 includes a reset IC 651. When the power is turned on, the reset IC 651 sets the output to a low level for a predetermined time determined by the capacity of the external capacitor, and sets the output to a high level when the predetermined time has elapsed. That is, the reset signal (system reset signal) is raised to a high level to make the CPU 56 operable. The reset signal is input to the reset terminal of the CPU 56 via the inverting circuits 942 and 941.

  In addition, the reset IC 651 monitors the power supply voltage of VSL, which is the power supply voltage equal to the power supply voltage monitored by the power supply monitoring circuit 920, and the voltage value is a predetermined value (than the power supply voltage value at which the power supply monitoring circuit outputs a power-off signal). When the value is less than (low value), the output is set to low level. Therefore, the CPU 56 performs a predetermined power supply stop process in response to the power-off signal from the power supply monitoring circuit 920, and then the system is reset. That is, the operation is completely stopped. Accordingly, the reset circuit 65 corresponds to second power supply monitoring means for outputting the detection signal at a timing later than the timing at which the power supply monitoring means outputs the detection signal. In this example, the state in which the second power supply monitoring unit outputs the detection signal is a state in which the reset signal is set to a low level.

  Next, the operation of the gaming machine will be described. FIG. 10 is a flowchart showing main processing executed by game control means (CPU 56 and peripheral circuits such as ROM and RAM) in the main board 31. When power is turned on to the gaming machine and the input level of the reset terminal becomes high level, the CPU 56 executes a security check process that is a process for confirming whether or not the contents of the program are valid, and then performs step S1. Subsequent main processing is started. In the main process, the CPU 56 first performs necessary initial settings.

  In the initial setting process, the CPU 56 first sets the interrupt prohibition (step S1). Next, the interrupt mode is set so that the address synthesized from the value of the specific register (I register) (1 byte) of the CPU 56 and the interrupt vector (1 byte: least significant bit 0) output by the built-in device is the interrupt address. Is set to interrupt mode 2 (step S2), and a stack pointer designation address is set to the stack pointer (step S3). Then, the built-in device register is initialized (step S4). Further, after initialization (step S5) of CTC (counter / timer) and PIO (parallel input / output port) which are built-in devices (built-in peripheral circuits), the RAM is set to an accessible state (step S6).

  Next, the CPU 56 confirms the state of the output signal of the clear switch 921 input via the input port 1 only once (step S7). When the on-state is detected in the confirmation, the CPU 56 executes normal initialization processing (steps S11 to S15). When the clear switch 921 is on (when pressed), a low-level clear switch signal is output. In the input port 1, the clear switch signal is on at a high level. Further, for example, the game clerk can easily execute the initialization process by starting the power supply to the gaming machine (for example, turning on the power switch 914) while turning the clear switch 921 on. That is, RAM clear or the like can be performed.

  If the clear switch 921 is not in the on state, whether or not data protection processing of the backup RAM area (for example, power supply stop processing such as addition of parity data) has been performed when power supply to the gaming machine is stopped Confirm (step S8). In this embodiment, when power supply is stopped, a process for protecting data in the backup RAM area is performed. If it is confirmed that such protection processing has been performed, the CPU 56 determines that there is a backup. When it is confirmed that such a protection process has not been performed, the CPU 56 executes an initialization process.

  Whether or not there is backup data in the backup RAM area is confirmed by the state of the backup flag set in the backup RAM area in the power supply stop process. For example, if “55H” is set in the backup flag area, it means that there is a backup (ON state), and if a value other than “55H” is set, it means that there is no backup (OFF state).

  If it is determined that there is a backup, the CPU 56 performs a data check of the backup RAM area (parity check in this example) (step S9). In the power supply stop process, the checksum is calculated by the same process as the data check process, and the checksum is stored in the backup RAM area. In step S9, the calculated checksum is compared with the stored checksum. When the power supply is stopped after an unexpected power failure or the like, the data in the backup RAM area should be saved, so the check result (comparison result) is normal (matched). That the check result is not normal means that the data in the backup RAM area is different from the data when the power supply is stopped. In such a case, since the internal state cannot be returned to the state when the power supply is stopped, the initialization process (the processes of steps S10 to S15) executed when the power is turned on, not when the power supply is stopped. Execute.

  If the check result is normal, the CPU 56 performs a game state restoration process for returning the internal state of the game control means and the control state of the electric component control means such as the display control means to the state when the power supply is stopped. Specifically, the start address of the backup setting table stored in the ROM 54 is set as a pointer (step S81), and the contents of the backup setting table are sequentially set in the work area (area in the RAM 55) (step S82). ). The work area is backed up by a backup power source. In the backup setting table, initialization data for an area that may be initialized in the work area is set. As a result of the processing in steps S81 and S82, the saved contents of the work area that should not be initialized remain. The portion that should not be initialized is, for example, a portion in which data indicating a gaming state before stopping power supply (a special symbol process flag or the like) or data indicating the number of unpaid prize balls is set.

  Further, the CPU 56 sets the start address of the backup command transmission table stored in the ROM 54 as a pointer (step S83), and power is supplied to the sub-boards (the payout control board 37 and the effect control board 80) according to the contents. Control is performed so that a control command indicating the recovery is transmitted (step S84). Then, the process proceeds to step S15.

  In the initialization process, the CPU 56 first performs a RAM clear process (step S10). Note that some data may be left as it is without initializing the entire area of the RAM. Further, the start address of the initialization setting table stored in the ROM 54 is set as a pointer (step S11), and the contents of the initialization setting table are sequentially set in the work area (step S12). By the processing of steps S11 and S12, for example, a normal symbol determination random number counter, a normal symbol determination buffer, a special symbol left middle right symbol buffer, a total prize ball number storage buffer, a special symbol process flag, an award ball flag, a ball break An initial value is set for a flag for selectively performing processing according to a control state, such as a flag or a payout stop flag.

  In addition, the CPU 56 sets the initial address of the initialization command transmission table stored in the ROM 54 as a pointer (step S13), and issues an initialization command for initializing the sub board according to the contents of the sub board. The process to transmit to is executed (step S14). Examples of the initialization command include a command indicating an initial symbol displayed on the variable display device 9.

  In step S15, the CPU 56 sets a CTC register built in the CPU 56 so that a timer interrupt is periodically generated, for example, every 2 ms. That is, a value corresponding to, for example, 2 ms is set in a predetermined register (time constant register) as an initial value. In this embodiment, it is assumed that a timer interrupt is periodically taken every 2 ms. A timer interrupt by CTC may be applied based on the clock signal from the transmission circuit 930 supplied to the external random number generation means.

  When the execution of the initialization process (steps S10 to S15) is completed, the display random number update process (step S17) is repeatedly executed in the main process. The CPU 56 sets the interrupt disabled state when the display random number update process is executed (step S16), and sets the interrupt enabled state when the display random number update process ends (step S18). Note that the display random number is a random number for determining a loss symbol displayed on the variable display device 9, and the display random number update process updates the counter value of the counter for generating the display random number. It is processing.

  Note that when the display random number update process is executed, the interrupt disabled state is executed because the display random number update process is also executed in the timer interrupt process described later. This is to avoid doing so. That is, if a timer interrupt occurs during the process of step S17 and the counter value of the counter for generating the display random number is updated during the timer interrupt process, the continuity of the counter value is impaired. There is a case. However, such an inconvenience does not occur if the interrupt is prohibited during the process of step S17.

  When the timer interruption occurs, the CPU 56 executes the game control process of steps S20 to S34 shown in FIG. In the game control process, the CPU 56 first executes a power-off detection process for detecting whether or not a power-off signal has been output (whether the power-off signal has been turned on) (step S20). Subsequently, detection signals of switches such as the gate switch 32a, the start port switch 14a, the count switch 23, and the winning port switches 29a, 30a, 33a, and 39a are input via the switch circuit 58, and their state is determined (switch Process: Step S21). Specifically, if the state of the input port for inputting the detection signal of each switch is ON, the value of the switch timer provided corresponding to each switch is incremented by one.

  Next, the CPU 56 performs a process of updating the counter value of the software configuration counter for generating each determination random number other than the jackpot determination random number used for game control (step S22). The CPU 56 further performs a process of updating the counter value of the software configuration counter for generating the display random number and the initial value random number (steps S23 and S24).

FIG. 12 is an explanatory diagram showing each random number. Each random number is used as follows.
(1) Random 1: Decide whether or not to generate a big hit (for big hit judgment)
(2) Random 2-1 to 2-3 (Random 2): For determining the left middle right of the special symbol (special symbol left middle right)
(3) Random 3: Determines the combination of special symbols that generate a big hit (for determining big hit symbols)
(4) Random 4: Determine the variation pattern of the special symbol (for variation pattern determination)
(5) Random 5: Decide whether or not to reach when no big hit is generated (for reach determination)
(6) Random 6: Determines whether or not to generate a hit based on a normal symbol (for normal symbol hit determination)

  In order to enhance the game effect, random numbers other than the random numbers (1) to (6) are also used. The random numbers (2), (4), and (5) correspond to display random numbers, and the random numbers (1), (3), and (6) correspond to determination random numbers. However, (1) random 1 is a random value obtained by reading the count value of the counter IC 931 as an external random number generating means. Accordingly, the CPU 56 performs a counter update process for generating the random numbers (3) and (6) in the determination random number update process in step S22.

  Further, the CPU 56 performs special symbol process processing (step S25). In the special symbol process control, corresponding processing is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to the gaming state. The value of the special symbol process flag is updated during each process according to the gaming state. Further, normal symbol process processing is performed (step S26). In the normal symbol process, the corresponding process is selected and executed according to the normal symbol process flag for controlling the display state of the normal symbol display 10 in a predetermined order. The value of the normal symbol process flag is updated during each process according to the gaming state.

  Next, the CPU 56 performs a process of setting an effect control command related to the special symbol in a predetermined area of the RAM 55 and sending the effect control command (special symbol command control process: step S27). Further, a process for sending an effect control command by setting an effect control command for the normal symbol in a predetermined area of the RAM 55 is performed (normal symbol command control process: step S28).

  Further, the CPU 56 performs information output processing for outputting data such as jackpot information, start information, probability variation information supplied to the hall management computer, for example (step S29).

  In addition, the CPU 56 executes a prize ball process for setting the number of prize balls based on the detection signals of the prize opening switches 29a, 30a, 33a, 39a (step S30). Specifically, a payout control signal such as a payout number signal indicating the number of winning balls is output to the payout control board 37 in response to detection of a win based on the winning opening switch 29a, 30a, 33a, 39a being turned on. The payout control CPU 371 mounted on the payout control board 37 drives the ball payout device 97 according to a payout control signal such as a payout number signal indicating the number of prize balls.

  And CPU56 performs the memory | storage process which checks the increase / decrease in the number-of-start winning memory | storage number (step S31). In addition, a test terminal process, which is a process for outputting a test signal for enabling the control state of the gaming machine to be confirmed outside the gaming machine, is executed (step S32). Next, the CPU 56 executes error processing as predetermined abnormality control processing based on the input of the abnormality signal from the monitoring circuit 934 (step S33). A RAM area (output port buffer) corresponding to the output state of the output port is provided, and the CPU 56 outputs the contents of the RAM area to the output port (step S34: output processing). Note that the contents of the output port buffer are updated by the processes of steps S25 to S30 and S31. Thereafter, the interrupt permission state is set (step S35), and the process is terminated.

  With the above control, in this embodiment, the game control process is started periodically (for example, every 2 ms). In this embodiment, the game control process is executed by the timer interrupt process. However, in the timer interrupt process, for example, only a flag indicating that an interrupt has occurred is set, and the game control process is performed by the main process. May be executed.

  FIG. 13 is a flowchart showing an example of a special symbol process processing program executed by the CPU 56. The special symbol process shown in FIG. 13 is a specific process of step S25 in the flowchart of FIG. When performing the special symbol process, the CPU 56 performs a variable shortening timer subtraction process (step S310) to detect that a game ball has won the start winning opening 14 provided in the game board 6. If the switch 14a is turned on, that is, if a start winning that causes the game ball to win the start winning opening 14 is generated (step S311), the start opening switch passing process (step S312) is performed, and then according to the internal state. Any one of steps S300 to S308 is performed. The variation shortening timer is a timer for measuring the elapsed time from the start winning prize, and shortens the variation time on condition that a predetermined period or more has elapsed.

  Special symbol normal processing (step S300): Waits until the variable symbol variable display can be started. When the special symbol variable display can be started, the start winning memory number is confirmed. If the start winning memorization number is not 0, it is determined whether or not to win the game as a result of variable display of special symbols. Then, the internal state (special symbol process flag) is updated so as to shift to step S301.

  Special symbol stop symbol setting process (step S301): The stop symbol of the left middle right symbol after variable display of the special symbol is determined. Then, the internal state (special symbol process flag) is updated so as to shift to step S302.

  Fluctuation pattern setting process (step S302): A variation pattern (variable display mode) of variable display of special symbols is determined according to a random 4 value. Also, a variable time timer is started. At this time, the left middle right final stop symbol and information for instructing the variation mode (variation pattern) are transmitted to the effect control board 80. Then, the internal state (special symbol process flag) is updated so as to shift to step S303.

  Special symbol variation process (step S303): When a predetermined time (the time indicated by the variation time timer in step S302) elapses, the internal state (special symbol process flag) is updated to shift to step S304.

  Special symbol stop process (step S304): Control is performed so that all symbols displayed on the variable display device 9 are stopped. Specifically, it sets to the state where the production control command which shows special symbol stop is transmitted. If the stop symbol is a combination of jackpot symbols, the internal state (special symbol process flag) is updated to shift to step S305. If not, the internal state is updated to shift to step S300.

  Big winning opening opening process (step S305): Control for opening the big winning opening is started. Specifically, the counter and the flag are initialized, and the solenoid 21 is driven to open the special winning opening. Also, the process timer sets the execution time of the big prize opening opening process and sets the big hit flag. Then, the internal state (special symbol process flag) is updated so as to shift to step S306.

  Processing for opening a special prize opening (step S306): A process for sending a production control command for displaying a big prize round to the production control board 80, a process for confirming the completion of the closing condition for the special prize opening, and the like are performed. When the closing condition for the last big prize opening is satisfied, the internal state is updated to shift to step S307.

  Specific area valid time process (step S307): The presence / absence of passing through the V winning switch 22 is monitored, and a process of confirming that the big hit gaming state continuation condition is satisfied is performed. If the condition for continuing the big hit gaming state is satisfied and there are still remaining rounds, the internal state is updated to shift to step S305. In addition, when the big hit gaming state continuation condition is not satisfied within a predetermined effective time, or when all rounds are finished, the internal state is updated to shift to step S308.

  Big hit end processing (step S308): Control for causing the effect control means to perform display control for notifying the player that the big hit gaming state has ended. Then, the internal state is updated so as to shift to step S300.

  FIG. 14 is a flowchart showing the start port switch passing process (step S312). In the start port switch passing process, the CPU 56 checks whether or not the start winning memorized number has reached 4 which is the maximum value (step S111). If the starting winning memory number has not reached 4, the starting winning memory number is increased by 1 (step S112), each random number value such as a big hit determination random number is extracted, and stored corresponding to the starting winning memory value Store in the area (special symbol determination buffer) (step S113). The extraction of random numbers means that for random numbers other than random 1, the count value is read from the counter for generating the random number, and the read count value is used as the random value. For random 1, the counter value is read from the latch circuit 933 of the counter IC 931 as an external random number generation means, and the read counter value is used as a random value. In step S113, random numbers 1 to 5 are extracted from the random numbers shown in FIG. In step S114, a timer for determining whether or not to shorten the variation time is set.

  FIG. 15 is a flowchart showing the special symbol normal process (step S300) in the special symbol process. In the special symbol normal process, the CPU 56 is in a state where the variation of the special symbol can be started (for example, when the value of the special symbol process flag is a value indicating step S300) (step S51), the start winning memory is stored. The value of the number is confirmed (step S52). Specifically, the counter value of the start winning counter is confirmed. The case where the value of the special symbol process flag is a value indicating step S300 is a case where the symbol is not changed in the variable display device 9 and the game is not a big hit game.

  If the starting winning memory number is not 0, each random number value stored in the storage area corresponding to the starting winning memory number = 1 is read and stored in the random number buffer area of the RAM 55 (step S53), and the starting winning memory number 1 is reduced by 1 and the contents of each storage area are shifted (step S54). That is, each random number value stored in the storage area corresponding to the start winning memory number = n (n = 2, 3, 4) is stored in the storage area corresponding to the starting winning memory number = n−1.

  Next, the CPU 56 reads the jackpot determination random number from the random number storage buffer (step S55), and executes the jackpot determination module (step S56). When it is determined to be a big hit (step S57), the CPU 56 sets a big hit flag (step S58). Then, the value of the special symbol process flag is updated to a value corresponding to the special symbol stop symbol setting process (step S59).

  FIG. 16 is a flowchart showing the special symbol stop symbol setting process (step S301) in the special symbol process. In the special symbol stop symbol setting process, the CPU 56 checks whether or not the big hit flag is set (step S61). When the big hit flag is set, the big hit symbol is determined according to the value of the big hit symbol random number (random 3) (random 3 read in step S53) (step S62). In this embodiment, each symbol of the symbol number set in the jackpot symbol table corresponding to the value of random 3 is determined as a jackpot symbol. In the jackpot symbol table, left, middle and right symbol numbers corresponding to a plurality of types of combinations of jackpot symbols are set. Then, the value of the special symbol process flag is updated to a value corresponding to the variation pattern setting process (step S63).

  When the big hit flag is not set, the CPU 56 executes a reach determination module (step S65). Here, in the reach determination module, it is determined whether or not to reach based on the random 3 value read from the storage area in step S53, that is, the value stored in the random value buffer (step S64). Further, the left and right symbols are determined according to the value of random 2-1, and the middle symbol is determined according to the value of random 2-2 (step S67). Here, if the determined middle symbol matches the left and right symbols, the symbol corresponding to the value obtained by adding 1 to the random number corresponding to the middle symbol is set as the stop symbol of the middle symbol so that it does not match the jackpot symbol. To do. Then, the process proceeds to step S63.

  If it is decided not to reach in step S66, a stop symbol in the case of a loss is determined (step S68). Specifically, the left symbol is determined according to the value read in step S53, that is, the extracted random 2-1 value, the middle symbol is determined according to the random 2-2 value, and the random 2-3 value is determined. The right design is determined according to. Here, when the left and right symbols match, the right symbol is shifted by one symbol so that it does not become reach. Then, the process proceeds to step S63. When the probability variation symbol is determined in step S62, a probability variation flag indicating that the game is shifted to the probability variation state after the big hit game is ended is set.

  FIG. 17 is a flowchart showing error processing by the game control means. The error process shown in FIG. 17 is a specific process of step S33 in the flowchart of FIG. The CPU 56 checks whether there is an input of an abnormality signal from the abnormality determination circuit 934C of the monitoring circuit 934 (step S321). If no abnormality signal is input, that is, if abnormality of the oscillator 930 is not detected by the abnormality determination circuit 934C, the CPU 56 ends the error processing without executing the processing of steps S322 to 327.

  When an abnormal signal is input in step S321, that is, when an abnormality of the oscillator 930 is detected by the abnormality determination circuit 934C, the CPU 56 outputs a power supply confirmation signal (to be output to the payout control means mounted on the payout control board 37). 25 and 26) is turned off (step S322). The payout control means detects the off state of the power supply confirmation signal, thereby stopping the game ball payout process and making it impossible to fire the game ball.

  Next, the CPU 56 performs a process for transmitting a command for an abnormal time control process to the sub-board (step S323). The sub board is, for example, an effect control board 80. The command for control processing at the time of abnormality is, for example, a notification command for causing the effect control means to notify that an abnormality has occurred in the oscillator 930. When receiving the notification command, the effect control CPU 101 mounted on the effect control board 80 causes the variable display device 9 as the notification means, the lamp / LED, the speaker 27, and the like to notify that an abnormality has occurred.

  Next, the CPU 56 stores the current control state, for example, the output state of the output port, in the RAM 55 (step S324). Then, the CPU 56 clears the output state of the output port (step S325). As signals output from the output port, there are a payout control signal (payout number signal and prize ball REQ signal) transmitted to the payout control board 37, a drive signal for the solenoids 16, 21, 21A, and the like. Accordingly, when the output state of the output port is cleared, the drive signal is cleared and the variable winning ball device 15 and the opening / closing plate 20 are closed by the solenoids 16, 21, 21A.

  Next, the CPU 56 checks whether or not error cancellation has been performed (step S326). Unless the error is canceled, the game control by the CPU 56 is not performed. That is, in the game control process of steps S20 to S34 shown in FIG. 11, the process does not proceed from the error process of step S33, and the game control by the CPU 56 is stopped. Therefore, the special symbol process process in step S25 is not executed, and the control process related to the game value provision relating to the game is stopped. As a method for canceling the error, for example, there is a method of turning on the clear switch 921 after eliminating the abnormal state.

  When the error is canceled, the CPU 56 restores the output state of the output port based on the control state stored in the RAM 55 (step S327). Therefore, the game control by the CPU 56 proceeds from the control state immediately before the abnormality occurs.

  FIG. 18 is a flowchart illustrating an example of command creation processing. The command creation process is a process including a command output process and an INT signal output process. The command creation process is a game control process in which a special command process process in step S25, a special symbol command control process in step S27, a normal symbol command control process in step S28, and a step S323 in an error process when creating a control command. Is called. In this embodiment, it is assumed that the effect control command has a 2-byte configuration of MODE data (data indicating the classification of the command) and EXT data (data indicating the type of command).

  In this embodiment, each effect control command that can be transmitted to the effect control means is stored in a ROM command transmission table. One command transmission table is composed of 3-byte data (INT data, command data 1 and command data 2). 80 (H) is set in the INT data. In the command data 1, MODE data is set. The command data 2 is set with EXT data (specifically, a pointer value to a command extension data address table described later). In the command creation process, the CPU 56 sets the effect control command data stored at the address of the ROM 54 indicated by the pointer as an output port for outputting the effect control command data, and indicates that the command is transmitted. An effect control INT signal is output. When calling the command creation process, the address of the command transmission table storing the effect control command to be transmitted is set in, for example, a register.

  In the command creation process, the CPU 56 first saves the address of the command transmission table in a stack or the like (step S331). Then, the INT data of the command transmission table pointed to by the pointer is loaded into the argument 1 (step S332). The argument 1 is input information for a command transmission process to be described later. Also, the address indicating the command transmission table is incremented by 1 (step S333). Therefore, the address indicating the command transmission table matches the address of the command data 1.

  Next, the CPU 56 reads the command data 1 and sets it to the argument 2 (step S334). The argument 2 is also input information for a command transmission process to be described later. Then, the command transmission processing routine is called (step S335).

  FIG. 28 is a flowchart showing a command transmission processing routine. In the command transmission processing routine, the CPU 56 first sets the data set as the argument 1, that is, the INT data, in the work area determined as the comparison value (step S351). Next, the transmission count = 1 is set in the work area determined as the number of processes (step S352). Then, the address of port 1 is set to the IO address (step S353). As shown in FIG. 12, the address of port 1 is the address of the output port for outputting the presentation control command data.

  Next, the CPU 56 shifts the comparison value to the left by 1 bit (step S354). As a result of the shift processing, it is confirmed whether or not the carry bit has become 1 (step S355). When the carry bit becomes 1, it means that the leftmost bit in the INT data is “1”.

  When the carry bit becomes 1, the data set in the argument 2, in this case, the command data 1 (that is, MODE data) is output to the address set as the IO address (step S 356). When the second shift process is performed, the port 2 address is set as the IO address. At that time, the MODE data of the effect control command is output to the port 2.

  Next, the CPU 56 adds 1 to the IO address (step S357) and subtracts 1 from the number of processes (step S358). Then, the CPU 56 confirms the value of the number of processes (step S359), and if the value is not 0, returns to step S354. In step S354, the shift process is performed again.

  In this embodiment, the control command transmitted by the command transmission process is only the effect control command, but the command transmission process program can be easily used for gaming machines that transmit other types of control commands. Can do. For example, if it is necessary to handle another type of control command in addition to the effect control command, 2 may be set as the number of transmissions in step S352.

  Next, the CPU 56 reads the content of the argument 1 in which the INT data before the start of the shift process is stored (step S360), and outputs the read data to the port 0 (step S361). In this embodiment, port 0 has a bit for outputting an effect INT signal (see FIG. 12). Therefore, the effect control INT signal is turned off (low level) by the process of step S361. Since port 0 also has bits (bits 0 to 6: see FIG. 12) for outputting signals other than the effect control INT signal, only bit 7 of the read data is reflected on port 0 in step S361. .

  Next, the CPU 56 sets a predetermined value in the wait counter (step S362), and subtracts one by one until the value becomes 0 (steps S363 and S364). When the value of the wait counter becomes 0, clear data (data for setting bit 7 to 0) is set (step S365), and the data is output to port 0 (step S366). Therefore, the INT signal is turned off. Then, a predetermined value is set in the wait counter (step S362), and 1 is subtracted one by one until the value becomes 0 (steps S368 and S369).

  As described above, the MODE data of the first byte of the control command is transmitted. Therefore, the CPU 56 adds 1 to the value indicating the command transmission table in step S336 shown in FIG. Therefore, the command data 2 area of the third byte is designated. The CPU 56 loads the contents of the indicated command data 2 into the argument 2 (step S337). Further, it is confirmed whether or not the value of bit 7 (work area reference bit) of the command data 2 is “0” (step S339). If not 0, the head address of the command extended data address table is set in the pointer (step S339), and the value of bit 6 to bit 0 of the command data 2 is added to the pointer to calculate the address (step S340). Then, the data of the area indicated by the address is loaded into the argument 2 (step S341).

  In the command extended data address table, EXT data that can be sent to the effect control means is sequentially set. Therefore, if the value of the work area reference bit is “1” by the above processing, the EXT data in the command extended data address table corresponding to the contents of the command data 2 is loaded into the argument 2 and the work area reference bit If the value is “0”, the contents of the command data 2 are loaded into the argument 2 as they are. Even when EXT data is read from the command extension data address table, bit 7 of the data is “0”.

  Next, the CPU 56 calls a command transmission processing routine (step S342). Therefore, the EXT data is transmitted at the same timing as the transmission of MODE data. Thereafter, the CPU 56 restores the address of the command transmission table (step S343), and updates the value of the read pointer indicating the command transmission table (step S344). If there are more commands to be sent (step S345), the process returns to step S331.

  As described above, the production control command having a 2-byte configuration is transmitted to the production control means of the production control board 80. When the effect control means detects a change in the level of the INT signal, the effect control command starts the process of capturing the effect control command.

  Then, when the effect control means recognizes that the received effect control command is a notification command, the effect control means performs control to display that an error has occurred on the variable display device 9.

  FIG. 20 is an explanatory diagram showing an example of error display by the variable display device 9. As shown in FIG. 20, when error processing is executed, “error” is displayed above the variable display of the special symbol in the variable display device 9. A store clerk or the like of an amusement store can easily grasp that an abnormality has occurred in the external random number generation means by such an error display. Also, when developing a gaming machine, it is possible to easily grasp that some abnormality has occurred in the external random number generation means.

  The notification that an abnormality has occurred is not limited to the case where it is performed using the variable display device 9, but is performed using other electrical components provided in the gaming machine, that is, the lamp / LED or the speaker 27. Also good. For example, a lamp / LED may be blinked, or sound may be output from the speaker 27 in a predetermined manner to notify that an abnormality has occurred. Further, notification may be performed using all or a combination of the variable display device 9, the lamp / LED, and the speaker 27.

Embodiment 2. FIG.
FIG. 21 is a block diagram showing the configuration of the second embodiment of the CPU 56, reset circuit, power supply monitoring circuit, external random number generation means, and monitoring circuit 935 on the main board 31. In FIG. 21, the same description as that shown in FIG. 8 will not be repeated. The external random number generation means includes an oscillator (OSC) 930 as a clock signal generation means and a counter IC 931 as a numerical data update means, similarly to the external random number generation means shown in FIG.

  When the start opening switch 14 a detects a winning ball that has entered the start winning opening 14, the start opening switch 14 a outputs a start detection signal notifying that a start winning has occurred to the latch circuit 933 and the monitoring circuit 935 of the counter IC 931 and also at the input port 572. To the CPU 56 via The monitoring circuit 935 as monitoring means latches the counter value counted by the counter 932 in accordance with the start detection signal from the start port switch 14a. The monitoring circuit 935 monitors an abnormality related to the update of the random number value (counter value) by the external random number generation unit based on the latched counter value.

  FIG. 22 is a block diagram illustrating an internal configuration of the monitoring circuit according to the second embodiment. As shown in FIG. 22, the monitoring circuit 935 includes a latch circuit 935A, a storage unit 935B, an abnormality determination circuit 935C, and a timer circuit 935D. When detecting the start detection signal from the start port switch 14a, the latch circuit 935A latches the counter value of the counter 932 at that time. For example, the timer circuit 935D counts clock signals supplied to the CPU 56 and outputs a time-up signal each time the counter value reaches a predetermined value. Therefore, the time-up signal is generated periodically. When the abnormality determination circuit 935C detects the time-up signal from the timer circuit 935D, the abnormality determination circuit 935C stores the counter value latched by the latch circuit 935A in the storage unit 935B, and stores the counter value previously stored in the storage unit 935B and this time. Compare counter values.

  The abnormality determination circuit 935C outputs an abnormality signal for notifying the abnormality to the CPU 56 when the counter values match as a result of the comparison. If both counter values match, an abnormality relating to updating of the counter value by the external random number generation means has occurred. That is, it is conceivable that the oscillation of the oscillator 930 has stopped, or the counter 932 has not correctly counted the clock signal. Therefore, when an abnormal signal is output from the monitoring circuit 935, the CPU 56 executes error processing as in the case of the second embodiment. If the counter values are different, the external random number generation means is considered to be operating normally, and the abnormality determination circuit 935C does not output an abnormality signal to the CPU 56.

  It is possible that the counter value stored last time in the storage unit 935B matches the counter value stored this time even though no abnormality has occurred in the external random number generation means. In this case, in order to more reliably determine the abnormality of the external random number generation means, the abnormality determination circuit 935C generates an abnormality when it is determined that both counter values coincide with each other continuously for a predetermined number of times (for example, two times or three times). You may comprise so that a signal may be output to CPU56.

Embodiment 3 FIG.
FIG. 23 is a block diagram showing the configuration of the third embodiment of the CPU 56, reset circuit, power supply monitoring circuit, and external random number generation means on the main board 31. In FIG. As shown in FIG. 23, in this embodiment, a monitoring circuit for monitoring an abnormality of the external random number generation means is not provided. In the third embodiment, the CPU 56 monitors the abnormality of the external random number generation means. When the CPU 56 detects the abnormality, it executes a predetermined error process.

  FIG. 24 is a flowchart showing error processing by the game control means in the third embodiment. The error process shown in FIG. 24 is a specific process of step S33 in the flowchart of FIG. The CPU 56 executes error processing when a start detection signal from the start port switch 14a is detected. Therefore, in the error processing, when the start detection signal from the start port switch 14a is turned on (step S401), the CPU 56 determines the big hit extracted from the latch circuit 933 of the counter IC 931 constituting the external random number generation means. The random number value (counter value) of the random number for use is stored in a predetermined area of the RAM 55 (step S328). The CPU 56 compares the random number value newly stored in the predetermined area of the RAM 55 with the previously stored random number value, and determines whether or not the two random number values match (step S329).

  If the two random numbers are different, the CPU 56 ends the error process without executing the processes of steps S322 to S327.

  If the two random number values match, it is considered that an abnormality relating to the update of the random number value by the external random number generation means has occurred. For example, the oscillation of the oscillator 930 is stopped, the counter 932 is not normally counting the clock signal, the signal line connecting the start port switch 14a and the latch circuit 933 is disconnected, and the latch circuit 933 generates the start detection signal. It may not be detected. Therefore, the CPU 56 performs the same processing as steps S322 to S327 shown in FIG.

  That is, the CPU 56 turns off the power supply confirmation signal output to the payout control CPU 371 mounted on the payout control board 37 (step S322). Then, the CPU 56 transmits a command for abnormal control processing to the sub-board (step S323). Next, the CPU 56 stores the current control state, for example, the output state of the output port, in the RAM 55 (step S324). Then, the CPU 56 clears the output state of the output port (step S325). Next, the CPU 56 checks whether or not error cancellation has been performed (step S326). At this time, unless the error is canceled, the game control by the CPU 56 is not performed. When the error is canceled, the CPU 56 restores the output state of the output port based on the control state stored in the RAM 55 (step S327). Thereby, the control of the game by the CPU 56 proceeds from the control state immediately before the abnormality occurs.

  As described above, in the third embodiment, such an abnormality is monitored instead of providing the monitoring circuits 934 and 935 for monitoring the abnormality of the external random number generation means as in the first and second embodiments. The monitoring means for this is realized by software. Accordingly, there is no need to provide a chip on which the monitoring circuits 934 and 935 are mounted, and it is possible to reduce the cost of the gaming machine. It is also possible to provide a software configuration monitoring unit that can flexibly cope with a change in the model of the gaming machine.

  The CPU 56 executes error processing when it detects a detection signal from the start port switch 14a, but it also executes error processing when it does not detect a detection signal from the start port switch 14a. May be. That is, it may be configured such that an error process is always executed every time a timer interrupt occurs and a game control process is executed. Even in this case, the timer interrupt is generated every 2 ms, whereas the counter 932 of the counter IC 931 counts, for example, a 20 MHz clock signal, so that the timer interrupt is generated and the counter 932 counts the clock signal. Are not synchronized. Therefore, when the external random number generation means including the oscillator 930 and the counter IC 931 is operating normally, even if error processing is always executed every time a timer interrupt occurs and game control processing is executed. The random number value stored in the predetermined area of the RAM 55 does not always become a constant value.

  Next, payout control signals transmitted and received between the main board 31 and the payout control board 37 will be described. FIG. 25 is an explanatory diagram showing an example of the contents of a control signal output from the game control means to the payout control means and a payout control signal input from the payout control means to the game control means. In this embodiment, a plurality of types of control signals are exchanged between the main board 31 and the payout control board 37 in order to perform various controls relating to the payout control and the like. As shown in FIG. 25, the power supply confirmation signal is output when the main board 31 rises, and a signal for notifying the payout control board 37 that the main board 31 has risen (connection confirmation signal for the main board 31). It is. Further, as described above, the power supply confirmation signal is turned off when power-off is detected and when an error occurs, and power-off detection is performed on the main board 31 with respect to the payout control board 37, and an error has occurred. It is also used as a signal for notifying.

  The prize ball REQ signal becomes a low level (output state = on state) at the time of a prize ball payout request, and becomes a high level (stop state = off state) at the end of the payout request (that is, a trigger signal for a prize ball payout request). ). The prize ball REQ signal is at a high level (stopped state) when the prize ball payout is forcibly stopped, and is also used as a forced stop stop signal for instructing the prize ball payout to be forcibly stopped. The payout number signal is a signal that is output to designate the number of game balls (1 to 15) that make a payout request.

  The payout BUSY signal (the signal for paying out a winning ball) is a signal used by the main board 31 to confirm the operation state on the payout control board 37. Each control signal only needs to be configured so that the output state or the on state and the stop state or the off state can be distinguished, and the above logic may be reversed in polarity.

  FIG. 26 is a block diagram showing signal lines and the like used for transmission / reception of each control signal shown in FIG. As shown in FIG. 26, the power confirmation signal, the prize ball REQ signal, and the payout number signal are output by the CPU 56 via the output circuit 67 and input to the payout control CPU 371 via the input circuit 373A. Further, the payout BUSY signal is output by the payout control CPU 371 via the output circuit 373B and input to the CPU 56 via the input circuit 68. Each of the power confirmation signal, the prize ball REQ signal, and the payout BUSY signal is 1-bit data, and is transmitted through one signal line. Since 1 to 15 payout number signals are designated, it is composed of 4-bit data and transmitted through four signal lines.

  Next, the operation of the payout control means will be described. FIG. 27 is a flowchart showing main processing executed by the payout control means. In the main process, the payout control CPU 371 first performs necessary initial settings. That is, the payout control CPU 371 first sets the interruption prohibition (step S701). Next, the interrupt mode is set to interrupt mode 2 (step S702), and a stack pointer designation address is set to the stack pointer (step S703). The payout control CPU 371 initializes the built-in device register (step S704), initializes the CTC and PIO (step S705), and then sets the RAM in an accessible state (step S706).

  In this embodiment, one channel of the built-in CTC is used in the timer mode. Accordingly, in the built-in device register setting process in step S704 and the process in step S705, register setting for setting the channel to be used to timer mode, register setting for permitting interrupt generation, and setting an interrupt vector. The register is set. The interrupt by the channel is used as a timer interrupt. For example, when it is desired to generate a timer interrupt every 2 ms, a value corresponding to 2 ms is set as an initial value in a predetermined register (time constant register).

  The interrupt vector set for the channel set to the timer mode (channel 3 in this embodiment) corresponds to the start address of the timer interrupt process. Specifically, the start address of the timer interrupt process is specified by the value set in the I register and the interrupt vector. In the timer interrupt process, a payout control process is executed.

  In this embodiment, the interruption mode 2 is also set in the payout control CPU 371. Therefore, it is possible to use an interrupt process based on counting up the built-in CTC. Also, an interrupt processing start address can be set according to the interrupt vector sent by the CTC.

  The interrupt based on CTC channel 3 (CH3) count-up is an interrupt generated when the CPU internal clock (system clock) is counted down and the register value becomes “0”, and is used as a timer interrupt. . Specifically, a clock obtained by dividing the operation clock of the CPU 371 is given to the CTC, the register value is subtracted by the input of the clock, and when the register value becomes 0, a timer interrupt occurs. For example, the register value of CH3 is subtracted at 1/256 period of the system clock. Since the subtraction is performed based on the divided clock, the initial value of the register does not increase.

  Next, the payout control CPU 371 executes normal initialization processing (steps S711 to S713). In the initialization process, the payout control CPU 371 first performs a RAM clear process (step S711). In addition, initial values are set in flags and counters in the RAM area. Then, the CTC register provided in the payout control CPU 371 is set so that a timer interrupt is periodically generated (step S712). That is, a value corresponding to the timer interrupt generation interval is set as an initial value in a predetermined register (time constant register). Since the interruption is prohibited in step S701 of the initial setting process, the interruption is permitted before the initialization process is finished (step S713). Thereafter, the loop processing is started.

  As described above, in this embodiment, the built-in CTC of the payout control CPU 371 is set to repeatedly generate a timer interrupt. When a timer interrupt occurs, a payout control process (steps S750 to S760) is executed in the timer interrupt process.

  In the payout control process, the payout control CPU 371 first performs an excitation pattern output process for the firing motor 94 (output of the patterns of the firing motors φ1 to φ4 to the output port 0) (step S750). In the firing motor control process in step S752, the excitation pattern is stored in the excitation pattern buffer that is the RAM area. In step S750, the payout control CPU 371 outputs the contents of the excitation pattern buffer to the lower 4 bits of the output port 0. Perform the process.

  Next, the payout control CPU 371 executes a switch process (step S751). The switch process is the same process as the switch process in the game control means. If the state of the input port for inputting the detection signal of each switch is ON, the value of the switch timer provided for each switch +1.

  Next, the payout control CPU 371 executes a firing motor control process (step S752). In the firing motor control process, the patterns of the firing motors φ1 to φ4 are stored in the excitation pattern buffer. When the firing motor 94 should be disabled, the patterns of the firing motors φ1 to φ4 that do not rotate the firing motor 94 are stored in the excitation pattern buffer. Also, the payout control CPU 371 executes a payout motor control process (step S753). In the payout motor control process, when the payout motor 289 is to be driven, a process for outputting the patterns of the payout motors φ1 to φ4 to the output port 0 is performed. Then, a prepaid card unit control process for communicating with the card unit 50 is executed (step S754).

  Next, the payout control CPU 371 executes main control communication processing for communicating with the game control means of the main board 31 (step S755). Further, a payout control process is performed to pay out the lent balls in response to a ball lending request from the card unit 50, and to control to pay out the number of prize balls indicated by the payout number signal from the main board ( Step S756).

  Then, the payout control CPU 371 executes error processing for detecting various errors (errors detected by the payout control means) (step S757). Further, an information output process for outputting prize ball information and ball lending information output to the outside of the gaming machine is executed (step S758). Further, a predetermined display is performed on the error display LED 374 according to the result of the error processing, and a display control process for lighting the prize ball LED 51 and the ball out LED 52 is executed (step S759). In the display control process, the payout control CPU 371 performs control for lighting the prize ball LED 51 when the prize ball REQ signal is on. Further, when the prize ball REQ signal is turned off, control for turning off the prize ball LED 51 is performed.

  As in the case of the game control means, a RAM area (output port buffer) corresponding to the output state of the output port is provided, and the payout control CPU 371 outputs the contents of the output port buffer to the output port. (Step S760: output process). However, since the lower 4 bits (fire motors φ1 to φ4) of output port 0 are executed in step S750, the output of the lower 4 bits of output port 0 is not performed in the output process. The output port buffer is updated by a payout motor control process (step S753), a prepaid card control process (step S754), a main control communication process (step S755), an information output process (step S758), and a display control process (step S759). The

  FIG. 29 is a flowchart showing the firing motor control process in step S752. In the firing motor control process, the payout control CPU 371, when the VL signal from the card unit 50 is in an off state (prepaid card is not connected), when the power confirmation signal from the main board 31 is in an off state (main board is not yet connected). Connection), or when the full tank switch 48 is in the ON state (bottom pan full), the process proceeds to step S518 (steps S511, S512, S513). If the prepaid card is not connected, the main board is not connected, and the lower pan is not full, the process proceeds to step S514. In step S514, the payout control CPU 371 checks whether or not the touch sensor signal is on. If it is in the on state, the process proceeds to step S515, and if it is not in the on state, the process proceeds to step S518. As described above, the payout control means includes the game controllable state detection means (the part that executes step S512) that detects that the game control means is in the controllable state by the power supply confirmation signal, and further includes the game control means. On the condition that the game controllable state detecting means detects that the control is in the controllable state, the firing control means for making the firing motor 94 operable (the processing of steps S515 to S517 is performed according to the result of step S512). Part to be executed).

  In step S515, the payout control CPU 371 increments the firing motor excitation pattern counter by one. Then, data corresponding to the value of the excitation pattern counter is read from the firing motor excitation pattern table stored in the ROM (step S516). Further, the read data is set in the firing motor excitation pattern buffer (step S517). As described above, the contents of the firing motor excitation pattern buffer are output to the output port in step S750. In the firing motor excitation pattern table, the excitation pattern data (shooting motors φ1 to φ4) for each step for rotating the firing motor 94 is sequentially set.

  In step S518, non-rotation data (excitation pattern for preventing the firing motor 94 from rotating) is set in the firing motor excitation pattern buffer.

  As described above, when a communication error such as a main board unconnected error occurs, the firing motor 94 is disabled, so that the game does not proceed despite the occurrence of a communication error. In addition, when the game control means detects an abnormality in the external random number generation means, the power supply confirmation signal is turned off, so that when viewed from the payout control means, even when an abnormality occurs in the external random number generation means, the main board A communication error of unconnected error will occur. That is, when an abnormality occurs in the external random number generation means, the firing motor 94 is disabled.

  FIG. 30 is a flowchart showing the payout control process in step S756. In the payout control process, when the payout control CPU 371 confirms that the detection signal of the payout count switch 301 is turned on, the payout control CPU 371 decreases the value of the unpaid-out number counter by 1. Thereafter, any one of steps S610 to S612 is executed according to the value of the payout control code.

  FIG. 31 is a flowchart showing the payout start waiting process (step S610) executed when the payout control code is 0. In the payout start waiting process, the payout control CPU 371 does not execute the subsequent processes if the error bit is set (step S621). On the other hand, if the BRDY signal is not in the ON state, the process for paying out a prize ball after step S631 is executed. If the BRDY signal is on and the BRQ signal that is a ball lending request signal is on, a ball lending operation flag is set (steps S623 and S624). Then, “25” is set in the unpaid number counter (step S625), and “25” is set in the unpaid number counter in the payout motor rotation count buffer (step S626).

  When the game control means detects an abnormality in the external random number generation means, the power confirmation signal is turned off, so that an error bit is set. Therefore, when an abnormality occurs in the external random number generation means, the processing after step S622 is not executed, so that the ball payout processing is not executed.

  The payout motor rotation frequency buffer is referred to in the payout motor control process (step S723). That is, in the payout motor control process, control is performed to rotate the payout motor 289 by the number of rotations corresponding to the value set in the payout motor rotation frequency buffer.

  Thereafter, the payout control CPU 371 sets a value (specifically “1”) corresponding to the payout motor activation preparation process (step S522) to the payout motor control code for selecting the process executed in the payout motor control process. It is set (step S634), the value of the payout control code is set to 1 (step S635), and the process is terminated.

  In step S631, the payout control CPU 371 checks whether or not the value of the unpaid-out number counter is 0 (step S631). If 0, the process ends. In the unpaid-out number counter, a value other than 0 (number indicated by the number-of-paid-out signal) is set in step S546 in the main control communication normal process, that is, when a prize ball REQ signal is received from the game control means of the main board 31. Has been. Accordingly, when the value of the unpaid-out number counter is not 0, a prize ball operating flag is set (step S632), and the value of the unpaid-out number counter is set in the payout motor rotation number buffer (step S633). Then, control goes to a step S634.

  FIG. 32 is a flowchart showing a payout motor stop waiting process (step S611) executed when the payout control code is 1. In the payout motor stop waiting process, the payout control CPU 371 checks whether or not the payout operation is completed (step S641). For example, the payout control CPU 371 sets a flag to that effect when the payout motor brake process (step S525) in the payout motor control process ends, and whether the payout operation is completed by checking the flag in step S641. You can check whether or not.

  When the payout operation is completed, the payout control CPU 371 sets the payout passing monitoring time in the payout control monitoring timer (step S642). The payout passing monitoring time is a time that has a margin in the time from when the last payout ball is paid out by the payout motor 289 until it passes through the payout count switch 301. Then, the value of the payout control code is set to 2 (step S643), and the process ends.

  FIG. 33 is a flowchart showing a payout passing waiting process (step S612) executed when the value of the payout control code is 2. In the payout passing waiting process, the payout control CPU 371 first decrements the value of the payout control timer by 1 (step S651). Then, the value of the payout control timer is confirmed. If the value is not 0, that is, if the payout control timer has not timed out, the process is terminated.

  If the payout control timer has timed out, the value of the unpaid-out number counter is confirmed (step S653). If the payout operation is normally executed, all the game balls paid out by the payout motor 289 pass through the payout count switch 301 before the payout control timer times out, and an unpaid-out counter is obtained by the processing of steps S601 and S602. The value of is 0. When the value of the unpaid-out number counter indicates a positive value, it means that the number of game balls actually paid out is less than the planned payout number (insufficient payout). Further, when the value of the unpaid-out number counter indicates a negative value, it means that the number of game balls actually paid out is larger than the planned payout number (excess payout).

  The payout control CPU 371 changes the internal state indicating that the payout process is being performed to a state where the payout process is not being performed when the value of the unpaid-out number counter is not a positive value (when the payout is not insufficient). Specifically, when the ball lending operation is being executed, that is, when the ball lending operation flag is set, the ball lending operation flag is reset (steps S654 and S655). Further, when the winning ball motion is being executed, that is, when the winning ball motion flag is set, the winning ball motion flag is reset (steps S654 and S656). Thereafter, the re-payout operation counter is cleared (step S667), the value of the payout control code is set to 0 (step S658), and the process ends. If the payout operation is normally executed, the process of step S657 is unnecessary, but after the corrected payout process described later is executed, the process of step S657 is required. Further, in this embodiment, it is considered that the payout process is normally completed even when there is an excessive payout. However, when there is an excessive payout, it may be notified that an error has occurred.

  When it is confirmed in step S653 that the value of the unpaid-out number counter is a positive value, the payout control CPU 371 performs control for the corrected payout process in steps S661 to S666. Here, a maximum of two re-payout operations are performed until the number of game balls to be paid out is paid out. An error bit is set when the number of game balls to be paid out is not paid out even after two re-payout operations are performed.

  In step S661, the payout control CPU 371 checks whether or not the value of the re-payout operation counter is 2. If not 2, the value of the unpaid number counter is set in the payout motor rotation number buffer (step S662), and the value (“1”) corresponding to the payout motor start preparation process is set in the payout motor control code ( Step S663). Further, the value of the re-payout operation counter is incremented by 1 (step S664), the value of the payout control code is set to 1 (step S665), and the process is terminated. The processing in steps S662, S663, and S665 is the same as the processing in steps S633 to S635 in the payout start waiting process, although the values set in the payout motor rotation frequency buffer are different.

  In step S661, when it is confirmed that the value of the re-payout operation counter is 2, the payout control CPU 371 sets a payout count switch non-passing error bit (payout case error bit) in the error flag ( Step S666), the process is terminated.

  Therefore, in this embodiment, the prize game medium payout control means in the payout control means is based on the detection signal from the payout count switch 301 as the payout detection means, and is a volatile storage means (in this example, an unpaid number counter). When it is detected that a prize game medium that has less than the number of payouts stored in the game has been paid out, the prize game is insufficient for the payout means up to a predetermined number of times (in this example, twice). Have the media dispensed.

  FIG. 34 is a flowchart showing the error processing in step S757. In the error processing, the payout control CPU 371 checks the error flag, and the set bits are only payout switch abnormality detection error 2, payout case error and prize ball REQ signal error (any one of the three). It is confirmed whether it is only a bit, or only two of the three bits (or only those three bits) (step S671). If only those bits are set, it is confirmed whether or not the operation signal is turned on from the error release switch 375 (step S672). When the operation signal is turned on, the error recovery time is set in the pre-error recovery timer (step S673). The error recovery time is the time from when the error release switch 375 is operated until the actual return from the error state to the normal state.

  If the operation signal from the error release switch 375 is not on, the value of the timer before error recovery is confirmed (step S674). If the value of the timer before error recovery is 0, that is, if the timer before error recovery is not set, the process proceeds to step S678. If the pre-error return timer is set, the value of the pre-error return timer is decremented by -1 (step S675). If the pre-error return timer value becomes 0 (step S676), the payout switch of the error flags is set. Bits of abnormality detection error 2, payout case error and prize ball REQ signal error are reset (step S677).

  As described above, since the error state (which is in the payout prohibition state as shown in step S621 in FIG. 46) is canceled based on the operation of the error cancel switch 375, the payout prohibition state is quickly canceled and the payout is performed. Processing can be activated.

  In step S678, the payout control CPU 371 checks the detection signal of the full switch 48. If the detection signal of the full tank switch 48 is output (if it is in the ON state), the full tank error bit in the error flag is set (step S679). If the detection signal of the full tank switch 48 is OFF, the full tank error bit is reset (step S680).

  Further, the payout control CPU 371 checks the detection signal of the ball break switch 187 (step S681). If the detection signal of the ball break switch 187 is output (if it is on), the ball break error bit in the error flag is set (step S682). If the detection signal of the ball break switch 187 is OFF, the ball break error bit is reset (step S683). When the ball break error bit is set, the bit corresponding to the ball break LED 52 in the output port buffer is set to a value corresponding to the lighting state in the display control process of step S759.

  Further, the payout control CPU 371 checks the state of the power supply confirmation signal from the main board 31 (step S685). If the power supply confirmation signal is not output (if it is in the off state), the main board unconnected error bit is set. Set (step S686). If the power confirmation signal is output (if it is in the on state), the main board unconnected error bit is reset (step S687).

  The payout control CPU 371 checks the value of the switch timer corresponding to the payout count switch 301 among the switch timers in which the state of the detection signal of each switch is set, and the value is the switch on maximum time (for example, “240 ”) (Step S688), the bit of the payout switch abnormality detection error 1 is set in the error flag (step S689). If the value of the switch timer corresponding to the payout count switch 301 is equal to or shorter than the switch-on maximum time, the payout switch abnormality detection error 1 bit is reset (step S690). Note that the value of each switch timer is incremented by 1 when the state of the input port to which the detection signal of each switch is input is switched on in the switch processing of step S751, and is cleared by 0 when it is off. Accordingly, the fact that the value of the switch timer corresponding to the payout count switch 301 has exceeded the maximum switch-on time means that the payout count switch 301 has been turned on beyond the maximum switch-on time. It is determined that the game ball is clogged at the disconnection of the count switch 301 or at the portion of the payout count switch 301.

  Also, the payout control CPU 371 resets both the ball lending operation flag and the winning ball operation flag when the value of the switch timer corresponding to the payout count switch 301 becomes a switch-on determination value (for example, “2”). If it is in the state, it is determined that the game ball has passed through the payout count switch 301 even though the payout operation is not in progress, and the bit of the payout switch abnormality detection error 2 in the error flag is set (step S693). If the ball lending operation flag or the winning ball operation flag is set, the bit of the payout switch abnormality detection error 2 is reset (step S694).

  Further, the payout control CPU 371 checks the input state of the VL signal from the card unit 50 (step S695). If the VL signal is not input (if it is in the off state), the prepaid card unit not yet in the error flag is displayed. A connection error bit is set (step S696). If the VL signal is input (if it is on), the prepaid card unit unconnected error bit is reset (step S697).

  In the display control process in step S759, notification by display (numerical value display) corresponding to the error bit in the error flag is performed by the error display LED 374. In this embodiment, the game control means mounted on the main board 31 and the payout control means mounted on the payout control board 37 perform bi-directional communication with respect to prize ball payout, but a communication error is indicated by an error display LED 374. Can be notified. As a communication error, a main board non-connection error due to the power supply confirmation signal from the main board 31 being turned off, and a prize ball REQ signal error in which the prize ball REQ signal is turned on or off at incorrect timing (steps S561 to S564 and However, when a communication error such as a main board unconnected error occurs, the firing motor 94 is disabled. That is, the game ball cannot be launched into the game area 7. Therefore, the game does not proceed despite the occurrence of a communication error such as a main board unconnected error.

  Further, since the communication error is detected on the payout control means side, even if the game control means and the payout control means perform bi-directional communication with respect to the prize ball payout, the communication without increasing the burden on the game control means. Can detect errors.

  In this embodiment, the main board non-connection error is automatically cleared when the power confirmation signal is turned on (see steps S685 and S687), but the error state is further determined on the condition that the error release switch 375 is operated. You may make it cancel.

  Further, in this embodiment, a communication error is reported in such a manner that a communication error with the card unit 50 (a prepaid card unit non-connection error and a prepaid card unit communication error) and other errors can be made special (see FIG. 51). . Therefore, a communication error between the game control unit and the payout control unit is easily identified.

  As described above, according to the configurations of the first and second embodiments, the external random number generation unit generates random numbers (counter values) for various determinations, and the monitoring circuits 934 and 935 operate according to the external random number generation unit. An abnormality relating to the update of the random number value is monitored, and the CPU 56 is configured to execute predetermined error processing based on the abnormality signal from the monitoring circuits 934 and 935 when the abnormality occurs, so that the external random number generating means Is operating normally, and if it is operating abnormally, appropriate control processing can be executed.

  The monitoring circuit 934 according to the first embodiment shown in FIGS. 8 and 9 is configured to monitor that a clock signal having a predetermined frequency from the oscillator 930 is not input to the counter IC 931. Thus, an abnormality such as a failure of the oscillator 930 can be reliably detected.

  The monitoring circuit 935 according to the second embodiment shown in FIGS. 21 and 22 is stored in the storage unit 935B that stores the counter value (random number value) counted by the counter IC 931 and the storage unit 935B this time. An abnormality determination circuit 935C that determines whether or not the counter value matches the previously stored counter value, and the abnormality determination circuit 935C continuously determines that the counter values match a predetermined number of times Therefore, an abnormality signal such as a failure of the counter IC 931 can be reliably detected.

  Further, according to the configuration of the third embodiment, when the random number value for various determinations is generated by the external random number generation means and the CPU 56 inputs the start detection signal from the start port switch 14a, the external random number is generated. The random value output by the means is stored in a predetermined area of the RAM 55, and it is determined whether or not the currently stored random number value matches the previously stored random value, and it is determined that the random number value matches. Since it is configured to execute predetermined error processing when it is determined consecutively, it is determined whether or not the external random number means is operating normally. Processing can be executed.

  Further, the CPU 56 is configured to perform a process for causing the notification means such as the variable display device 9 to notify that an abnormality relating to the update of the random number value has occurred as the error process. It is possible to easily recognize that an abnormality relating to updating has occurred.

  Further, since the CPU 56 is configured to perform a process for stopping the control related to the game as an error process, a new problem caused by the progress of the game in a state where an abnormality has occurred is generated. Can be prevented.

  In addition, since the CPU 56 is configured to stop the control related to the provision of the game value relating to the game in the error processing, it is possible to reliably prevent the game value from being imparted in the presence of the abnormality. it can.

  Further, when the monitoring circuits 934 and 935 and the CPU 56 determine whether or not the currently stored random number value matches the previously stored random number value, an abnormality relating to the update of the random number value reliably by simple processing. Can be detected. In addition, when the monitoring circuits 934 and 935 and the CPU 56 determine whether or not the random number stored this time matches the random number stored last time and the previous time, it is more reliably involved in updating the numerical data. Abnormality can be detected.

  Further, since the counter value as a random number value is used to determine whether a predetermined game value is given, the hardware configuration counter IC931 is different from the software configuration counter executed in the CPU 56 and is not synchronized with the control related to the game. The possibility that the illegal player will recognize the timing at which the counter value for giving the game value is generated is reduced.

  In addition, the CPU 56 may be configured to output a notification signal indicating that an abnormality has occurred in the external random number generation means to, for example, a hall computer outside the gaming machine. In this case, it is possible to automatically confirm that an abnormality has occurred in the gaming machine at a gaming store or the like, and it is possible to leave a record of the occurrence of such an abnormality.

  In the first to third embodiments, an update abnormality that the count by the counter IC 931 is stopped is monitored, and predetermined error processing is executed based on the occurrence of the update abnormality. That is, in the first embodiment, the monitoring circuit 934 monitors the stop of the count of the counter IC 931 by monitoring the abnormality of the clock signal from the transmitter 930, and in the second embodiment, the monitoring circuit 935 includes the counter 932 of the counter 932. The stop of the count of the counter IC 931 is monitored by monitoring the abnormality of the value. In the third embodiment, the count of the counter IC 931 is stopped by the CPU 56 monitoring the abnormality of the counter value output from the counter IC 931. Monitor. As a result, based on the detection of the stop of the counter IC 931 being detected, the CPU 56 executes a predetermined error process.

  However, the present invention is not limited to such a configuration, and the counter IC 931 may be configured to monitor whether the counter value is counted within a normal range (that is, 0 to 65535). For example, the monitoring circuit 935 or the CPU 56 (or a special monitoring circuit) always monitors whether or not the counter value counted by the counter IC 931 is within a normal range, and it is determined that the counter value is out of the normal range. Then, the CPU 56 may be configured to execute predetermined error processing. The counter IC 931 may be configured to monitor whether the counter value is counted only within a normal range but within a specific range (for example, within a range of 20000 to 29999). For example, a counter for monitoring the counter 932 is provided separately from the counter 932 for generating random numbers in the counter IC 931, and the counter value of the counter 932 for generating random numbers is compared with the counter value for monitoring by a comparator. The counter 932 for generating a random number may be configured to monitor whether or not it is counting only within a specific range.

  Note that the pachinko gaming machine 1 of each of the above embodiments mainly has a predetermined game value when the stop symbol of the special symbol variably displayed on the variable display device 9 based on the start winning is a combination of the predetermined symbols. The first type pachinko gaming machine that can be given to a player, but if there is a winning in a predetermined area of an electric accessory that is released based on a start winning, a second gaming value can be given to the player When a winning is given to a predetermined electric game that is released when a stop symbol of a symbol variably displayed based on a seed pachinko gaming machine or a start winning combination becomes a predetermined symbol combination, a predetermined right is generated or continued. The present invention can be applied even to a seed pachinko gaming machine.

Embodiment 4 FIG.
In each embodiment described above, a pachinko gaming machine is shown as an example of a gaming machine, but the present invention is not limited to a pachinko gaming machine and can be applied to other gaming machines. Hereinafter, an example in which the present invention is applied to a slot machine which is an example of another gaming machine will be described.

  FIG. 36 is a front view of the slot machine 500 as viewed from the front. As shown in FIG. 36, in the slot machine 500, a game panel 501 is detachably attached near the center. In addition, a variable display device 502 for variably displaying a plurality of types of symbols is provided near the center of the front surface of the game panel 501. In this embodiment, the variable display device 502 has three symbol display areas of “left”, “middle”, and “right”, and the symbol display reels 502a, 502b, and 502c correspond to the symbol display areas, respectively. Is provided.

  Below the game panel 501, an operation table 520 is provided in which various input switches and the like for the player to perform various operations are arranged. On the back side of the operation table 520, a BET switch 521 for betting (putting) coins one by one, and a MAXBET switch 522 for betting coins by the maximum number (three in this example) that can be placed in one game. A settlement switch 523 and a coin insertion slot 524 are provided. Coins inserted into the coin insertion slot 524 are detected by an inserted coin sensor (not shown).

  On the front side of the operation table 520, a start switch 525, a left reel stop switch 526a, a middle reel stop switch 526b, a right reel stop switch 526c, and a coin jam elimination switch 527 are provided. Lamps 528a and 528b are provided on the left and right sides of the operation table 520, respectively. A speaker 530 for outputting sound effects and the like is provided below the operation table 520.

  On the upper part of the game panel 501, an image display device (LCD: liquid crystal display device) 540 for notifying the player of a game method, a game state, and the like is provided. For example, when a winning occurs, an image in which a character performs a predetermined action is displayed on the image display device 540 to notify the player that a winning flag, which will be described later, is set. Two speakers 541L and 541R that emit sound effects are provided on the left and right of the image display device 540.

  The winning combinations generated in the slot machine 500 include a small winning combination, a replay winning, a big bonus winning, and a regular bonus winning. In the slot machine 500, random numbers are extracted at the timing when the start switch 525 is operated, and it is determined whether or not the winning of any winning combination is allowed. The fact that winnings are allowed is said to be “winning internally”. When the internal winning is made, a winning flag indicating that is set in the slot machine 500. In the game with the winning flag set, the reels 502a to 502c are controlled so that the winning combination corresponding to the winning flag can be drawn. On the other hand, in a game in which the winning flag is not set, the reels 502a to 502c are controlled so that no winning is generated.

Next, an outline of the game provided by the slot machine will be described.
For example, when a multiplier is set by inserting a coin from the coin insertion slot 524 and pressing the BET switch 521 or the MAXBET switch 522, the operation of the start switch 525 becomes effective. When the player operates the start switch 525, the symbol display reels 502a to 502c provided in the variable display device 502 start rotating. In addition, when a regular bonus prize or a big bonus prize is internally won at the timing when the start switch 525 is operated, for example, a screen on which a predetermined character performs a predetermined action is displayed on the image display device 540. Thus, the player or the like is notified that the internal winning is made.

  When a predetermined time elapses after the symbol display reels 502a to 502c start rotating, the operations of the reel stop switches 526a to 526c become effective. In this state, when the player presses one of the reel stop switches 526a to 526c, the rotation of the reel corresponding to the operated stop switch is stopped. When the symbol display reels 502a to 502c are left for a predetermined period or more without being stopped, the symbol display reels 502a to 502c are automatically stopped.

  When all the symbol display reels 502a to 502c are stopped, the symbol display reels 502a to 502c displayed on the variable display device 502 are determined according to the number of symbols in the upper, middle, and lower three symbols. Whether or not a prize is won is determined by a combination of symbols positioned on a valid winning line. When the multiplying number is 1, only the middle one horizontal winning line in the variable display device 502 is valid. When the multiplying number is 2, the three rows of winning lines in the upper, middle, and lower rows in the variable display device 502 are valid. When the number of multiplications is 3, a total of five pay lines of three horizontal rows and two diagonal diagonal lines in the variable display device 502 are effective lines.

  When a combination of symbols on the active line becomes a specific display mode determined in advance and a winning occurs, a predetermined game effect is made by sound, light, display on the image display device 540, etc. The game according to is started.

  FIG. 37 is a block diagram showing an example of a circuit configuration of a main board (game control board) 600 provided in the slot machine 500. FIG. 37 also shows an effect control board 630, a reel unit 650, an external random number generation means, and a monitoring circuit 934. Note that other substrates such as a power supply substrate and a relay substrate are also connected to the main substrate 600, but are not shown in FIG. The main board 600 includes a CPU 602 that performs a control operation according to a program, a RAM 603 that is an example of a storage unit used as a work memory, a ROM 604 that stores a game control program, and the like, and an I / O port unit 605. Yes.

  The external random number generation means generates a random number used for determination of internal winning or the like of bonus winning by a CPU (game control microcomputer) 602. The external random number generation means includes an oscillator (OSC) 930 as a clock signal generation means and a counter IC 931 as a numerical data update means, and is provided outside the CPU 602 as shown in FIG.

  The oscillator 930 generates a clock signal having a predetermined frequency (for example, 20 MHz). The clock signal generated by the oscillator 930 is input to the counter 932 of the counter IC 931. The counter IC 931 includes a counter 932 and a latch circuit 933. The counter 932 counts the clock signal generated by the oscillator 930. When detecting the detection signal from the start switch 525, the latch circuit 933 extracts and latches the counter value counted by the counter 932 at that time (for example, the rising edge of the detection signal).

  When the start switch 525 detects a switch operation by the player, the start switch 525 outputs a detection signal notifying that the rotation of each of the symbol display reels 502a to 502c has occurred to the latch circuit 933 of the counter IC 931 and via the I / O 605. It outputs to CPU602. When detecting the detection signal from the start switch 525, the CPU 602 reads the counter value latched by the latch circuit 933. The CPU 602 stores the read counter value in a predetermined area of the RAM 603.

  The internal configuration of the monitoring circuit 934 is the same as the configuration shown in FIG. The monitoring circuit 934 receives the clock signal generated by the oscillator 930 and counts the input clock signal. The monitoring circuit 934 stores the counter value in accordance with the time-up signal from the timer circuit 934D, and compares the counter value stored last time with the counter value stored this time. As a result of the comparison, the monitoring circuit 934 determines that an abnormality has occurred in the oscillator 930 if both counter values match, and if both counter values are different, the oscillator operates normally. It is determined that When the monitoring circuit 934 determines that an abnormality has occurred in the oscillator 930, the monitoring circuit 934 outputs an abnormality signal to notify the abnormality to the CPU 602. The CPU 602 executes error processing similar to that in the first embodiment based on the abnormal signal output from the monitoring circuit 934.

  It is possible that the counter value stored last time in the storage unit 934B matches the counter value stored this time even though no abnormality has occurred in the oscillator 930. Therefore, in order to more reliably determine the abnormality of the oscillator 930, the abnormality determination circuit 934C is configured to output an abnormality signal to the CPU 56 when it is determined that both counter values match continuously a predetermined number of times. Also good.

  It should be noted that the monitoring circuit 934 as shown in FIG. 37 can monitor the abnormality of the oscillator 930, and the monitoring circuit 935 as shown in FIG. is there. Also, a configuration for monitoring the abnormality of the oscillator 930 with the monitoring circuit 934 as shown in FIG. 37, and a configuration for monitoring the abnormality of the external random number generation means inside the CPU 602 without providing the monitoring circuit as shown in FIG. It is also possible to make it.

  In the reel unit 650, a reel motor 651, a reel lamp 652, and a reel sensor 653 are stored. The reel motor 651 is a motor for rotating the reels 502a to 502c. The reel lamp 652 is provided inside each of the reels 502a to 502c, and is a lamp for illuminating a symbol visually recognized by the variable display device 502 from the inside of the reel among symbols drawn on the reels 502a to 502c. . The reel sensor 653 is a sensor for sensing the rotation state, the number of rotations, and the like of each of the reels 502a to 502c.

  In this embodiment, the effect control means mounted on the effect control board 630 performs display control of the image display device 540 provided in the slot machine 500 and lighting control of the reel lamp 652. The image display device 540 displays various kinds of information such as a decorative pattern change display and a display for notifying a game state and a game method under the control of the effect control means. In this example, the effect control means mounted on the effect control board 630 includes a CPU or GCL for effect control. Therefore, the effect control means mounted on the effect control board 630 is configured to be able to execute a game effect by a moving image based on the moving image data, like the pachinko gaming machine described above. The effect control means mounted on the effect control board 630 includes lighting control of various game effect lamps 550, 551, 552, and 553 provided in the slot machine 500 and a speaker provided in the slot machine 500. Sound output control of 501, 541 L, 541 R is performed.

  In this example, the effect control board 630 controls the image display device 540, the game effect lamp 550, the speaker 530, and the like according to the effect pattern based on the control command received from the main board 600. In the image display device 540, the decorative symbols are displayed in a variable manner according to a predetermined image display pattern (an example of an effect pattern). In the decorative symbol variation display effect, for example, a symbol combination effect display such as a special symbol variation display in a pachinko machine, or a symbol combination effect such as a reel 502a to 502c variation display is performed. Which effect pattern is used from among a plurality of effect patterns provided in advance is determined by the CPU 602 at the timing when the start switch 525 is operated, for example.

  In the slot machine 500 described above, effects such as moving images based on the moving image data are performed. For example, during a normal game period in which a prize is not awarded, a regular bonus game is performed by a regular bonus winning. It may be executed during a period during which a big bonus game by big bonus winning is being performed.

  As described above, the present invention can be applied to a slot machine, and the effects of the above-described embodiments can be obtained even when the present invention is applied to a slot machine.

It is the front view which looked at the pachinko game machine from the front. It is a front view which shows the front surface of the game board in the state which removed the glass door frame. It is the rear view which looked at the gaming machine from the back. It is the rear view which looked at the mechanism board to which various members were attached from the game machine back side. It is a block diagram which shows the circuit structural example of a game control board (main board). It is a block diagram which shows the circuit structural example of a payout control board. FIG. 4 is a block diagram illustrating a configuration example of an effect control board, a lamp driver board, and an audio output board. 1 is a block diagram showing a configuration of a first embodiment of a CPU, a reset circuit, a power supply monitoring circuit, an external random number generator, and a monitoring circuit on a main board. FIG. 3 is a block diagram illustrating an internal configuration of a monitoring circuit according to the first embodiment. It is a flowchart which shows the main process which CPU in a main board | substrate performs. It is a flowchart which shows a timer interruption process. It is explanatory drawing which shows each random number. It is a flowchart which shows a special symbol process process. It is a flowchart which shows a starting port switch passage process. It is a flowchart which shows a special symbol normal process. It is a flowchart which shows a special symbol stop symbol setting process. It is a flowchart which shows the error process by a game control means. It is a flowchart which shows the process example of a command creation process. It is a flowchart which shows a command transmission process routine It is explanatory drawing which shows the example of an error display by a variable display apparatus. It is a block diagram which shows the structure of Embodiment 2 of CPU, a reset circuit, a power supply monitoring circuit, an external random number generation means, and a monitoring circuit in a main board. FIG. 6 is a block diagram illustrating an internal configuration of a monitoring circuit according to a second embodiment. It is a block diagram which shows the structure of Embodiment 3 of CPU, a reset circuit, a power supply monitoring circuit, and an external random number generation means in a main board. It is a flowchart which shows the error processing of Embodiment 3 by a game control means. It is explanatory drawing which shows an example of the content of a control signal. It is a block diagram which shows the signal wire | line etc. which are used for transmission / reception of a control signal. It is a flowchart which shows the main process which CPU for payout control performs. It is a flowchart which shows the timer interruption process which CPU for payout control performs. It is a flowchart which shows a discharge motor control process. It is a flowchart which shows payout control processing. It is a flowchart which shows the payout start waiting process. It is a flowchart which shows a payout motor stop waiting process. It is a flowchart which shows payout passage waiting processing. It is a flowchart which shows the error process by the payout control means. It is a flowchart which shows the error process by the payout control means. It is the front view which looked at the lot machine from the front. It is a block diagram which shows an example of the circuit structure of the main board | substrate with which a slot machine is equipped.

Explanation of symbols

1 Pachinko machine 9 Variable display device 14a Start port switch 27 Speaker 31 Main board 35 Lamp driver board 37 Dispensing control board 55,603 RAM
56,602 CPU
70 Audio output board 80 Production control board 101 Production control CPU
371 CPU for payout control
500 slot machine 525 start switch 930 oscillator 931 counter IC
934, 935 monitoring circuit

Claims (1)

A gaming machine in which a player plays a predetermined game and can give a predetermined game value to the player in accordance with establishment of a predetermined condition,
A game control microcomputer for controlling the progress of the game;
Clock signal generating means for generating a clock signal of a predetermined frequency;
Numeric data updating means provided separately from the game control microcomputer, and based on the clock signal, updates numeric data used for control related to the game in the game control microcomputer;
Monitoring means for monitoring whether updating of the numerical data is stopped,
The monitoring means outputs an update abnormality signal for notifying the microcomputer for game control of an update abnormality that the updating of the numerical data is stopped when the updating of the numerical data is stopped. Gaming machine.

Images