JP2008192763A - Capacity cell and semiconductor integrated circuit with the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a bypass capacitor which can be reduced in noise in an I/O cell region, and to provide a semiconductor integrated circuit equipped with the same. <P>SOLUTION: The bypass capacitor 1 has an I/O capacity portion 21 formed in the I/O cell region 3 in the periphery of a substrate 45, I/O capacity cell a1 which is electrically connected to the I/O capacity portion 21 and is extended to the boundary of a core region 5 surrounded by the I/O cell region 3 and includes a pair of terminal portions 39 which face each other via an interlayer insulation film, a pair of connection interconnection portions 41 connected to the pair of terminal portions 39 of the I/O capacity cell a1, core capacity cell b10 including a core capacity portion 33 which is connected to the pair of connection interconnection portions 41 and is formed in the core region 5, and core capacity cells b11-b42 connected to the core capacity cell b10. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a capacity cell and a semiconductor integrated circuit including the capacity cell, and more particularly to a capacity cell provided in a core region of a semiconductor substrate.

  In recent large-scale integrated circuits (LSIs), there is an increasing demand for low noise. For this reason, the LSI has to ensure a larger capacity between the power supply wiring to which the drive power supply potential is applied and the ground (GND). In particular, an I / O cell used for an interface with an external circuit needs to have a very low noise performance compared to an internal logic cell.

  When the power supply potential for operating the I / O cell is different from the power supply potential for operating the internal logic cell, the power supply wiring for the I / O cell and between the GND in the I / O cell region where the I / O cell is arranged A sufficient capacity value must be secured. However, since the area of the I / O cell region that can be arranged inside the LSI is limited, the area in which the bypass capacitor can be arranged is also limited. For this reason, it is difficult to satisfy the low noise requirement required for recent LSIs only by the capacitance value of the bypass capacitor. Therefore, the core region for forming the internal logic cell is used as a region for forming a bypass capacitor for the I / O cell.

FIG. 3 is a diagram schematically showing a schematic configuration of a conventional LSI, and is a plan view showing the vicinity of the boundary between the I / O cell region and the core region when viewed in the normal direction of the substrate surface.
As shown in FIG. 3, the LSI includes an I / O cell region 3 disposed on the outer periphery of the semiconductor substrate and a core region 5 surrounded by the I / O cell region 3. In the I / O cell region 3, a plurality of I / O cells 10 and a plurality of I / O capacity cells 51 arranged adjacent to the I / O cell 10 are arranged. On the I / O cell region 3, a power supply ring 4 for applying a power supply voltage to the I / O cell region 3 and a reference potential ring for applying a reference potential (GND potential) to the I / O cell region 3. 2, a power supply ring 8 for applying a power supply voltage to the core region 5, and a reference potential ring 6 for applying a reference potential to the core region 5 are arranged. Each ring 2, 4, 6, 8 is wired across the I / O cell 10 and the I / O capacity cell 51. The I / O capacity cell 51 is electrically connected between the rings 2 and 4 so as to capacitively couple the power supply ring 4 and the reference potential ring 2. Thereby, the I / O capacity cell 51 functions as a bypass capacitor of the I / O cell region 3.

  In the core region 5, an internal logic cell 20 and main power supply wirings 12 and 14 for applying a power supply potential and a reference potential to the internal logic cell 20 are formed. Further, a plurality of core capacity cells 53a, 53b, 53c are arranged in the core region 5. The core capacity cells 53a, 53b, and 53c are arranged in an empty space in the core region 5 where the internal logic cell 20 or the like is not formed.

  The core capacity cells 53a, 53b, and 53c have an upper electrode 59, a lower electrode 55, and an insulating film (not shown) sandwiched between the electrodes 55 and 59, respectively. The upper electrodes 59 of the core capacity cells 53a, 53b, and 53c are connected to the common wiring 63, respectively. The common wiring 63 is connected to the lead wiring 61 drawn from the I / O cell region 3. The lead wiring 61 is connected to the power supply ring 4. The lower electrodes 55 of the core capacity cells 53a, 53b, and 53c are connected to the common wiring 67, respectively. The common wiring 67 is connected to the lead wiring 65 drawn from the I / O cell region 3. The lead wiring 65 is connected to the reference potential ring 2. Since the core capacity cells 53a, 53b, and 53c are capacitively coupled between the power supply ring 4 and the reference potential ring 2, they function as bypass capacitors for the I / O cell region 3.

In the conventional LSI shown in FIG. 3, in addition to the I / O capacity cell 51 arranged in the I / O cell area 3, the core capacity cells 53a, 53b, and 53c are arranged in the empty space of the core area 5. An increase in the capacitance value is attempted.
JP-A-7-106521 JP 2002-246548 A JP-A-11-204766 Japanese Patent Laid-Open No. 5-48020

  The core capacity cells 53a, 53b, and 53c are arranged in the core region 5 in order to reduce noise generated in the LSI to an allowable value or less. However, the core capacity cells 53a, 53b, and 53c have the same shape as the capacitor used in the internal logic cell 20, for example, and the shape is fixed. For this reason, as shown in FIG. 3, the core capacity cells 53 a, 53 b, and 53 c can be spread only in one direction in the core region 5. For this reason, the empty space in the core area 5 is not used to the maximum extent as an arrangement area for the core capacity cells 53a, 53b, 53c. Therefore, it is difficult to sufficiently increase the capacitance value of the bypass capacitor in the I / O cell region 3. Furthermore, in order to connect the core capacity cells 53 a, 53 b, 53 c to the power supply ring 4 and the reference potential ring 2, lead wires 61, 65 must be wired in the I / O cell region 3. The lead wirings 61 and 65 are wired in a region where the I / O capacity cell 51 is to be originally arranged. For this reason, since the total number of I / O cell capacities 51 in the I / O cell region 3 decreases, the capacity value of the I / O capacity cell 51 formed in the I / O cell region 3 decreases. There is. Therefore, the conventional bypass capacitor cannot sufficiently reduce the noise generated in the power supply ring 4 and the reference potential ring 2, and it is difficult to sufficiently improve the noise resistance performance of the LSI.

  An object of the present invention is to provide a bypass capacitor capable of reducing noise in the I / O cell region and a semiconductor integrated circuit including the same.

  The above object is provided in a core region on a semiconductor substrate in a region where a logic cell is not formed, a lower electrode formed on the semiconductor substrate, an insulating layer formed on the lower electrode, and the insulating layer This is achieved by a capacity cell comprising an upper electrode having an arbitrary shape formed thereon.

  Further, the above object is achieved by a semiconductor integrated circuit having the capacity cell of the present invention.

  According to the present invention, it is possible to reduce the noise of a semiconductor integrated circuit.

  A semiconductor integrated circuit including a bypass capacitor according to an embodiment of the present invention will be described with reference to FIGS. A schematic configuration of the bypass capacitor according to the present embodiment will be described with reference to FIGS. FIG. 1 shows a semiconductor integrated circuit including a bypass capacitor 1 according to the present embodiment, and shows the vicinity of the boundary between the I / O cell region 3 and the core region 5 when viewed in the normal direction of the substrate surface of the semiconductor integrated circuit. It is a top view shown typically. In FIG. 1, for easy understanding, a part of the I / O capacity cell a1, the part of the I / O cell 10 and the part of the core capacity cell b10 which are not on the same plane are indicated by broken lines, and are integrated. I / O capacity cell a1 and core capacity cells (capacity cells) b10, b11, b12, b21, b22, b31, b32, b41, b42 (hereinafter referred to as “core capacity cells b10 to b42”) In order to facilitate understanding, each boundary is indicated by a solid line. FIG. 2 is a cross-sectional view of the vicinity of the boundary between the I / O cell region 3 and the core region 5 cut in a direction perpendicular to the substrate surface. 2A shows a cross section cut along a virtual straight line AA shown in FIG. 1, and FIG. 2B shows a cross section cut along a virtual straight line BB shown in FIG. In FIG. 2, the boundary between the core capacity cells b <b> 10 and b <b> 11 that are integrally formed and continuous is indicated by a broken line in order to facilitate understanding.

  As shown in FIGS. 1 and 2, the bypass capacitor 1 is electrically connected to the I / O capacitor portion 21 formed in the I / O cell region 3 on the outer periphery of the semiconductor substrate 45 and the I / O capacitor portion 21. The I / O capacity cell a1 is formed to extend to the boundary of the core region 5 surrounded by the I / O cell region 3 and includes a pair of terminal portions 39 facing each other through an interlayer insulating film (not shown). And have. The I / O capacity cell a1 is disposed adjacent to the I / O cell 10 formed in the I / O cell region 3. In the I / O cell region 3, a plurality of I / O cells 10 and an I / O capacity cell a1 are arranged. On the I / O cell region 3, a power supply ring 4 for applying a power supply voltage to the I / O cell region 3 and a reference potential ring for applying a reference potential (GND potential) to the I / O cell region 3. 2, a power supply ring 8 for applying a power supply voltage to the core region 5, and a reference potential ring 6 for applying a GND potential to the core region 5 are arranged. Each ring 2, 4, 6, 8 is wired across the I / O cell 10 and the I / O capacity cell a1.

  As shown in FIG. 2A, the first terminal portion 7 that is one of the pair of terminal portions 39 is connected to the power supply ring 4, and the second terminal portion 9 that is the other of the pair of terminal portions 39 is the reference potential ring. 2 is connected. The first and second terminal portions 7 and 9 are insulated by an interlayer insulating film (not shown). Between the power supply ring 4 and the first terminal portion 7, for example, an intermediate power supply wiring 24 formed in the same layer as the power supply ring 8 and the reference potential ring 6 is wired. The intermediate power supply wiring 24 is connected to the power supply ring 4 through the interlayer electrode 13a. The intermediate power supply wiring 24 is connected to the first terminal portion 7 through the interlayer electrode 13b. The first terminal portion 7 is connected to the power supply ring 4 via the interlayer electrode 13b, the intermediate power supply wiring 24, and the interlayer electrode 13a. Insulating layers (not shown) are formed between the power supply ring 4 and the intermediate power supply wiring 24 and between the intermediate power supply wiring 24 and the first terminal portion 7, respectively. The interlayer electrodes 13a and 13b are formed by being buried in contact holes (not shown) formed in the insulating layer.

  Between the reference potential ring 2 and the second terminal portion 9, for example, an intermediate reference potential wiring 22 formed in the same layer as the power supply ring 8 and the reference potential ring 6 is wired. The intermediate reference potential wiring 22 is connected to the reference potential ring 2 through the interlayer electrode 11a. The intermediate reference potential wiring 22 is connected to the second terminal portion 9 through the interlayer electrode 11b. The second terminal portion 9 is connected to the reference potential ring 2 via the interlayer electrode 11b, the intermediate reference potential wiring 22 and the interlayer electrode 11a. Insulating layers (not shown) are respectively formed between the reference potential ring 2 and the intermediate reference potential wiring 22 and between the intermediate reference potential wiring 22 and the second terminal portion 9. The interlayer electrodes 11a and 11b are formed by being buried in contact holes (not shown) formed in the insulating layer.

  The I / O capacitor unit 21 includes a first electrode 15 electrically connected to the first terminal unit 7, a second electrode 19 connected to the second terminal unit 9, and first and second electrodes 15 and 19. And an insulating film 17 sandwiched between them. The second electrode 19 is a well region formed on the substrate 45, for example. An insulating film 17 is formed on the second electrode 19, which is a well region, a first electrode 15 is formed on the insulating film 17, and an insulating layer (not shown) is formed on the first electrode 15. The first electrode 15 is insulated from the second terminal portion 9 by the insulating layer. The first electrode 15 is connected to the first terminal portion 7 via the interlayer electrode 13c. The interlayer electrode 13c includes a contact hole (not shown) formed in the interlayer insulating film between the first and second terminal portions 7 and 9, a contact hole CH1 formed in the second terminal portion 9, and a second terminal. It is embedded in a contact hole (not shown) formed in the insulating layer between the portion 9 and the first electrode 15.

  The second electrode 19 is connected to the second terminal portion 9 via the interlayer electrode 11c. The interlayer electrode 11 c is formed by being buried in a contact hole (not shown) formed in the insulating layer between the second terminal portion 9 and the second electrode 19.

  The I / O capacitor unit 21 configured as described above is electrically connected between the rings 2 and 4 so as to capacitively couple the power supply ring 4 and the reference potential ring 2. Therefore, the I / O capacity cell a1 functions as a bypass capacitor of the I / O cell region 3.

  As shown in FIG. 1, an internal logic cell 20 and basic power supply wirings 12 and 14 for applying a power supply potential and a reference potential to the internal logic cell 20 are formed in the core region 5. The bypass capacitor 1 further includes core capacity cells b <b> 10 to b <b> 42 formed in the core region 5. The core capacity cells b10 to b42 are arranged in an empty space in the core region 5 where the internal logic cell 20 or the like is not formed. Since the core capacity cells b10 to b42 have the same structure, these structures will be described below by taking the core capacity cell b10 as an example.

  As shown in FIGS. 1 and 2, the core capacity cell b10 is connected to a pair of connection wiring portions 41 connected to a pair of terminal portions 39 of the I / O capacity cell a1 and a pair of connection wiring portions 41. And a core capacitor 33 formed in the core region 5. As shown in FIG. 2A, the first connection wiring portion 23, which is one of the pair of connection wiring portions 41, is formed in the same layer as the first terminal portion 7 and is connected to the first terminal portion 7. The second connection wiring portion 25, which is the other of the pair of connection wiring portions 41, is formed in the same layer as the second terminal portion 9 and is connected to the second terminal portion 9. The first and second connection wiring portions 23 and 25 are disposed to face each other via an interlayer insulating film (not shown). The first and second connection wiring portions 23 and 25 are insulated by the interlayer insulating film.

  As shown in FIGS. 2A and 2B, the core capacitor portion 33 is electrically connected to the upper electrode 27 electrically connected to the first connection wiring portion 23 and the second connection wiring portion 25. The connected lower electrode 31 and the insulating film 29 sandwiched between the upper electrode 27 and the lower electrode 31 are provided. The lower electrode 31 is a well region formed in the substrate 45, for example. For example, the upper electrode 27 is formed in the same layer as the first electrode 15, the insulating film 29 is formed in the same layer as the insulating film 17, and the lower electrode 31 is formed in the same layer as the second electrode 19. As shown in FIG. 1, when viewed in the normal direction of the substrate surface of the substrate 45, the first connection wiring portion 23 has a square shape with four corners missing, and the second connection wiring portion 25 has a square shape with four corners similarly missing. It has a shape.

  As shown in FIG. 1 and FIG. 2A, an insulating film 29 is formed on the lower electrode 31 that is a well region, an upper electrode 27 is formed on the insulating film 29, and not on the upper electrode 27. The illustrated insulating layer is formed. The upper electrode 27 is insulated from the second connection wiring portion 25 by the insulating layer. The upper electrode 27 is connected to the first connection wiring portion 23 via the interlayer electrode 35. The interlayer electrode 35 is disposed substantially at the center of the upper electrode 27. The interlayer electrode 35 includes a contact hole (not shown) formed in the interlayer insulating film between the first and second connection wiring portions 23 and 25, a contact hole CH 2 formed in the second connection wiring portion 25, It is embedded in a contact hole (not shown) formed in the insulating layer between the two connection wiring part 25 and the upper electrode 27.

  As shown in FIGS. 1 and 2B, the lower electrode 31 is connected to the second connection wiring portion 25 through the interlayer electrode 37. The interlayer electrode 37 is disposed at each corner of the lower electrode 31. The interlayer electrode 37 is formed by being embedded in a contact hole (not shown) formed in the insulating layer between the second connection wiring portion 25 and the lower electrode 31.

  The core capacitor 33 configured as described above is electrically connected between the rings 2 and 4 so as to capacitively couple the power supply ring 4 and the reference potential ring 2 via the I / O capacitor cell a1. Is done. Accordingly, the core capacity cell b10 functions as a bypass capacitor of the I / O cell region 3.

  The core capacity cells b11, b12, b31, b32, b41, b42 (hereinafter referred to as “core capacity cells b11 to b42”) have the same configuration as the core capacity cell b10. As shown in FIG. 1, the adjacent core capacity cells b <b> 10 to b <b> 42 are connected to each other by a pair of connection wiring portions 41. For example, the core capacity cell b <b> 11 is connected to the core capacity cells b <b> 10, b <b> 12, b <b> 21 arranged adjacent to each other by a pair of connection wiring portions 41. As a result, the core capacity unit 33 of the core capacity cells b11 to b42 is coupled to both the ring 2 so as to capacitively couple the power supply ring 4 and the reference potential ring 2 via the core capacity cell b10 and the I / O capacity cell a1. 4 are electrically connected. Accordingly, the core capacity cells b11 to b42 also function as bypass capacitors in the I / O cell region 3 in the same manner.

  The I / O capacity cell a <b> 1 has a pair of terminal portions 39 that extend to the boundary between the I / O cell region 3 and the core region 5. For this reason, the bypass capacitor 1 according to the present embodiment needs to be extended from the power supply ring 4 and the reference potential ring 2 in the I / O cell region 3 to the empty space in the core region 5 as in the conventional LSI. Absent. Thereby, the bypass capacitor 1 does not need to remove the I / O capacity cell 51 in order to route the lead wires 61 and 65 as in the conventional LSI. Therefore, the semiconductor integrated circuit including the bypass capacitor 1 according to the present embodiment can increase the capacitance value of the bypass capacitor for the I / O cell region 3 as compared with the conventional LSI.

  The core capacity cells b10 to b42 are arranged in an empty space generated when the arrangement of the internal logic cell 20 (macro cell) and the wiring of the main power supply wirings 12 and 14 are completed in the layout design stage. The core capacity cells b10 to b42 have a pair of connection wiring portions 41 that can be directly connected to the pair of terminal portions 39 of the I / O capacity cell a1. Therefore, for example, the core capacity cell b10 among the core capacity cells b10 to b42 can be disposed adjacent to the I / O capacity cell a1 at the boundary between the I / O cell region 3 and the core region 5. As described above, in the semiconductor integrated circuit according to the present embodiment, the core capacitor cell b10 is directly connected to the I / O capacitor cell a1 without using the lead wires 61 and 65 and the common wires 63 and 67 as in the conventional LSI. Therefore, the core capacity cell b10 can be used as a bypass capacitor for the I / O cell region 3.

  The core capacity cells b <b> 10 to b <b> 42 can be connected to each other on each of the outer peripheral sides of the pair of connection wiring portions 41. For this reason, the core capacity cells b10 to b42 can be arranged adjacent to each other in any direction. For this reason, the core capacity cells b10 to b42 can be arranged adjacent to each other so as to be laid out in an empty space surrounded by the already arranged internal logic cells 20, the main power supply wirings 12, 14 and the like. The core capacitor cells b10 to b42 may be arranged just before contacting the internal logic cell 20 or the like in the layout design stage of the semiconductor integrated circuit.

  Since the pair of terminal portions 39 have a wider wiring width than the conventional LSI lead-out wirings 61 and 65, the resistance value of the wiring can be reduced. Further, for example, the I / O capacity cell a1 shown in the lowermost part of FIG. 1 has a core capacity by further disposing another core capacity cell between the I / O capacity cell 1a and the core capacity cell b41. It can be connected to the cell b41. Thereby, since the two I / O capacity cells a1 are connected to the core capacity cells b10 to b42, the resistance value between the core capacity cells b10 to b42 and the power supply ring 4 and the reference potential ring 2 can be lowered. .

  As shown in FIGS. 2A and 2B, the core capacity cells b10 to b42 are used only up to the second layer of the wiring layer. For this reason, when the wiring layer of the main power supply wirings 12 and 14 is the third layer or more, the core capacity cell can be arranged also under the main power supply wirings 12 and 14 of the third layer or more. In addition, the core capacity cell can be arranged below a signal wiring (not shown) using a third or higher wiring layer. Similarly, since the I / O capacity cell a1 is used only up to the second layer of the wiring layer, it can also be arranged below the signal wiring (not shown) using the third and higher wiring layers. . In this way, the bypass capacitor 1 can be spread down to the lower layers of the signal wiring, power supply wiring, and internal logic cell 20 of three layers or more. Thereby, since the capacitance value of the bypass capacitor 1 can be increased, the semiconductor integrated circuit can reduce noise generated in the I / O cell region 3.

  Further, the I / O capacity cell a1 can be arranged in all the empty spaces in the I / O cell area 3 where the I / O cell 10 is not arranged. As a result, the bypass capacitor 1 can sufficiently secure a capacitance value between the power supply ring 4 and the reference potential ring 2. As a result, the semiconductor integrated circuit can meet the demand for low noise.

  As described above, according to the present embodiment, the bypass capacitor 1 does not need to be provided with the lead wires 61 and 65 in the I / O cell region 3 as in the prior art. Further, according to the present embodiment, the I / O capacity cell a1 and the core capacity cell b10 are merely arranged adjacent to each other and connected, and function as a bypass capacitor in the I / O cell region 3. Furthermore, the plurality of core capacity cells can be repeatedly arranged adjacent to each other in any direction, up, down, left, and right. For this reason, the core capacity cell is disposed in the empty space of the core region 5 without waste. Thereby, the bypass capacitor 1 can ensure a very large capacitance value compared with the conventional bypass capacitor. Therefore, the bypass capacitor 1 has a very high effect in reducing noise in the I / O cell region 3. Thereby, the semiconductor integrated circuit including the bypass capacitor 1 can improve the noise resistance performance.

  Further, the bypass capacitor 1 can be connected to the power supply ring 4 and the reference potential ring 2 with a sufficient wiring width. For this reason, the impedance between the bypass capacitor 1 and the power supply ring 4 and the reference potential ring 2 can be lowered. Thereby, the bypass capacitor 1 can further enhance the noise reduction effect of the semiconductor integrated circuit.

The bypass capacitor and the semiconductor integrated circuit including the bypass capacitor according to the present embodiment described above are summarized as follows.
(Appendix 1)
In the core region on the semiconductor substrate, provided in the region where the logic cell is not formed, the lower electrode formed on the semiconductor substrate,
An insulating layer formed on the lower electrode;
A capacity cell comprising: an upper electrode having an arbitrary shape formed on the insulating layer.
(Appendix 2)
The capacity cell according to attachment 1, wherein
The capacitor cell according to claim 1, wherein the lower electrode is a well region formed in the semiconductor substrate.
(Appendix 3)
The capacity cell according to appendix 1 or 2,
The upper electrode is formed in the core region and is electrically connected to an I / O capacitor cell having a pair of terminal portions via a wiring.
(Appendix 4)
The capacity cell according to attachment 3, wherein
A first electrode of the I / O capacity cell is electrically connected to a reference potential ring provided around the semiconductor substrate;
The capacity cell, wherein the second electrode of the I / O capacity cell is electrically connected to a power supply ring provided around the semiconductor substrate.
(Appendix 5)
A semiconductor integrated circuit comprising the capacity cell according to any one of appendices 1 to 4.
(Appendix 6)
A substrate on which a semiconductor layer is formed;
The I / O capacitor portion formed in the I / O cell region on the outer periphery of the substrate and the core region connected to the I / O capacitor portion and extending to the boundary of the core region surrounded by the I / O cell region. And a I / O capacitor cell having a pair of terminal portions facing each other with an interlayer insulating film interposed therebetween.
(Appendix 7)
In the bypass capacitor described in Appendix 6,
The I / O capacitor portion includes a first electrode connected to the one of the pair of terminal portions, a second electrode connected to the other of the pair of terminal portions, and the first and second electrodes. A bypass capacitor having an insulating film sandwiched therebetween.
(Appendix 8)
In the bypass capacitor described in Appendix 7,
The bypass capacitor, wherein the second electrode is a well region formed in the substrate.
(Appendix 9)
In the bypass capacitor according to any one of appendices 6 to 8,
A core capacity cell further comprising: a pair of connection wiring portions connected to the pair of terminal portions; and a core capacity portion connected to the pair of connection wiring portions and formed in the core region. Bypass capacitor.
(Appendix 10)
In the bypass capacitor described in appendix 9,
A plurality of the core capacity cells;
The bypass capacitor, wherein the core capacity cells arranged adjacent to each other are connected to each other by the pair of connection wiring portions.
(Appendix 11)
A semiconductor integrated circuit comprising the bypass capacitor according to any one of appendices 6 to 10.

1 is a plan view schematically showing a schematic configuration of a bypass capacitor 1 according to an embodiment of the present invention. It is sectional drawing which shows typically schematic structure of the bypass capacitor 1 by one embodiment of this invention. It is a top view which shows typically schematic structure of the conventional bypass capacitor.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Bypass capacitor 2, 6 Reference potential ring 3 I / O cell area | region 4, 8 Power supply ring 7 1st terminal part 9 2nd terminal part 10 I / O cell 11a, 11b, 11c, 13a, 13b, 13c, 35, 37 Interlayer electrodes 12, 14 Core power supply wiring 15 First electrode 17, 29 Insulating film 19 Second electrode 20 Internal logic cell 21 I / O capacitor portion 23 First connection wiring portion 25 Second connection wiring portion 27, 59 Upper electrode 31, 55 Lower electrode 33 Core capacity part 39 A pair of terminal part 41 A pair of connection wiring part 51, a1 I / O capacity cell 53a, 53b, 53c, b10-b42 Core capacity cell 61, 65 Lead wiring 63, 67 Common wiring

Claims (5)

In the core region on the semiconductor substrate, provided in the region where the logic cell is not formed, the lower electrode formed on the semiconductor substrate,
An insulating layer formed on the lower electrode;
A capacity cell comprising: an upper electrode having an arbitrary shape formed on the insulating layer. The capacity cell of claim 1,
The capacitor cell according to claim 1, wherein the lower electrode is a well region formed in the semiconductor substrate. The capacity cell according to claim 1 or 2,
The upper electrode is formed in the core region and is electrically connected to an I / O capacitor cell having a pair of terminal portions via a wiring. The capacity cell according to claim 3, wherein
A first electrode of the I / O capacity cell is electrically connected to a reference potential ring provided around the semiconductor substrate;
The capacity cell, wherein the second electrode of the I / O capacity cell is electrically connected to a power supply ring provided around the semiconductor substrate. A semiconductor integrated circuit comprising the capacity cell according to claim 1.

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