JP2010087336A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit that efficiently removes noise without making wiring efficiency worse. <P>SOLUTION: A standard cell 10 has a logic circuit region 10a and a capacity region 10b, one power supply wiring 22 and two grounding wirings 20 and 21 (or two power supply wirings and one ground wiring) belonging to the same wiring layer are connected to the standard cell 10, and a MOS capacitor 17 is connected between the power supply wiring 22 and the ground wiring 21 of the same wiring layer in the capacity region 10b. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having a capacity for removing noise generated in a logic circuit.

  In a semiconductor integrated circuit having a plurality of circuit blocks (hereinafter referred to as cells), a capacitor connected between a power supply wiring and a ground wiring in order to remove noise (operation noise and power supply noise) generated in a logic circuit. Is used.

Conventionally, such a capacitor has been arranged in a region where a logic circuit of a semiconductor integrated circuit is not formed (for example, a main power supply wiring region).
However, in order to form a capacitor having a sufficient capacitance value, it is necessary to widen a region where a logic circuit is not formed, resulting in an increase in the area of the semiconductor integrated circuit.

Therefore, a semiconductor integrated circuit is known in which a capacitor is arranged in each cell of the standard cell to remove power supply noise (see, for example, Patent Document 1).
JP 2003-224195 A

  However, in the conventional technique for forming a capacitor in the cell, the capacitors are connected using a plurality of different metal layers in the cell, so that it is difficult to arrange signal wiring and the wiring efficiency in the cell is deteriorated. There was a problem.

  In view of the above points, the present inventors have an object to provide a semiconductor integrated circuit capable of efficiently removing noise without deteriorating wiring efficiency.

  In order to achieve the above object, the following semiconductor integrated circuit is provided. This semiconductor integrated circuit has a plurality of cells each having a logic circuit region and a capacitor region, and the cells belong to the same wiring layer and include two power supply wires and one ground wire, or one A power supply line and two ground lines are connected. In the capacity region, a capacitor is connected between the power supply line and the ground line in the same wiring layer.

  Noise generated in the logic circuit area can be efficiently removed without deteriorating the wiring efficiency.

Hereinafter, the present embodiment will be described in detail with reference to the drawings.
FIG. 1 is a top view of the main part of the semiconductor integrated circuit according to the first embodiment.
2 is a cross-sectional view taken along line AB in FIG.

  In the top view of FIG. 1, the configuration up to the first metal layer is illustrated, and the components below the first metal wiring layer are indicated by dotted lines. The same applies to each top view described later in this specification.

The semiconductor integrated circuit of the first embodiment has a plurality of cells (hereinafter referred to as standard cells 10).
Each standard cell 10 has a logic circuit region 10a and a noise removal capacitor region 10b.

As shown in FIG. 2, a plurality of diffusion layers 12 are formed in the semiconductor substrate 11 in order to achieve electrical connection from the upper layer and stabilize the well potential of the semiconductor substrate 11.
FIG. 1 shows an example in which a 2-input NOR circuit is configured as an example of the logic circuit region 10a.

  In the logic circuit region 10 a, an n-channel MOSFET (Metal-Oxide Semiconductor Field Effect Transistor) region (hereinafter abbreviated as nMOS region) 13 and a p-channel MOSFET region (hereinafter abbreviated as pMOS region) 14 are formed on a semiconductor substrate 11. Yes. Two gate electrodes 15 and 16 (for example, polysilicon) are formed so as to straddle the nMOS region 13 and the pMOS region 14.

  The capacitor region 10 b has a MOS capacitor 17. The MOS capacitor 17 has, for example, a structure having a diffusion layer 17a formed on the semiconductor substrate 11, a silicon oxide film 17b formed on the diffusion layer 17a, and a polysilicon 17c formed on the silicon oxide film 17b as an upper electrode. .

  An interlayer insulating film 18 is further formed on the semiconductor substrate 11 having the above-described structure (not shown in FIG. 1). A plurality of vias 19 are formed in the interlayer insulating film 18 to electrically connect the wiring layer of the first metal layer to the diffusion layers 12 and 17a, the gate electrodes 15 and 16 and the MOS capacitor 17 described above. Yes.

The standard cell 10 according to the present embodiment has two ground wirings 20 and 21, a power supply wiring 22, and a plurality of signal wirings 23, 24 and 25 in the first metal wiring layer.
In the case of the example of FIG. 1, in the logic circuit region 10a, the wiring layer is connected to each region as follows through the via 19 so as to constitute a NOR circuit composed of two nMOS and two pMOS. Yes.

  A signal wiring 23 is connected to the gate electrode 15. A signal wiring 24 is connected to the gate electrode 16. In addition, the ground wiring 20 is connected to the nMOS source region (not shown) of the nMOS region 13. A power supply wiring 22 is connected to the source region of one pMOS (not shown) of the pMOS region 14. A signal wiring 25 is connected to the drain region of the other pMOS (not shown), and is connected to the drains of two nMOSs (not shown) in the nMOS region 13.

  Two inputs of such a NOR circuit are input to the gate electrodes 15 and 16 of the nMOS region 13 and the pMOS region 14 through the signal wirings 23 and 24, and the calculation result is output through the signal wiring 25.

  In the capacitance region 10 b, the ground wiring 21 is connected to the polysilicon 17 c that is the upper electrode of the MOS capacitor 17 through the via 19, and the power supply wiring 22 is connected to the diffusion layer 17 a that is the lower electrode through the via 19. The Further, the power supply wiring 22 may be connected to the polysilicon 17c of the upper electrode, and the ground wiring 21 may be connected to the diffusion layer 17a of the lower electrode.

  As shown in FIG. 2, an interlayer insulating film 26 is formed on the first metal wiring layer, and a second metal wiring layer 27 is formed thereon. Further, an interlayer insulating film 28 is formed thereon, and a metal third wiring layer 29 is formed. In FIG. 2, the number of wiring layers is three, but four or more wiring layers may be formed.

  Although only three standard cells 10 are shown in FIG. 1, for example, a plurality of similar standard cells 10 are also arranged in the vertical and horizontal directions of these standard cells 10. At that time, the ground wiring 20 is shared with a standard cell (not shown) adjacent to the lower side of the standard cell 10 in FIG. 1, and is connected to the MOS capacitor of the standard cell via a via. The ground wiring 21 is shared with a standard cell (not shown) adjacent to the upper side of the standard cell 10, and is connected to the logic circuit region of the standard cell through a via.

Further, the signal wirings 23 to 25 may be pulled up to an upper wiring layer of the second or higher metal layer in an arbitrary standard cell or a region outside the standard cell.
The ground wirings 20 and 21 and the power wiring 22 are in the same layer in the standard cell 10 and are pulled up to the upper wiring layer outside the standard cell 10 (for example, a region for forming a power wiring ring or a ground wiring ring described later). It may be.

FIG. 3 is an overall configuration diagram of an example of the semiconductor integrated circuit according to the first embodiment.
The semiconductor integrated circuit 30 of the first embodiment has a cell array region in which a plurality of standard cells 10 are arranged, and a power supply wiring ring 31 and a ground wiring ring 32 surround the periphery of the cell array region.

  Although not shown in FIG. 3, the ground wirings 20 and 21 drawn from the standard cells 10 shown in FIGS. 1 and 2 are connected to a ground wiring ring 32, and the power wiring 22 is a power wiring ring. 31 is connected. Further, the signal wirings 23, 24, and 25 are connected to any of signal terminals of other cells, signal wirings, or a plurality of input / output terminals 33 arranged on the outer periphery of the semiconductor integrated circuit 30.

  Thus, by uniformly disposing the standard cell 10 having the MOS capacitor 17 in the semiconductor integrated circuit 30, noise generated in the logic circuit region 10a can be efficiently reduced.

  Further, since the MOS capacitor 17 is connected between the power supply wiring 22 and the ground wiring 21 in the same wiring layer, the arrangement of the other wiring layers is not disturbed, and the wiring efficiency is efficiently reduced. Noise can be removed.

Next, a semiconductor integrated circuit according to a second embodiment will be described.
FIG. 4 is a top view of the main part of the semiconductor integrated circuit according to the second embodiment.
In the semiconductor integrated circuit of the second embodiment, each standard cell 40 has a logic circuit region 40a and a capacitor region 40b. The configuration of each region is the same as that of the logic circuit region 10a and the capacitance region 10b in FIG. However, unlike the semiconductor integrated circuit of the first embodiment, the standard cell 40 is connected to two power supply wires 41 and 42 and one ground wire 43.

  The power supply wiring 41 and the ground wiring 43 are connected to the logic circuit area 40a in the same manner as the connection relation of the power supply wiring 22 and the ground wiring 20 to the logic circuit area 10a of FIG. Further, the power supply wiring 42 and the ground wiring 43 are connected to the capacitance region 40b in the same manner as the connection relationship of the power supply wiring 22 and the ground wiring 21 to the capacitance region 10b in FIG.

  In FIG. 4, only three standard cells 40 are illustrated. For example, a plurality of similar standard cells 40 are also arranged in the vertical and horizontal directions of these standard cells 40. At that time, the power supply wiring 41 is shared with a standard cell (not shown) adjacent to the upper side of the standard cell 40 in FIG. 4, and the power supply wiring 42 is shared with a standard cell (not shown) adjacent to the lower side of the standard cell 40.

  As described above, the capacitance region 40b for noise removal is provided in each standard cell 40, and the power supply wiring 42 and the ground wiring 43 of the same wiring layer (metal 1 layer) are connected to the MOS capacitor. The same effects as those of the semiconductor integrated circuit of the embodiment can be obtained.

Next, a semiconductor integrated circuit according to a third embodiment will be described.
FIG. 5 is a top view of the main part of the semiconductor integrated circuit according to the third embodiment.
In the semiconductor integrated circuit of the third embodiment, each standard cell 50, 51, 52 has a logic circuit region 50a and a capacitor region 50b. Since the configuration of the logic circuit area 50a is the same as that of the logic circuit area 10a of FIG. 1, the reference numerals are omitted.

  In the semiconductor integrated circuit of the third embodiment, unlike the semiconductor integrated circuits of the first and second embodiments, the MOS capacitor 53 is formed across adjacent standard cells 50 to 52. Similarly, a diffusion layer 55 formed on the semiconductor substrate 54 and serving as the lower electrode of the MOS capacitor 53 is also formed across the standard cells 50 to 52.

The connection relationship between the ground wirings 56 and 57, the power supply wiring 58, the logic circuit region 50a, and the capacitance region 50b is the same as in FIG.
The standard cell 50 is, for example, a terminal cell of a cell array region arranged as shown in FIG. 3, and a MOS capacitor 53 is formed partway in the horizontal direction of the capacitor region 50b, and the rest is a free region. . On the surface of the semiconductor substrate 54 in the vacant area, a contact with the power supply wiring 58 may be made through the via 59 to stabilize the substrate potential. Note that contact with the ground wiring 57 may be achieved.

  According to the semiconductor integrated circuit of the third embodiment as described above, the same effect as that of the semiconductor integrated circuit of the first embodiment can be obtained, and the MOS capacitor can be extended across the standard cells 50-52. By forming 53, the area of the capacitor can be increased. Thereby, noise can be more efficiently removed.

  As in the semiconductor integrated circuit according to the second embodiment, the logic circuit region 50a and the capacitor region 50b of the standard cells 50 to 52 are replaced, and each standard cell 50 to 52 has two power supply lines and one You may make it connect to a ground wiring.

Further, in order to increase the MOS capacity 53, the MOS capacity 53 may be formed so as to extend to the logic circuit area 50a if the logic circuit area 50a has an empty area.
Next, a semiconductor integrated circuit according to a fourth embodiment will be described.

FIG. 6 is a top view of the main part of the semiconductor integrated circuit according to the fourth embodiment.
FIG. 7 is a cross-sectional view taken along the line AB of FIG.
In the semiconductor integrated circuit of the fourth embodiment, each standard cell 60 has a logic circuit region 60a and a capacitor region 60b. Since the configuration of the logic circuit area 60a is the same as that of the logic circuit area 10a of FIG. 1, the reference numerals are omitted.

A plurality of diffusion layers 62 are formed in the semiconductor substrate 61 in order to achieve electrical connection from the upper layer and stabilize the well potential of the semiconductor substrate 61.
Similar to the semiconductor integrated circuit of the first embodiment, each standard cell 60 is connected to two ground wirings 63 and 64 and one power supply wiring 65.

  However, unlike the semiconductor integrated circuits of the first to third embodiments, the semiconductor integrated circuit of the fourth embodiment uses a ferroelectric material 66 in place of the MOS capacitor in the capacitor region 60b. Make up body volume.

  The ferroelectric material 66 is provided between the upper electrode 67 and the lower electrode 68 and is disposed apart from the semiconductor substrate 61 in the interlayer insulating film 69 as shown in FIG. The upper electrode 67 is connected to the ground wiring 64 through the via 70a, and the lower electrode 68 is connected to the power supply wiring 65 through the via 70b.

  According to the semiconductor integrated circuit of the fourth embodiment, the same effect as that of the semiconductor integrated circuit of the first embodiment can be obtained, and the ferroelectric material 66 having a large dielectric constant can be formed in the capacitor region 60b. By configuring a ferroelectric capacitor using, noise can be further efficiently removed.

Next, a semiconductor integrated circuit according to a fifth embodiment will be described.
FIG. 8 is a top view of the main part of the semiconductor integrated circuit according to the fifth embodiment.
FIG. 9 is a cross-sectional view taken along the line AB of FIG.

The same components as those in the semiconductor integrated circuit according to the fourth embodiment are denoted by the same reference numerals.
In the semiconductor integrated circuit of the fifth embodiment, each standard cell 80 has a logic circuit region 80a and a capacitor region 80b. Although the detailed description is omitted, the logic circuit region 80a shows an example in which an OR circuit including a NOR circuit and an inverter circuit is configured.

  In the standard cell 80 in the semiconductor integrated circuit according to the fifth embodiment, a ferroelectric material 81 constituting a ferroelectric capacitor passes under the power wiring 65 and extends to the logic circuit region 80a. Similarly, the upper electrode 82 and the lower electrode 83 are also expanded and connected to the ground wiring 64 or the power supply wiring 65 through the vias 84a and 84b, respectively.

  According to the semiconductor integrated circuit of the fifth embodiment as described above, the same effect as that of the integrated circuit of the fourth embodiment can be obtained, and the ferroelectric capacitance can be increased, so that noise can be more efficiently generated. Can be removed.

  Whether the standard cell 60 in the fourth embodiment or the standard cell 80 in the present embodiment is used does not require a free area (for example, a contact from the first metal wiring layer) in the logic circuit area. It may be selected according to whether or not there is an area.

Next, a semiconductor integrated circuit according to a sixth embodiment will be described.
FIG. 10 is a top view of the main part of the semiconductor integrated circuit according to the sixth embodiment.
FIG. 11 is a cross-sectional view taken along the line AB of FIG.

The same components as those in the semiconductor integrated circuit according to the fourth embodiment are denoted by the same reference numerals.
In the semiconductor integrated circuit of the sixth embodiment, the standard cell 60 is connected to two ground wirings 90 and 91 and one power supply wiring 92 as in the semiconductor integrated circuit of the fourth embodiment. . However, the wiring width of the ground wiring 91 and the power supply wiring 92 connected to the capacitance region 60b is expanded so as to shield the upper portion of the capacitance region 60b. However, a gap with a predetermined width is provided so that the ground wiring 91 and the power supply wiring 92 do not contact each other.

  Thereby, the wiring resistance of the ground wiring 91 and the power supply wiring 92 is reduced, and the operation noise can be efficiently removed. Even when a ferroelectric capacitor having a large dielectric constant is used, the coupling capacitance between the ferroelectric capacitor and the upper wiring layer 93 can be reduced by the shielding effect of the ground wiring 91 and the power supply wiring 92. .

  As in the semiconductor integrated circuits of the first to third embodiments, even when a MOS capacitor is used, the wiring width of the power supply wiring and the ground wiring to which the MOS capacitor is connected is set as described above. You may make it expand so that an upper part may be shielded.

  Further, in the semiconductor integrated circuits of the fourth to sixth embodiments, the logic circuit region and the capacitor region of the standard cell are interchanged as in the semiconductor integrated circuit of the second embodiment as shown in FIG. Each standard cell may be connected to two power supply lines and one ground line.

  Further, like the MOS capacitor 53 of the semiconductor integrated circuit of the third embodiment as shown in FIG. 5, a ferroelectric capacitor is provided so as to straddle between standard cells adjacent in the horizontal direction. Also good.

  The standard cells in the semiconductor integrated circuits of the first to sixth embodiments described above may be arranged so as to be combined with each other in, for example, the semiconductor integrated circuit as shown in FIG.

  Further, in the semiconductor integrated circuits of the first to sixth embodiments, the ground wiring and the power supply wiring are used as the first metal layer so that the upper signal wiring can be efficiently routed, and the MOS capacitance and the ferroelectric are provided there. The body capacitance is connected, but it may be the second layer or more as long as it is the same layer. In that case, the ferroelectric capacitor is formed in the interlayer insulating film of the wiring layer where the ground wiring and the power supply wiring exist, so that the wiring distance from the logic circuit region to the ferroelectric capacitor can be shortened. In addition, it can be prevented that the signal wirings of other layers are disturbed.

Further, when a large capacity is not required, it may be combined with a standard cell having no capacity area.
FIG. 12 is a top view showing an example of a semiconductor integrated circuit in which standard cells having a capacitor region and standard cells having no capacitor region are mixed.

  Here, a case is shown in which standard cells 50, 51 and 52 in the semiconductor integrated circuit of the third embodiment shown in FIG. 5 are mixed with standard cells 100 and 101 having no capacity region. The same components as those in FIG. 5 are denoted by the same reference numerals or omitted.

  For the standard cells 50, 51, 52 having the logic circuit region 50a and the capacitor region 50b, two ground wirings 56, 57 and one power supply wiring 58 are connected. On the other hand, for the standard cell 100 having no capacity region, the ground wiring 56 and the power wiring 102 are connected, and for the standard cell 101 having no capacity region, the power wiring 102 and the ground wiring 103 are connected. Connected.

  As mentioned above, although the semiconductor integrated circuit of this case has been described based on a plurality of embodiments, these are only examples and are not limited to the above description.

1 is a top view of a main part of a semiconductor integrated circuit according to a first embodiment; It is sectional drawing in the AB line of FIG. 1 is an overall configuration diagram of an example of a semiconductor integrated circuit according to a first embodiment; It is a top view of the principal part of the semiconductor integrated circuit of 2nd Embodiment. It is a top view of the principal part of the semiconductor integrated circuit of 3rd Embodiment. It is a top view of the principal part of the semiconductor integrated circuit of 4th Embodiment. It is sectional drawing in the AB line | wire of FIG. It is a top view of the principal part of the semiconductor integrated circuit of 5th Embodiment. It is sectional drawing in the AB line | wire of FIG. It is a top view of the principal part of the semiconductor integrated circuit of 6th Embodiment. It is sectional drawing in the AB line of FIG. It is a top view which shows an example of the semiconductor integrated circuit which mixed the standard cell which has a capacity | capacitance area | region, and the standard cell which does not have a capacity | capacitance area | region.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Standard cell 10a Logic circuit area 10b Capacitance area | region 11 Semiconductor substrate 12, 17a Diffusion layer 13 nMOS area | region 14 pMOS area | region 15,16 Gate electrode 17 MOS capacity | capacitance 18 Interlayer insulating film 19 Via 20, 21 Ground wiring 22 Power supply wiring

Claims (5)

A plurality of cells having a logic circuit area and a capacity area;
The cell is connected to two power supply wirings and one grounding wiring, or one power supply wiring and two grounding wirings belonging to the same wiring layer. A semiconductor integrated circuit characterized by being connected between the power supply wiring and the ground wiring in the same wiring layer.   The semiconductor integrated circuit according to claim 1, wherein the capacitor is disposed across adjacent cells.   The semiconductor integrated circuit according to claim 1, wherein the capacitor is disposed so as to be expanded in the logic circuit region.   4. The semiconductor integrated circuit according to claim 1, wherein the power supply wiring and the ground wiring connected to the capacitor are provided so as to cover an upper portion of the capacitor. 5.   5. The semiconductor integrated circuit according to claim 1, wherein the capacitor is connected to the power supply wiring and the ground wiring in a lowermost wiring layer. 6.

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