JP2008166910A - クロック信号生成装置及びアナログ−デジタル変換装置 - Google Patents

クロック信号生成装置及びアナログ−デジタル変換装置 Download PDF

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Publication number
JP2008166910A
JP2008166910A JP2006351203A JP2006351203A JP2008166910A JP 2008166910 A JP2008166910 A JP 2008166910A JP 2006351203 A JP2006351203 A JP 2006351203A JP 2006351203 A JP2006351203 A JP 2006351203A JP 2008166910 A JP2008166910 A JP 2008166910A
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JP
Japan
Prior art keywords
output
clock signal
flip
signal
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2006351203A
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English (en)
Japanese (ja)
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JP2008166910A5 (https=
Inventor
Yoshikazu Makabe
良和 眞壁
Ikuo Hidaka
郁夫 日高
Koji Oka
浩二 岡
Toshiaki Ozeki
俊明 尾関
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2006351203A priority Critical patent/JP2008166910A/ja
Priority to CN2007101993543A priority patent/CN101212213B/zh
Priority to US11/964,943 priority patent/US7609194B2/en
Publication of JP2008166910A publication Critical patent/JP2008166910A/ja
Publication of JP2008166910A5 publication Critical patent/JP2008166910A5/ja
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
    • H03M1/0624—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by synchronisation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/06—Clock generators producing several clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/151—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with two complementary outputs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/1205—Multiplexed conversion systems
    • H03M1/121—Interleaved, i.e. using multiple converters or converter parts for one channel
    • H03M1/1215—Interleaved, i.e. using multiple converters or converter parts for one channel using time-division multiplexing

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Analogue/Digital Conversion (AREA)
  • Manipulation Of Pulses (AREA)
JP2006351203A 2006-12-27 2006-12-27 クロック信号生成装置及びアナログ−デジタル変換装置 Pending JP2008166910A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2006351203A JP2008166910A (ja) 2006-12-27 2006-12-27 クロック信号生成装置及びアナログ−デジタル変換装置
CN2007101993543A CN101212213B (zh) 2006-12-27 2007-12-17 模拟-数字变换装置以及ic芯片
US11/964,943 US7609194B2 (en) 2006-12-27 2007-12-27 Clock signal generating device and analog-digital conversion device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006351203A JP2008166910A (ja) 2006-12-27 2006-12-27 クロック信号生成装置及びアナログ−デジタル変換装置

Publications (2)

Publication Number Publication Date
JP2008166910A true JP2008166910A (ja) 2008-07-17
JP2008166910A5 JP2008166910A5 (https=) 2009-02-19

Family

ID=39583125

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006351203A Pending JP2008166910A (ja) 2006-12-27 2006-12-27 クロック信号生成装置及びアナログ−デジタル変換装置

Country Status (3)

Country Link
US (1) US7609194B2 (https=)
JP (1) JP2008166910A (https=)
CN (1) CN101212213B (https=)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8749419B2 (en) * 2009-08-11 2014-06-10 Hittite Microwave Corporation ADC with enhanced and/or adjustable accuracy
PL220358B1 (pl) * 2012-01-31 2015-10-30 Akademia Górniczo Hutnicza Im Stanisława Staszica W Krakowie Sposób i układ do bezzegarowego przetwarzania wielkości napięcia elektrycznego na słowo cyfrowe
KR101970612B1 (ko) * 2013-03-15 2019-08-13 퀄컴 인코포레이티드 저 전력 아키텍처들
JP6127807B2 (ja) * 2013-07-26 2017-05-17 富士通株式会社 送信回路、通信システム及び通信方法
KR102432457B1 (ko) * 2015-10-21 2022-08-12 삼성전자주식회사 디스큐 기능을 갖는 클락 발생 회로 및 상기 회로를 포함하는 반도체 집적회로 장치
JP6823268B2 (ja) * 2016-03-11 2021-02-03 株式会社ソシオネクスト 分周回路、デマルチプレクサ回路、及び半導体集積回路
US10790845B1 (en) * 2019-05-31 2020-09-29 The Boeing Company Clocking circuit and method for time-interleaved analog-to-digital converters
CN112202446B (zh) * 2019-07-08 2024-06-14 北京三中科技有限公司 一种相位同步装置和方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5552732A (en) * 1995-04-25 1996-09-03 Exar Corporation High speed divide by 1.5 clock generator
JPH09270677A (ja) * 1995-09-05 1997-10-14 Mitsubishi Electric Corp フリップフロップ回路及びスキャンパス並びに記憶回路
US5808691A (en) * 1995-12-12 1998-09-15 Cirrus Logic, Inc. Digital carrier synthesis synchronized to a reference signal that is asynchronous with respect to a digital sampling clock
JP3467975B2 (ja) * 1996-06-27 2003-11-17 安藤電気株式会社 位相検出回路
EP0844740B1 (en) * 1996-11-21 2003-02-26 Matsushita Electric Industrial Co., Ltd. A/D converter and A/D conversion method
JP2000216762A (ja) 1999-01-26 2000-08-04 Hitachi Denshi Ltd サンプリング周波数変換回路
JP4397488B2 (ja) * 1999-12-17 2010-01-13 Ｎｓｃ株式会社 オーバーサンプリング処理回路およびデジタル−アナログ変換器
JP2001217886A (ja) 2000-01-31 2001-08-10 Matsushita Electric Ind Co Ltd 移相器
US6642747B1 (en) * 2002-03-15 2003-11-04 National Semiconductor Corporation Frequency detector for a phase locked loop system
JP3956847B2 (ja) * 2002-04-24 2007-08-08 株式会社デンソー Ａ／ｄ変換方法及び装置
DE60321016D1 (https=) * 2003-12-17 2008-06-26 Sgs Thomson Microelectronics
DE602005018114D1 (de) * 2005-03-31 2010-01-14 Freescale Semiconductor Inc Verfahren zur rauschminderung in einem phasenregelkreis und einrichtung mit rauschminderungsfähigkeiten
US7515666B2 (en) * 2005-07-29 2009-04-07 International Business Machines Corporation Method for dynamically changing the frequency of clock signals
KR100808055B1 (ko) * 2006-10-31 2008-02-28 주식회사 하이닉스반도체 반도체 소자의 지연 고정 루프와 그의 구동 방법

Also Published As

Publication number Publication date
US7609194B2 (en) 2009-10-27
CN101212213A (zh) 2008-07-02
US20080158035A1 (en) 2008-07-03
CN101212213B (zh) 2011-11-23

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