JP2008166605A - Multi-chip module - Google Patents

Multi-chip module Download PDF

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Publication number
JP2008166605A
JP2008166605A JP2006356360A JP2006356360A JP2008166605A JP 2008166605 A JP2008166605 A JP 2008166605A JP 2006356360 A JP2006356360 A JP 2006356360A JP 2006356360 A JP2006356360 A JP 2006356360A JP 2008166605 A JP2008166605 A JP 2008166605A
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Japan
Prior art keywords
circuit board
circuit boards
terminals
clip terminal
external connection
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Pending
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JP2006356360A
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Japanese (ja)
Inventor
Hidetoshi Takahashi
英俊 高橋
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Hitachi Ltd
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Hitachi Ltd
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Priority to JP2006356360A priority Critical patent/JP2008166605A/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched

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  • Combinations Of Printed Boards (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the decline of reliability by eliminating adverse influence by heat even for a multi-chip module for which circuit boards arranged in two or more stages are connected and fixed so as to be clamped by terminals for external connection. <P>SOLUTION: The circuit boards 3 where a plurality of semiconductor chips 5 is mounted are laminated and disposed in two or more stages, and both ends of the respective circuit boards 3 are connected and held by being clamped by the recessed parts 9a of a clip terminal 9. A notched part 9b is provided between the recessed parts 9a of the clip terminal 9, the deformation (warp) caused by heat of the circuit boards 3 is absorbed by the notched part 9b and influence onto the other circuit boards 3 is eliminated. <P>COPYRIGHT: (C)2008,JPO&amp;INPIT

Description

本発明は、電子部品である半導体チップを複数備えたマルチチップモジュールに関する。   The present invention relates to a multichip module including a plurality of semiconductor chips which are electronic components.

従来より、特に小型の電子機器に用いるために、小さな容量で高密度に半導体チップを回路基板に実装した構成のマルチチップモジュールが開発されている。   2. Description of the Related Art Conventionally, multi-chip modules having a configuration in which semiconductor chips are mounted on a circuit board with a small capacity and high density have been developed for use in particularly small electronic devices.

そして近年、より高機能な電子機器に向けて、半導体チップ数の増加に対応するために、回路基板を2枚重ねて接合したものの両面に半導体チップを実装したものが提案されている(例えば下記特許文献1参照)。
特開平5−291493号公報
In recent years, in order to cope with an increase in the number of semiconductor chips, there has been proposed a semiconductor chip mounted on both sides of a circuit board in which two circuit boards are stacked and bonded in order to cope with an increase in the number of semiconductor chips (for example, the following). Patent Document 1).
JP-A-5-291493

ところで、上記した従来のマルチチップモジュールは、2枚重ねの回路基板の両端を外部接続用の端子で挟み込むようにして固定すると同時に外部との電気的接続を行っている。   By the way, the above-described conventional multichip module fixes both ends of a two-layer circuit board so as to be sandwiched between terminals for external connection, and at the same time performs electrical connection with the outside.

ところが、このようなマルチチップモジュールにおいて、さらにモジュールの高密度化が要求されて2枚重ねの回路基板を、所定間隔をおいて複数段に重ねる構成とした場合に、上記した外部接続用の端子で、それぞれの回路基板を挟み込むようにすると、熱によって回路基板に反りが発生したときに、該回路基板を挟み込んでいる外部接続用の端子に応力が作用して他の回路基板に悪影響を及ぼし、この影響を受けた回路基板と該回路基板に実装している半導体チップとの接合部に応力が作用して信頼性の低下を招く。   However, in such a multi-chip module, when the module is required to have a higher density and the two-layer circuit board is configured to be stacked in a plurality of stages at predetermined intervals, the external connection terminal described above is used. Thus, if each circuit board is sandwiched, when the circuit board is warped by heat, stress acts on the external connection terminals sandwiching the circuit board and adversely affects other circuit boards. The stress acts on the joint between the affected circuit board and the semiconductor chip mounted on the circuit board, leading to a decrease in reliability.

そこで、本発明は、複数段に配置した回路基板を、外部接続用の端子で挟み込むようにして接続固定したマルチチップモジュールであっても、熱による悪影響を排除して信頼性の低下を防止することを目的としている。   Therefore, the present invention eliminates adverse effects due to heat and prevents a decrease in reliability even in a multichip module in which circuit boards arranged in a plurality of stages are connected and fixed so as to be sandwiched between terminals for external connection. The purpose is that.

本発明は、外部接続用の端子の挟持部相互間の切欠部によって、熱により回路基板に発生した反りによる変形分を吸収し、他の回路基板への影響を排除し、他の回路基板と該他の回路基板に実装している半導体チップとの接合部への応力付与を回避して、信頼性の低下を防止することができる。   The present invention absorbs the deformation due to the warp generated in the circuit board due to heat by the notch part between the pinching parts of the terminals for external connection, eliminates the influence on the other circuit board, It is possible to prevent stress from being applied to the joint portion with the semiconductor chip mounted on the other circuit board and to prevent a decrease in reliability.

以下、本発明の実施の形態を図面に基づき説明する。   Hereinafter, embodiments of the present invention will be described with reference to the drawings.

図1は、本発明の第1の実施形態に係わるマルチチップモジュール1の正面断面図である。このマルチチップモジュール1は、回路基板3(3a,3b,3c)を複数枚(ここでは3枚)所定間隔をおいて積層配置しており、これら各回路基板3上には、電子部品である半導体チップ5をそれぞれ複数実装している。実装した半導体チップ5は、ワイヤボンディング7で回路基板3に接続する。   FIG. 1 is a front sectional view of a multichip module 1 according to a first embodiment of the present invention. In this multichip module 1, a plurality of circuit boards 3 (3a, 3b, 3c) (three in this case) are laminated at a predetermined interval, and on these circuit boards 3, electronic components are arranged. A plurality of semiconductor chips 5 are respectively mounted. The mounted semiconductor chip 5 is connected to the circuit board 3 by wire bonding 7.

上記した各回路基板3の図1中で左右両端は、外部接続用の端子である弾性変形可能なクリップ端子9により固定している。クリップ端子9は、その全体を導電性部材で構成するか、あるいは表面を導電性金属部材によりメッキを施してあり、回路基板3上の半導体チップ5の電源端子、GND端子、あるいは信号端子となる。   The left and right ends of each circuit board 3 in FIG. 1 are fixed by elastically deformable clip terminals 9 which are terminals for external connection. The clip terminal 9 is entirely composed of a conductive member, or the surface thereof is plated with a conductive metal member, and becomes a power supply terminal, a GND terminal, or a signal terminal of the semiconductor chip 5 on the circuit board 3. .

このようなクリップ端子9は、図2(a)に模式的に示す平面図のように、回路基板3の図2中で左右両端の側縁に沿って長いものを一つずつ設ける構成としてもよく、また同図(b)のように、回路基板3の図2中で左右両端の側縁に沿ってそれぞれ複数(ここでは2個)設ける構成としてもよい。   As shown in the plan view schematically shown in FIG. 2 (a), such a clip terminal 9 may have a structure in which one long one is provided along the left and right side edges of the circuit board 3 in FIG. Alternatively, as shown in FIG. 2B, a plurality (two in this case) may be provided along the side edges of the left and right ends of the circuit board 3 in FIG.

上記したクリップ端子9は、各回路基板3を挟み込むようにして固定する挟持部となる凹部9aを備え、この凹部9aに回路基板3の両端を挿入し、回路基板3の両端と凹部9aとは導電性接着剤で接続固定する。これによりクリップ端子9は、回路基板3を機械的に挟持固定するとともに、回路基板3上の導電部に電気的に接続した状態となる。   The above-described clip terminal 9 includes a concave portion 9a serving as a clamping portion that fixes each circuit board 3 so as to sandwich each circuit board 3, and both ends of the circuit board 3 are inserted into the concave portion 9a. Connect and fix with conductive adhesive. Thereby, the clip terminal 9 is in a state of mechanically holding and fixing the circuit board 3 and being electrically connected to the conductive portion on the circuit board 3.

なお、回路基板3の両端をクリップ端子9の凹部9aに挿入した状態では、回路基板3の端縁部と凹部9aの底部との間に、隙間11を設けている。   In the state where both ends of the circuit board 3 are inserted into the recesses 9a of the clip terminals 9, a gap 11 is provided between the edge of the circuit board 3 and the bottom of the recess 9a.

そして、各回路基板3が挿入されるクリップ端子9の凹部9a相互間には、凹部9aとほぼ同じ深さで、凹部9aよりも図1中で上下方向の幅が狭い切欠部9bを設けている。   Between the recesses 9a of the clip terminal 9 into which each circuit board 3 is inserted, a notch 9b having a depth substantially the same as the recess 9a and having a narrower vertical width in FIG. 1 than the recess 9a is provided. Yes.

クリップ端子9は、上記した凹部9aおよび切欠部9bを備える基板保持部9cの図1中で下部外側から下方に延びるピン部9dを備え、このピン部9dを、例えばマザー基板13に接続固定する。   The clip terminal 9 is provided with a pin portion 9d extending downward from the lower outer side in FIG. 1 of the substrate holding portion 9c having the recess 9a and the notch portion 9b, and the pin portion 9d is connected and fixed to the mother substrate 13, for example. .

また、上記した各回路基板3は、クリップ端子9の基板保持部9cおよび、ピン部9dの基板保持部9c側の一部位とともに、樹脂カバー15によって覆われている。この樹脂カバー15はアッパカバー15aとロアカバー15bとで構成しており、これら各カバー15a,15bを、クリップ端子9で保持している各回路基板3に対して上下から被せるようにして覆い、各カバー15a,15bの接合端部相互を接着剤などによって固定する。 なお、このときロアカバー15bには、ピン部9dが挿入される貫通孔15cを設けている。   Each circuit board 3 described above is covered with a resin cover 15 together with the substrate holding part 9c of the clip terminal 9 and a part of the pin part 9d on the board holding part 9c side. The resin cover 15 is composed of an upper cover 15a and a lower cover 15b. The covers 15a and 15b are covered with the circuit boards 3 held by the clip terminals 9 from above and below. The joint ends of the covers 15a and 15b are fixed with an adhesive or the like. At this time, the lower cover 15b is provided with a through hole 15c into which the pin portion 9d is inserted.

このように構成したマルチチップモジュール1は、例えば半導体チップ5の発熱による熱によって、例えば一つの回路基板3aに反りが発生して変形した場合には、その変形による応力がクリップ端子9に作用するが、この応力は凹部9a相互間に設けてある切欠部9bが吸収する。   In the multichip module 1 configured as described above, for example, when one of the circuit boards 3a is warped and deformed by heat generated by the semiconductor chip 5, for example, the stress due to the deformation acts on the clip terminal 9. However, this stress is absorbed by the notch 9b provided between the recesses 9a.

具体的には、回路基板3aの反りによってクリップ端子9は、回路基板3aの端部を挿入してある凹部9aと切欠部9bとの間の部分9eが切欠部9b側に変形して切欠部9bの図1中で上下方向の幅が狭くなるように変形する。   Specifically, the clip terminal 9 is deformed by the warp of the circuit board 3a so that the portion 9e between the recess 9a into which the end of the circuit board 3a is inserted and the notch 9b is deformed to the notch 9b side. 9b is deformed so that the width in the vertical direction becomes narrower in FIG.

これによりクリップ端子9は、他の回路基板3b,3c、特に反りが発生している回路基板3aに隣接する回路基板3bを保持している凹部9b付近の変形が抑制され、該回路基板3bや回路基板3cの変形を防止することができる。回路基板3b,3cの変形を防止することで、回路基板3b,3cと該回路基板3b,3cに実装している半導体チップ5との接合部への応力付与を回避して、信頼性の低下を防止することができる。   As a result, the clip terminal 9 is prevented from being deformed in the vicinity of the other circuit boards 3b and 3c, particularly the recess 9b holding the circuit board 3b adjacent to the circuit board 3a in which the warp is generated, The deformation of the circuit board 3c can be prevented. By preventing deformation of the circuit boards 3b and 3c, it is possible to avoid applying stress to the joint between the circuit boards 3b and 3c and the semiconductor chip 5 mounted on the circuit boards 3b and 3c, thereby reducing reliability. Can be prevented.

すなわち、本実施形態においては、反りが発生している回路基板の他の回路基板への影響を排除し、高密度化したマルチチップモジュール1の信頼性を高めることができる。   In other words, in the present embodiment, the influence of the warped circuit board on other circuit boards can be eliminated, and the reliability of the multichip module 1 having a higher density can be improved.

図3は、本発明の第2の実施形態に係わるマルチチップモジュール1Aの正面断面図である。このマルチチップモジュール1Aは、回路基板3を、ワイヤボンディング7にて半導体チップ5を実装していない面同士を貼り合わせて一体化し、この一体化した2枚の回路基板対3Aを、クリップ端子9の挟持部である凹部9aにて挟持固定している。   FIG. 3 is a front sectional view of a multichip module 1A according to the second embodiment of the present invention. In this multi-chip module 1A, the circuit board 3 is integrated by bonding the surfaces on which the semiconductor chip 5 is not mounted by wire bonding 7, and the integrated two circuit board pairs 3A are connected to the clip terminals 9A. It is clamped and fixed by the recessed part 9a which is a clamping part.

その他の構成は、前記図1に示した第1の実施形態と同様であり、同一構成要素には同一符号を付してある。   Other configurations are the same as those of the first embodiment shown in FIG. 1, and the same components are denoted by the same reference numerals.

第2の実施形態においても、半導体チップ5の発熱による熱によって、例えば一つの回路基板対3Aに反りが発生した場合には、その反りによる応力がクリップ端子9に作用するが、この応力は凹部9a相互間に設けてある切欠部9bが吸収するので、他の回路基板3Aへの影響を排除し、図1の第1の実施形態よりもさらに高密度化したマルチチップモジュール1Aの信頼性を高めることができる。   Also in the second embodiment, when a warp occurs in one circuit board pair 3A due to the heat generated by the semiconductor chip 5, for example, the stress due to the warp acts on the clip terminal 9, but this stress is a concave portion. 9a absorbs the notch 9b provided between each other, so that the influence on the other circuit board 3A is eliminated, and the reliability of the multichip module 1A having a higher density than that of the first embodiment of FIG. Can be increased.

本発明の第1の実施形態に係わるマルチチップモジュールの正面断面図である。It is front sectional drawing of the multichip module concerning the 1st Embodiment of this invention. 図1のマルチチップモジュールにおけるクリップ端子の模式的な平面図である。FIG. 2 is a schematic plan view of clip terminals in the multichip module of FIG. 1. 本発明の第2の実施形態に係わるマルチチップモジュールの正面断面図である。It is front sectional drawing of the multichip module concerning the 2nd Embodiment of this invention.

符号の説明Explanation of symbols

3 回路基板
5 半導体チップ(電子部品)
9 クリップ端子(外部接続用の端子)
9a クリップ端子の凹部(挟持部)
9b クリップ端子の切欠部
3 Circuit board 5 Semiconductor chip (electronic component)
9 Clip terminal (terminal for external connection)
9a Recessed part of clip terminal (clamping part)
9b Notch in clip terminal

Claims (1)

電子部品を実装した回路基板を所定間隔をおいて複数枚積層し、これら各回路基板の両端を外部接続用の端子に設けた挟持部によってそれぞれ挟持し、前記外部接続用の端子の前記挟持部相互間に切欠部を設けたことを特徴とするマルチチップモジュール。   A plurality of circuit boards on which electronic components are mounted are stacked at a predetermined interval, and both ends of each circuit board are respectively clamped by clamping parts provided on the terminals for external connection, and the clamping part of the terminals for external connection A multi-chip module characterized in that a notch is provided between each other.
JP2006356360A 2006-12-28 2006-12-28 Multi-chip module Pending JP2008166605A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2006356360A JP2008166605A (en) 2006-12-28 2006-12-28 Multi-chip module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006356360A JP2008166605A (en) 2006-12-28 2006-12-28 Multi-chip module

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JP2008166605A true JP2008166605A (en) 2008-07-17

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Country Link
JP (1) JP2008166605A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010056377A (en) * 2008-08-29 2010-03-11 Seiko Instruments Inc Electronic component package, and method of manufacturing electronic component package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010056377A (en) * 2008-08-29 2010-03-11 Seiko Instruments Inc Electronic component package, and method of manufacturing electronic component package

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