JP4674477B2 - Semiconductor module - Google Patents

Semiconductor module Download PDF

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Publication number
JP4674477B2
JP4674477B2 JP2005058776A JP2005058776A JP4674477B2 JP 4674477 B2 JP4674477 B2 JP 4674477B2 JP 2005058776 A JP2005058776 A JP 2005058776A JP 2005058776 A JP2005058776 A JP 2005058776A JP 4674477 B2 JP4674477 B2 JP 4674477B2
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semiconductor
mounting substrate
mounting
semiconductor device
semiconductor chip
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JP2006245278A (en
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浩章 桂
剛史 東條
信治 吉野
英信 西川
隆司 佐藤
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Panasonic Corp
Panasonic Holdings Corp
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Panasonic Corp
Matsushita Electric Industrial Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors

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  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To materialize a high speed high capacity semiconductor module, while keeping the entire shape small. <P>SOLUTION: A plurality of semiconductor devices 209, equipped with a semiconductor chip 211 and a protruded electrode 212, are packaged on a packaging substrate 210, such that an angle has an inclination &theta; between a direction perpendicular to one side where the connection 215 of the semiconductor chip 211 is existent and the packaging substrate 210. Consequently, required packaging substrates 210 are reduced to decrease the height of the module, since this can provide a semiconductor module that has realized high speed and high capacity. <P>COPYRIGHT: (C)2006,JPO&amp;NCIPI

Description

本発明は半導体装置及び半導体モジュールに係り、特に高速対応メモリ及び高速対応メモリモジュールとして用いて好適な半導体装置及び半導体モジュールに関するものである。   The present invention relates to a semiconductor device and a semiconductor module, and more particularly to a semiconductor device and a semiconductor module suitable for use as a high-speed compatible memory and a high-speed compatible memory module.

従来の半導体モジュールとしては、メモリの容量を大きくするために、基板に複数の半導体チップを積層しているものがあった(例えば、特許文献1参照)。図11は、特開2002−9227号公報に記載された従来の実施形態を示すものである。   As a conventional semiconductor module, there is one in which a plurality of semiconductor chips are stacked on a substrate in order to increase the capacity of a memory (see, for example, Patent Document 1). FIG. 11 shows a conventional embodiment described in Japanese Patent Laid-Open No. 2002-9227.

図11の実施形態は、インタポーザ基板(中間実装基板)510の少なくとも片面に半導体チップ211を実装したものを、スペーサ基板512を介して互いに積層した構成となっている。しかしながら、図11の実施形態では、中間実装基板が存在するために、半導体モジュールの高密度化を妨げるという問題を有している。   In the embodiment of FIG. 11, a semiconductor chip 211 mounted on at least one surface of an interposer substrate (intermediate mounting substrate) 510 is stacked on each other via a spacer substrate 512. However, the embodiment of FIG. 11 has a problem that the density of the semiconductor module is hindered due to the presence of the intermediate mounting substrate.

実装密度を高めるためには、半導体装置を搭載する実装基板を少なくして、実装基板に搭載する半導体チップ211の数を増やすことが必要である。実装基板を少なくして、実装基板に搭載する半導体チップ211の数を増やす方法として、実装基板に対して、半導体装置を、立設もしくは斜めに実装するものがあった(例えば、特許文献2参照)。図12は、特開平10−335374号公報に記載された従来の実施形態を示すものである。   In order to increase the mounting density, it is necessary to reduce the number of mounting substrates on which semiconductor devices are mounted and increase the number of semiconductor chips 211 mounted on the mounting substrate. As a method of reducing the number of mounting boards and increasing the number of semiconductor chips 211 mounted on the mounting board, there is a method of mounting a semiconductor device upright or obliquely with respect to the mounting board (for example, see Patent Document 2). ). FIG. 12 shows a conventional embodiment described in JP-A-10-335374.

図12において、半導体チップ211の回路形成面の接続部に外部接続端子104を設けてあった。この外部接続端子には折曲部105が設けてあり、この折曲部を垂立するように半田付けすることによって、立設もしくは斜めに実装することが可能となっている。
特開2002−9227号公報 特開平10−335374号公報
In FIG. 12, the external connection terminal 104 is provided at the connection portion of the circuit formation surface of the semiconductor chip 211. The external connection terminal is provided with a bent portion 105, and can be installed upright or obliquely by soldering the bent portion so as to be suspended.
JP 2002-9227 A Japanese Patent Laid-Open No. 10-335374

しかしながら、前記従来の構成では、半導体モジュールの高さは、半導体チップの高さと実装基板の厚みと外部接続端子の高さの合計によって決定される。したがって、外部接続端子が存在することによって、半導体チップと実装基板との間に接続のための空間が必要になり、半導体モジュールの低背化を妨げるという課題を有していた。   However, in the conventional configuration, the height of the semiconductor module is determined by the sum of the height of the semiconductor chip, the thickness of the mounting substrate, and the height of the external connection terminals. Therefore, the presence of the external connection terminals necessitates a space for connection between the semiconductor chip and the mounting substrate, which hinders a reduction in the height of the semiconductor module.

本発明は、前記従来の課題を解決するもので、半導体装置の実装密度を大きくしつつ低背化を図った高容量かつ小型な半導体モジュールを提供することを目的とする。   SUMMARY OF THE INVENTION The present invention solves the above-described conventional problems, and an object thereof is to provide a high-capacity and small-sized semiconductor module that is reduced in height while increasing the mounting density of semiconductor devices.

上記目的を解決するために、回路形成面を有する半導体チップと前記半導体チップ上に設けられた複数の突起電極とからなる半導体装置を、複数の電極部を備えた基板上に前記回路形成面が対向するように傾けて、前記複数の突起電極と前記複数の電極部を電気的に接続した半導体モジュールであって、前記半導体装置を複数個並設し、隣り合う前記半導体装置を、前記複数の突起電極の配設方向に前記複数の突起電極の間隔の4分の1から4分の3までの間でずらして配設したことを特徴とする半導体モジュールを用いる。 In order to solve the above-described object, a semiconductor device including a semiconductor chip having a circuit formation surface and a plurality of protruding electrodes provided on the semiconductor chip is formed on a substrate having a plurality of electrode portions. A semiconductor module in which the plurality of protruding electrodes and the plurality of electrode portions are electrically connected to each other so as to be opposed to each other , wherein a plurality of the semiconductor devices are arranged side by side, and the adjacent semiconductor devices are A semiconductor module is used, wherein the semiconductor module is arranged so as to be shifted from one-fourth to three-fourths of the interval between the plurality of protruding electrodes in the protruding electrode arrangement direction.

以上のように、本発明の半導体モジュールにおいて、半導体装置を実装基板に半導体チップの回路形成面上で接続部が存在する一辺に直交する方向と実装基板のなす角が傾きθを有するように、基板上の電極部と電気的に接続させている。これにより実装状態における半導体モジュールの低背化及び高密度化を実現することができる。   As described above, in the semiconductor module of the present invention, the angle formed by the mounting substrate and the direction perpendicular to one side where the connecting portion exists on the circuit formation surface of the semiconductor chip is mounted on the mounting substrate so that the angle formed by the mounting substrate has an inclination θ. It is electrically connected to the electrode part on the substrate. As a result, it is possible to reduce the height and density of the semiconductor module in the mounted state.

以下本発明を図示の実施の形態によって説明する。   The present invention will be described below with reference to the illustrated embodiments.

(実施の形態1)
図1(a)、(b)は、本発明の実施の形態1における複数の半導体装置209が実装基板210に実装された半導体モジュールを示す断面図及び斜視図であり、図2(a)、(b)は、半導体装置209の断面図及び斜視図であり、図3(a)、(b)及び図4(a)、(b)は、図1における複数実装された半導体装置209のうち、一個の半導体装置209を実装基板210に実装した状態を示す断面図及び斜視図であり、図6は、本実施の形態1の他の実施例を示す斜視図である。
(Embodiment 1)
FIGS. 1A and 1B are a cross-sectional view and a perspective view showing a semiconductor module in which a plurality of semiconductor devices 209 according to the first embodiment of the present invention are mounted on a mounting substrate 210. FIGS. FIG. 3B is a cross-sectional view and a perspective view of the semiconductor device 209. FIGS. 3A, 3B, 4A, and 4B are views of a plurality of mounted semiconductor devices 209 in FIG. FIG. 6 is a cross-sectional view and a perspective view showing a state where one semiconductor device 209 is mounted on the mounting substrate 210, and FIG. 6 is a perspective view showing another example of the first embodiment.

図2(a)に示す半導体装置209は、大略すると半導体チップ211、突起電極212、保護部材213により構成されている。半導体チップ211は高速メモリとして機能するものであり、かつそのメモリ容量は例えば1チップで128Mb以上を実現できる高容量のメモリチップである。この半導体チップ211の片側はメモリ回路が形成された回路形成面となっており、また回路形成面の一辺(同図における下辺)には、複数の接続部215が並設された構成とされている。この接続部215は電極パッドであり、その上部には各々突起電極212が形成されている。   A semiconductor device 209 shown in FIG. 2A is roughly composed of a semiconductor chip 211, a protruding electrode 212, and a protective member 213. The semiconductor chip 211 functions as a high-speed memory, and the memory capacity thereof is a high-capacity memory chip that can realize, for example, 128 Mb or more with one chip. One side of the semiconductor chip 211 is a circuit formation surface on which a memory circuit is formed, and a plurality of connection portions 215 are arranged in parallel on one side (the lower side in the figure) of the circuit formation surface. Yes. The connection part 215 is an electrode pad, and a protruding electrode 212 is formed on each of the connection parts 215.

突起電極212は、半導体チップ211の回路形成面上で半導体チップ211の接続部215が存在する一辺に直交する方向と実装基板210のなす角が傾きθを有するように、基板上の電極部214と電気的に接続されている。これにより実装状態における半導体モジュールの低背化及び高密度化を図ることができる。さらに外部接続端子を介さず、突起電極212と電極部214を電気的に接続しているので、電送系路による損失が少なくなる。また図11に示す積層型の半導体モジュールと比べて各電極部214の離間距離が短くなる。したがって処理速度の高速化も実現できる。なお、本発明は低背化、高密度化及び処理速度の高速化を実現するのに前記傾きθが鋭角において効果を有する。すなわち、傾きθが鋭角以外だと、突起電極212と電極部214を直接、電気的に接続が困難となるからである。さらに、半導体モジュールを包含する外部パッケージの制約と実装密度の関係から前記傾きθを2度〜10度に設定することが望ましい。なお突起電極212は、ワイヤーボンデイング、メッキ法などで作製できる。   The protruding electrode 212 has an electrode portion 214 on the substrate such that the angle formed by the mounting substrate 210 and the direction perpendicular to one side where the connection portion 215 of the semiconductor chip 211 exists on the circuit formation surface of the semiconductor chip 211 has an inclination θ. And are electrically connected. As a result, it is possible to reduce the height and density of the semiconductor module in the mounted state. Furthermore, since the protruding electrode 212 and the electrode portion 214 are electrically connected without using an external connection terminal, loss due to the power transmission path is reduced. Further, the distance between the electrode portions 214 is shorter than that of the stacked semiconductor module shown in FIG. Therefore, the processing speed can be increased. In the present invention, the inclination θ is effective at an acute angle in order to realize a low profile, a high density, and a high processing speed. That is, when the inclination θ is other than an acute angle, it is difficult to directly electrically connect the protruding electrode 212 and the electrode portion 214. Furthermore, it is desirable to set the inclination θ to 2 ° to 10 ° from the relationship between the restrictions on the external package including the semiconductor module and the mounting density. The protruding electrode 212 can be manufactured by wire bonding, plating, or the like.

保護部材213は、上記構成とされた半導体チップ211の回路形成面に配設されている。この保護部材213は、例えばポリイミド系樹脂、エポキシ系樹脂、シリコーン系樹脂等の絶縁性を有した液状コーティング材を、例えばスピンコート、ポッティング、スクリーン印刷、或いはトランスファーモールド等を用いて形成を適用することが可能である。なお、液状コーティング材でなく、絶縁性シート、テープを用いることもできる。液状コーティングまたは、シート、テープは、全面に必要ではなく、部分的にあってもよい。中央にのみ形成すると、材料費が安くできる。一方、半導体チップ211のコーナー部分に設けると、コーナーの欠けなども防ぐことができる。   The protection member 213 is disposed on the circuit formation surface of the semiconductor chip 211 configured as described above. The protective member 213 is formed by applying a liquid coating material having an insulating property such as polyimide resin, epoxy resin, or silicone resin by using, for example, spin coating, potting, screen printing, or transfer molding. It is possible. In addition, an insulating sheet or a tape can be used instead of the liquid coating material. The liquid coating, sheet, or tape is not necessary on the entire surface, and may be partially present. If it is formed only in the center, the material cost can be reduced. On the other hand, when the semiconductor chip 211 is provided at a corner portion, corner breakage or the like can be prevented.

本実施例における保護部材213は、前記した接続部215が形成されている部位には配設されてはおらず、よって接続部215の形成位置は半導体チップ211が露出した露出部216とされている。しかるに、保護部材213は、少なくとも回路形成面の回路が形成された部位は確実に被覆し保護する構成とされている。これにより、半導体チップ211において最もデリケートな部分である回路形成領域は保護部材213により保護されているため、半導体装置209の信頼性を向上させることができる。   The protective member 213 in the present embodiment is not disposed at the portion where the connection portion 215 is formed, and therefore the connection portion 215 is formed at the exposed portion 216 where the semiconductor chip 211 is exposed. . However, the protection member 213 is configured to reliably cover and protect at least a portion of the circuit formation surface where the circuit is formed. Thereby, since the circuit formation region which is the most sensitive part in the semiconductor chip 211 is protected by the protection member 213, the reliability of the semiconductor device 209 can be improved.

続いて、上記構成とされた半導体装置209の実装形態について説明する。図3(a)は、半導体装置209を実装基板210の実装位置に、半導体チップ211の回路形成面上で半導体チップ211の接続部215が存在する一辺に直交する方向と、実装基板210のなす角が傾きθを有するように実装し、半導体チップ211の接続部215、突起電極212、実装基板210の接続部215を覆うように封止樹脂217によって封止した実装形態を示している。この接続方法としては、例えば、異方性導電性膜、導電性接着剤を用いた圧設工法や、熱圧着工法を適用することができる。   Subsequently, a mounting form of the semiconductor device 209 having the above-described configuration will be described. FIG. 3A shows the mounting substrate 210 at a position where the semiconductor device 209 is mounted on the mounting substrate 210 and a direction perpendicular to one side where the connection portion 215 of the semiconductor chip 211 exists on the circuit formation surface of the semiconductor chip 211. A mounting form is shown in which the corners are mounted with an inclination θ and sealed with a sealing resin 217 so as to cover the connection portion 215 of the semiconductor chip 211, the protruding electrode 212, and the connection portion 215 of the mounting substrate 210. As this connection method, for example, a pressing method using an anisotropic conductive film or a conductive adhesive or a thermocompression bonding method can be applied.

実装基板210は、半導体装置209に配設されている各々の突起電極212と電気的に接続する電極部214が配設されている。さらに各々の電極部214から配線が実装基板210になされている。本実装形態では、任意の基板を選択することが可能である。具体的には、実装基板210として、プリント配線基板、フレキシブル回路基板、セラミック回路基板、Tabテープ等の種々の基板を用いることが可能であり、また基板構造としては単層配線基板を用いることも、また多層配線基板を用いることも可能である。   The mounting substrate 210 is provided with electrode portions 214 that are electrically connected to the protruding electrodes 212 provided in the semiconductor device 209. Furthermore, wiring is made from each electrode part 214 to the mounting substrate 210. In this mounting form, any board can be selected. Specifically, various substrates such as a printed wiring board, a flexible circuit board, a ceramic circuit board, and a Tab tape can be used as the mounting board 210, and a single-layer wiring board can be used as the board structure. A multilayer wiring board can also be used.

封止樹脂217は、例えばエポキシ系樹脂等の絶縁性を有した液状封止材を適用することができる。また封止樹脂217を供給する方法としては、例えば注入を用いることが可能である。半導体チップ211の接続部215、突起電極212、実装基板210の露出部216を覆うように封止樹脂217によって封止することによって、半導体チップ211の回路形成面の全てが被覆された状態となり、半導体装置209の信頼性をさらに向上させることが可能となる。また、半導体チップ211と実装基板210の接続部215を機械的に接続することとなり、封止樹脂217がない場合と比べ、突起電極212にかかる応力が分散され、機械的強度を増すことができる。   As the sealing resin 217, for example, a liquid sealing material having insulation properties such as an epoxy resin can be applied. As a method for supplying the sealing resin 217, for example, injection can be used. By sealing with the sealing resin 217 so as to cover the connection portion 215 of the semiconductor chip 211, the protruding electrode 212, and the exposed portion 216 of the mounting substrate 210, the circuit formation surface of the semiconductor chip 211 is entirely covered, The reliability of the semiconductor device 209 can be further improved. In addition, the connection portion 215 between the semiconductor chip 211 and the mounting substrate 210 is mechanically connected, so that stress applied to the protruding electrode 212 is dispersed and mechanical strength can be increased as compared with the case where the sealing resin 217 is not provided. .

続いて、半導体装置209の別の実施形態について説明する。図4(a)は、半導体装置209と実装基板210との間に、半導体装置209または実装基板210に加わる力によって、半導体装置209を支える半導体支持部材321を配設したことを特徴とする実装形態を示している。この半導体支持部材321は、例えば熱可塑性を有し接着剤として機能する樹脂を用いる構成としてもよく、また絶縁性材料により半導体支持部材321を形成し、これを接着剤で半導体装置209及び実装基板210に接着する構成としてよい。   Next, another embodiment of the semiconductor device 209 will be described. FIG. 4A shows a mounting in which a semiconductor support member 321 that supports the semiconductor device 209 is disposed between the semiconductor device 209 and the mounting substrate 210 by a force applied to the semiconductor device 209 or the mounting substrate 210. The form is shown. The semiconductor support member 321 may be configured to use, for example, a resin having thermoplasticity and functioning as an adhesive. The semiconductor support member 321 is formed of an insulating material, and the semiconductor support member 321 is formed of an adhesive with the semiconductor device 209 and the mounting substrate. It may be configured to adhere to 210.

かかる構成によれば、図3(a)に示す実施形態に比べ、半導体装置209の実装時や、半導体モジュールの実環境での使用時に突起電極212に加わる応力がさらに分散され、機械的強度を向上させることが可能となる。なお半導体支持部材321の形状は、応力の関係から図5のような形状にするとより一層機械的強度を高めることが可能となる。図5では、半導体支持部材321の形状が弓矢状、または、凹状の外形をもつ構造となっているので、応力の緩和に効果がある。図4(a)と図5とを比較すると、半導体装置209に圧力がかかると、図4(a)の場合、直接、バンプ212に力がかかり、接続安定性を損ねる。一方、図5の場合、力が緩和させ、接続安定性がよい。   According to such a configuration, compared to the embodiment shown in FIG. 3A, the stress applied to the protruding electrode 212 is further dispersed when the semiconductor device 209 is mounted or when the semiconductor module is used in an actual environment, and the mechanical strength is increased. It becomes possible to improve. Note that the shape of the semiconductor support member 321 can be further increased in mechanical strength if the shape is as shown in FIG. 5 due to stress. In FIG. 5, since the shape of the semiconductor support member 321 has a bow and arrow shape or a concave outer shape, it is effective for stress relaxation. Comparing FIG. 4A and FIG. 5, when pressure is applied to the semiconductor device 209, in the case of FIG. 4A, force is directly applied to the bumps 212 and connection stability is impaired. On the other hand, in the case of FIG. 5, the force is relaxed and the connection stability is good.

図1(a)に示す実施形態は、図2(a)に示す半導体装置209を少なくとも2個、実装基板210に並設して上記に示した方法で実装し、構成したものである。まず、図4(a)に示す実装形態のように、半導体支持部材321を配設し、半導体装置209を実装する。続いて図3(a)に示す実装形態のように半導体装置209を実装する。この図3(a)に示す実装形態を所定の回数繰り返すことによって、本実装形態を実現する。このように、複数の半導体装置209を傾けて併設し実装する構成とすることにより、各々の基板上の各電極部214の離間距離が短くなるため処理速度が高速になり、かつ全体形状を小さく維持することが可能となる。したがって、高容量で高速の半導体モジュールを実現することができる。   In the embodiment shown in FIG. 1A, at least two semiconductor devices 209 shown in FIG. 2A are arranged in parallel on the mounting substrate 210 and mounted by the method described above. First, as in the mounting form shown in FIG. 4A, the semiconductor support member 321 is disposed, and the semiconductor device 209 is mounted. Subsequently, the semiconductor device 209 is mounted as in the mounting form shown in FIG. This mounting mode is realized by repeating the mounting mode shown in FIG. 3A a predetermined number of times. In this way, by adopting a configuration in which a plurality of semiconductor devices 209 are inclined and mounted, the separation distance between the electrode portions 214 on each substrate is shortened, so that the processing speed is increased and the overall shape is reduced. Can be maintained. Therefore, a high-capacity and high-speed semiconductor module can be realized.

また、各々の半導体装置209の実装前、既に実装基板210に実装されている半導体チップ211の非回路形成面、またはこれから実装する半導体装置209の保護部材表面に接着剤を塗布する、または、各々の半導体装置209が実装された後、接着剤を注入し、各々の半導体装置209を固定する構成とすることによって、機械的強度を増すことができる。さらに保護部材213の材料に接着性を有する材料を用いることによって、接着剤を用いて接着する構成に比べて、半導体装置209の実装密度を向上させるとともに、部品点数の削減及び組立作業の簡略化を図ることができる。さらに、封止樹脂217は、全ての半導体装置209を実装した後に、一括して注入することにより、組立作業の簡略化及び半導体モジュールを製造する時間を短縮することができる。   Further, before the mounting of each semiconductor device 209, an adhesive is applied to the non-circuit forming surface of the semiconductor chip 211 already mounted on the mounting substrate 210, or the surface of the protective member of the semiconductor device 209 to be mounted, or After the semiconductor device 209 is mounted, mechanical strength can be increased by injecting an adhesive and fixing each semiconductor device 209. Further, by using a material having adhesiveness as the material of the protective member 213, the mounting density of the semiconductor device 209 is improved as compared with the configuration in which the adhesive is used, and the number of components is reduced and the assembly work is simplified. Can be achieved. Further, the sealing resin 217 can be injected at a time after all the semiconductor devices 209 are mounted, thereby simplifying the assembly work and reducing the time for manufacturing the semiconductor module.

なお、本実施の形態において、半導体チップ211の接続部215に突起電極212を形成し、圧接工法や熱圧着工法によって実装基板210に実装する構成としたが、ハンダ材料を半導体チップ211の接続部215、または、実装基板210の電極部214に、例えば印刷、または塗布によってハンダを供給し、熱プロセスを加え、ハンダ付けを行うことによって実装することも可能である。   In the present embodiment, the protruding electrode 212 is formed on the connection portion 215 of the semiconductor chip 211 and mounted on the mounting substrate 210 by a pressure welding method or a thermocompression bonding method. However, the solder material is connected to the connection portion of the semiconductor chip 211. For example, it is possible to mount solder by supplying solder to the electrode part 214 of the mounting substrate 210 by printing or coating, applying a thermal process, and soldering.

なお、本実施の形態において、半導体装置209の突起電極212の配設されている一辺に直交する一端面(半導体チップ端面208)が同一平面上になるように配設した構成としたが、図6に示す実施形態のように、半導体チップ端面208が同一平面上にない構成とすることも可能である。図6では、半導体装置209が、実装基板210の幅の約半分の大きさで、並列に配列されている。実装基板210に対して、小さい半導体装置209を配置するので、実装基板210上を空きスペースなく、半導体装置209を配置できる。なお、大きさは半分でなくとも小さくてもよい。実装基板210の幅の整数分の1であれば効率的に配置できる。   In the present embodiment, one end face (semiconductor chip end face 208) orthogonal to one side where the protruding electrodes 212 of the semiconductor device 209 are arranged is arranged on the same plane. As in the embodiment shown in FIG. 6, the semiconductor chip end face 208 may not be on the same plane. In FIG. 6, the semiconductor devices 209 are arranged in parallel so as to be about half the width of the mounting substrate 210. Since the small semiconductor device 209 is disposed with respect to the mounting substrate 210, the semiconductor device 209 can be disposed on the mounting substrate 210 without a free space. Note that the size may not be half but small. If it is 1 / integer of the width | variety of the mounting substrate 210, it can arrange | position efficiently.

(実施の形態2)
図7は、本発明の実施の形態2における複数の半導体装置209が実装基板210に実装された半導体モジュールを示す断面図である。図7において、図1〜図4と同じ構成要素については同じ符号を使い、説明を省略する。
(Embodiment 2)
FIG. 7 is a cross-sectional view showing a semiconductor module in which a plurality of semiconductor devices 209 according to Embodiment 2 of the present invention are mounted on a mounting substrate 210. 7, the same components as those in FIGS. 1 to 4 are denoted by the same reference numerals, and the description thereof is omitted.

図7の実施形態は、実装基板210の各々の面に少なくとも2個の半導体装置209を実装基板210の両面に配設した構成を示している。まず、図1(a)に示す実装形態によって実装基板210の一方の面に、少なくとも2枚の半導体装置209を実装する。続いて、実装基板210の他方の面に、少なくとも2枚の半導体装置209を同様に実装することによって、本実装形態を実現する。   The embodiment of FIG. 7 shows a configuration in which at least two semiconductor devices 209 are disposed on both surfaces of the mounting substrate 210 on each surface of the mounting substrate 210. First, at least two semiconductor devices 209 are mounted on one surface of the mounting substrate 210 by the mounting form shown in FIG. Subsequently, at least two semiconductor devices 209 are similarly mounted on the other surface of the mounting substrate 210, thereby realizing this mounting form.

かかる構成によれば、図11の実装形態による半導体装置209を積層した構成よりも、実装基板1枚分の低背化が図れるとともに、積層した半導体装置間の実装回路を電気的に接続するための部品及び工程が不要となる。   According to such a configuration, the height of one mounting substrate can be reduced compared to the configuration in which the semiconductor devices 209 according to the mounting form of FIG. 11 are stacked, and the mounting circuit between the stacked semiconductor devices is electrically connected. This eliminates the need for parts and processes.

なお、図7に示す実装形態において、実装基盤210の上の半導体装置209と実装基板210の下の半導体装置209が平行となるように示しているが、半導体装置209と実装基板210の傾きθが、上下で異なる構成を選択してもよい。これにより基板の両面の実装密度を調整することが可能となり、外部パッケージ411の制約が基板の両面で異なる場合にも対応することができる。   7, the semiconductor device 209 on the mounting substrate 210 and the semiconductor device 209 below the mounting substrate 210 are shown to be parallel to each other, but the inclination θ between the semiconductor device 209 and the mounting substrate 210 is illustrated. However, different configurations may be selected on the upper and lower sides. As a result, it is possible to adjust the mounting density on both sides of the substrate, and it is possible to cope with the case where the constraints of the external package 411 are different on both sides of the substrate.

また図8(a)(b)に示す外部端子410がついた実施形態の場合、図8(b)のように半導体装置209を外部端子410と反対方向に傾けるとさらによい。すなわち外部パッケージ411の制約から外部端子410と同じ方向に傾けるよりも、電極部214と外部端子410との離間距離a−a´が短くなるため、より一層の処理速度の高速化が望まれる。   8A and 8B, it is further preferable that the semiconductor device 209 is tilted in the opposite direction to the external terminal 410 as shown in FIG. 8B. In other words, the distance aa ′ between the electrode part 214 and the external terminal 410 is shorter than the inclination in the same direction as that of the external terminal 410 due to the restriction of the external package 411. Therefore, further increase in processing speed is desired.

(実施の形態3)
図9は、本発明の実施の形態3における複数の半導体装置209が実装基盤210に実装された半導体モジュールを示す斜視図である。図9において、図1〜図4と同じ構成要素については同じ符号を用い、説明を省略する。
(Embodiment 3)
FIG. 9 is a perspective view showing a semiconductor module in which a plurality of semiconductor devices 209 according to the third embodiment of the present invention are mounted on a mounting board 210. 9, the same components as those in FIGS. 1 to 4 are denoted by the same reference numerals, and the description thereof is omitted.

図9の実施形態は、隣り合う半導体装置209の実装位置を突起電極212の配設方向に、突起電極212の間隔の4分の1から4分の3までの間で、ずらして配設した構成を示している。   In the embodiment of FIG. 9, the mounting positions of the adjacent semiconductor devices 209 are shifted in the arrangement direction of the bump electrodes 212 from one quarter to three quarters of the gap between the bump electrodes 212. The configuration is shown.

かかる構成によれば、半導体チップ211に配設されている突起電極212の半導体チップ平面に水平な断面形状は円状の形状であるため、隣り合う半導体装置209の実装位置を突起電極212の配設方向に、突起電極212の間隔の4分の1から4分の3までの間で、ずらして配設することにより、図1(a)に示す実装形態に比べ各電極部214の離間距離が縮まる。したがって、突起電極212の大きさに制約されずに、より一層の高密度化及び処理速度の高速化を実現することができる。突起電極212の大きさを小さくすると、接続の安定性に欠ける。また、突起電極212を小さく形成する困難差もある。   According to this configuration, the protruding electrode 212 disposed on the semiconductor chip 211 has a circular cross-sectional shape in the plane of the semiconductor chip, so that the mounting positions of the adjacent semiconductor devices 209 are arranged on the protruding electrode 212. In the installation direction, the distance between the electrode portions 214 is smaller than that of the mounting form shown in FIG. Shrinks. Therefore, it is possible to achieve higher density and higher processing speed without being restricted by the size of the protruding electrode 212. If the size of the protruding electrode 212 is reduced, the connection stability is lacking. Further, there is a difference in difficulty in forming the protruding electrode 212 small.

なお、規格化されたメモリモジュール、メモリカードにおいては、その大きさが規格化されており、上記記載の構造は、特に有効である。メモリカードでは、メモリIC以外に、コンデンサー、抵抗、制御IC、外部接続電極が必要であり、これらの部材を上記の構造の空き空間に設置すればよい。たとえば、図10に示す構造にすれば、高密度に実装できる。実装基板210の面に対して、斜めに実装された半導体装置209とその半導体装置209と実装基板210の間に、制御IC603、または、コンデンサー601や抵抗602を設置し、外部端子410を実装基板210の裏面に設けるととてもコンパクトな構造になる。外部パッケージ411に、半導体装置209を斜めに実装する場合、その間をなす角度θは、約2度以上10度以下になる。好ましくは、3度以上7度以下がよい。コンパクトに半導体装置209が、外部パッケージ411内に設置できる。   Note that the standardized memory modules and memory cards are standardized in size, and the above-described structure is particularly effective. In the memory card, in addition to the memory IC, a capacitor, a resistor, a control IC, and an external connection electrode are necessary, and these members may be installed in an empty space having the above structure. For example, the structure shown in FIG. 10 can be mounted with high density. A control IC 603 or a capacitor 601 or a resistor 602 is installed between the semiconductor device 209 mounted obliquely with respect to the surface of the mounting substrate 210, and between the semiconductor device 209 and the mounting substrate 210, and the external terminals 410 are connected to the mounting substrate. When it is provided on the back surface of 210, the structure becomes very compact. When the semiconductor device 209 is obliquely mounted on the external package 411, the angle θ formed therebetween is about 2 degrees or more and 10 degrees or less. Preferably, it is 3 degrees or more and 7 degrees or less. The semiconductor device 209 can be installed in the external package 411 in a compact manner.

メモリカードはこのタイプ限定されるわけでなく、外部パッケージ411が樹脂で完全にモールドされているものなどいろいろなタイプのものに適用できる。また、半導体チップ211の上面で、外部パッケージ411との間の空間を利用して、制御IC603、コンデンサー601、抵抗602などを設置してもよい。また、この空間をデザインのため、カット、削除してもよい。または、逆に、この部分の厚みを厚くして、外部端子410と、対応すべき他の機器の端子との接触が安定するようにしてもよい。   The type of the memory card is not limited to this type, and it can be applied to various types such as those in which the external package 411 is completely molded with resin. In addition, a control IC 603, a capacitor 601, a resistor 602, and the like may be installed on the upper surface of the semiconductor chip 211 using a space between the external package 411. Further, this space may be cut or deleted for design. Or, conversely, the thickness of this portion may be increased so that the contact between the external terminal 410 and the terminal of another device to be supported is stabilized.

本発明にかかる半導体モジュールにおいて、半導体装置を実装基板に半導体チップの回路形成面上で接続部が存在する一辺に直交する方向と実装基板のなす角が傾きθを有するように、基板上の電極部と電気的に接続させている。これにより実装状態における半導体モジュールの低背化及び高密度化を実現することができ、半導体装置を実装する空間が限られたメモリーカード等の高容量化の用途にも適用できる。   In the semiconductor module according to the present invention, the electrode on the substrate is arranged such that the angle formed by the mounting substrate and the direction perpendicular to one side where the connection portion exists on the circuit formation surface of the semiconductor chip is on the mounting substrate and the mounting substrate has an inclination θ. It is electrically connected to the part. As a result, it is possible to reduce the height and increase the density of the semiconductor module in the mounted state, and it can also be applied to high capacity use such as a memory card in which a space for mounting the semiconductor device is limited.

本発明の実施の形態1における複数の半導体装置209が実装された構成を示す(a)断面図(b)斜視図(A) Cross-sectional view (b) Perspective view showing a configuration in which a plurality of semiconductor devices 209 according to the first embodiment of the present invention are mounted 半導体装置209を示す(a)断面図(b)斜視図(A) Cross-sectional view (b) Perspective view showing semiconductor device 209 図1における複数実装された半導体装置209のうち、一個の半導体装置209を実装基板210に実装した状態を示す(a)断面図(b)斜視図FIG. 1A is a sectional view showing a state in which one semiconductor device 209 is mounted on a mounting substrate 210 among a plurality of mounted semiconductor devices 209 in FIG. 図1における複数実装された半導体装置209のうち、一個の半導体装置209を実装基板210に実装した状態を示す(a)断面図(b)斜視図FIG. 1A is a sectional view showing a state in which one semiconductor device 209 is mounted on a mounting substrate 210 among a plurality of mounted semiconductor devices 209 in FIG. 図4における別の実施の形態の半導体モジュールの断面図Sectional drawing of the semiconductor module of another embodiment in FIG. 本発明の実施の形態1の他の実施例を示す斜視図The perspective view which shows the other Example of Embodiment 1 of this invention. 本発明の実施の形態2における複数の半導体装置209を実装基板210の両面に実装した構成を示す断面図Sectional drawing which shows the structure which mounted the some semiconductor device 209 in Embodiment 2 of this invention on both surfaces of the mounting substrate 210 本発明の実施の形態2の他の実施例で、半導体装置209が外部端子410と(a)対向しないように傾いた断面図(b)対向するように傾いた断面図In another example of the second embodiment of the present invention, the semiconductor device 209 is (a) a sectional view inclined so as not to oppose the external terminal 410 (b) a sectional view inclined so as to oppose it. 本発明の実施の形態3における複数の半導体装置209が実装基盤210に実装された半導体モジュールを示す斜視図The perspective view which shows the semiconductor module with which the several semiconductor device 209 in Embodiment 3 of this invention was mounted in the mounting board | substrate 210. FIG. 本願発明のメモリモジュールの断面図Sectional view of the memory module of the present invention 従来の半導体モジュールの縦断面図Vertical section of a conventional semiconductor module 従来の他の半導体モジュールの縦断面図Vertical sectional view of another conventional semiconductor module

符号の説明Explanation of symbols

209 半導体装置
210 実装基板
211 半導体チップ
212 突起電極
213 保護部材
214 電極部
215 半導体チップ211の接続部
216 実装基板210の露出部
217 封止樹脂
321 半導体支持部材
410 外部端子
411 外部パッケージ
510 インタポーザ基板
512 スペーサ基板
513 ベース基板
209 Semiconductor device 210 Mounting substrate 211 Semiconductor chip 212 Protruding electrode 213 Protective member 214 Electrode portion 215 Connection portion of semiconductor chip 211 216 Exposed portion of mounting substrate 210 217 Sealing resin 321 Semiconductor support member 410 External terminal 411 External package 510 Interposer substrate 512 Spacer substrate 513 Base substrate

Claims (1)

回路形成面を有する半導体チップと前記半導体チップ上に設けられた複数の突起電極とからなる半導体装置を、複数の電極部を備えた基板上に前記回路形成面が対向するように傾けて、前記複数の突起電極と前記複数の電極部を電気的に接続した半導体モジュールであって、
前記半導体装置を複数個並設し、隣り合う前記半導体装置を、前記複数の突起電極の配設方向に前記複数の突起電極の間隔の4分の1から4分の3までの間でずらして配設したことを特徴とする半導体モジュール。
The semiconductor device comprising a plurality of protruding electrodes provided to the semiconductor chip on the semiconductor chip having a circuit forming surface, the circuit forming surface is inclined so as to face the substrate having a plurality of electrode portions, wherein A semiconductor module in which a plurality of protruding electrodes and the plurality of electrode portions are electrically connected ,
A plurality of the semiconductor devices are arranged side by side, and the adjacent semiconductor devices are shifted in a direction in which the plurality of protruding electrodes are arranged from one-fourth to three-fourths of the interval between the plurality of protruding electrodes. A semiconductor module characterized by being disposed.
JP2005058776A 2005-03-03 2005-03-03 Semiconductor module Expired - Fee Related JP4674477B2 (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01217996A (en) * 1988-02-26 1989-08-31 Hitachi Ltd Electronic device
JPH06291248A (en) * 1993-04-05 1994-10-18 Toshiba Corp Semiconductor device
JPH09326543A (en) * 1996-06-04 1997-12-16 Hitachi Ltd Electronic part
JPH11186489A (en) * 1997-12-17 1999-07-09 Hitachi Ltd Semiconductor device and electronic device using it
JP2001035992A (en) * 1999-07-22 2001-02-09 Seiko Epson Corp Manufacture of semiconductor device and semiconductor device, and semiconductor substrate, electronic device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01217996A (en) * 1988-02-26 1989-08-31 Hitachi Ltd Electronic device
JPH06291248A (en) * 1993-04-05 1994-10-18 Toshiba Corp Semiconductor device
JPH09326543A (en) * 1996-06-04 1997-12-16 Hitachi Ltd Electronic part
JPH11186489A (en) * 1997-12-17 1999-07-09 Hitachi Ltd Semiconductor device and electronic device using it
JP2001035992A (en) * 1999-07-22 2001-02-09 Seiko Epson Corp Manufacture of semiconductor device and semiconductor device, and semiconductor substrate, electronic device

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