JP2008160074A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of writing and erasing data with a low voltage, and to provide a method of manufacturing the semiconductor device. <P>SOLUTION: There are provided: an Si layer 5 formed on an Si substrate 1 via an insulating film 3; an Si layer 9 formed on the Si layer 5 via an insulating film 7; a PMOS 20 formed at least on one side face of the Si layer 5; and an NMOS 30 formed at least on one side face of the Si layer 9. The PMOS 20 and the NMOS 30 have common floating gates 17, 13. The common floating gate 13 is provided successively from the side face of the Si layer 5 to that of the Si layer 9, thus writing data to and erasing data from the common floating gate 13 by supplying two carriers, namely an electron and a hole. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and, for example, to a technology capable of executing data reading and data writing and erasing at a low voltage.

As shown in Patent Documents 1 and 2, a conventional nonvolatile memory has a planar MOS structure, and a floating gate surrounded by a SiO ₂ insulating film is formed between a control gate and a silicon substrate (MOSFET channel). It had been. In the nonvolatile memory having such a structure, data is written by applying a large positive voltage of several tens of volts to the source / drain or body to the control gate and injecting electrons into the floating gate. . Further, data is erased by applying a large negative voltage of several tens of volts to the source / drain or body to the control gate and extracting electrons from the floating gate.
JP 2006-186300 A International Publication No. 2004/084314 Pamphlet JP 2005-327796 A JP 2005-322830 A T.A. Sakai et al. “Separation by Bonding Si Islands (SBSI) for LSI Applications”, Second International SiGe Technology and Device Meeting, Meeting Abstract, pp. 230-231, May (2004)

  In the conventional technology, data is written to and erased from the floating gate using only one carrier called electrons, so it is necessary to apply large positive and negative voltages to the control gate during writing and erasing. there were. For this reason, for example, even in an LSI in which a low-voltage drive logic circuit and a non-volatile memory are mixedly mounted, a high-voltage drive circuit operation is required, resulting in an increase in manufacturing cost due to an increase in the chip area of the LSI and deterioration in reliability of the low-voltage drive circuit. There was a risk of doing so.

Even in the device structure of non-volatile memory, the gate insulating film cannot be thinned or the source / drain junction cannot be sharpened in order to ensure high voltage drive reliability. was there. Furthermore, the fact that the gate insulating film cannot be thinned or the source / drain junction cannot be abrupt means that the drain current of the MOS transistor is small when reading data. For this reason, the conventional technology has not been able to sufficiently read at a low voltage or at a high speed.
Therefore, the present invention has been made in view of such circumstances, and an object of the present invention is to provide a semiconductor device capable of executing data writing and erasing at a low voltage and a method for manufacturing the same.

  In order to solve the above-described problem, one of semiconductor devices according to the present invention includes a first semiconductor layer formed on a substrate via a first insulating film, and a second insulating film formed on the first semiconductor layer. A second semiconductor layer formed on the first semiconductor layer, a first conductivity type MOS transistor formed on at least one side surface of the first semiconductor layer, and a second conductivity layer formed on at least one side surface of the second semiconductor layer. The first conductivity type MOS transistor and the second conductivity type MOS transistor have a common charge storage layer and a common control gate, and the common charge storage layer includes The semiconductor device is continuously provided from the side surface on which the first conductive MOS transistor of one semiconductor layer is formed to the side surface of the second semiconductor layer on which the second conductive MOS transistor is formed. And it is characterized in that it is.

Here, the “first semiconductor layer” and the “second semiconductor layer” of the present invention are, for example, single crystal silicon (Si) layers. In the present invention, the “first conductivity type” is one of P type and N type, and the “second conductivity type” is the other of P type and N type. For example, when the first conductivity type is a P-type channel, the second conductivity type is an N-type channel. Furthermore, the “tunnel gate insulating film” of the present invention is an insulating film through which electrons or holes (holes) pass through due to the tunnel effect or energy exceeding the barrier. In the present invention, carriers are supplied from the first semiconductor layer or the second semiconductor layer to the charge storage layer through this insulating film. This insulating film has a film thickness of several nm in terms of SiO ₂ film thickness. Due to this thinness, not only hot carriers jump over the energy barrier, but also carriers are supplied to the charge storage layer by the FN tunnel effect due to the electric field between the source and gate electrodes. For this reason, in the present invention, this insulating film is called a tunnel gate insulating film. The “charge storage layer” of the present invention is a layer for storing carriers (electrons or holes) that have passed through the tunnel gate insulating film. For example, polysilicon (p-type or n-type impurities introduced) Poly-Si) or the like, or a metal thin film such as Ti, Ta, TiN, or TaN, or an insulating film such as Si ₃ N ₄ film, or a high-resistance semiconductor such as intrinsic Poly-Si. It is what is done.

  In order to solve the above-described problem, one of semiconductor devices according to the present invention includes a first semiconductor layer formed on a substrate via a first insulating film, and a second insulating film formed on the first semiconductor layer. A first semiconductor MOS transistor formed on at least one side surface of the first semiconductor layer, and a first semiconductor layer formed on at least one side surface and the upper surface of the second semiconductor layer. A two-conductivity type MOS transistor, wherein the first conductivity-type MOS transistor and the second conductivity-type MOS transistor have a common charge accumulation layer and a common control gate, and the common charge accumulation layer includes: From the side surface where the first conductivity type MOS transistor of the first semiconductor layer is formed, through the side surface where the second conductivity type MOS transistor of the second semiconductor layer is formed, And it is characterized in that is provided continuously over the said top surface of serial second semiconductor layer.

  One of the semiconductor devices according to the present invention includes a first semiconductor layer formed on a substrate via a first insulating film, and a second semiconductor layer formed on the first semiconductor layer via a second insulating film. And a first conductivity type MOS transistor formed on at least one side surface of the first semiconductor layer, and a second conductivity type MOS transistor formed on at least one side surface and the upper surface of the second semiconductor layer. The first conductivity type MOS transistor and the second conductivity type MOS transistor have a common charge storage layer and a common control gate, and the common charge storage layer is the first semiconductor layer of the first semiconductor layer. The conductive MOS transistor is continuously provided from the side surface where the MOS transistor is formed to the side surface where the second conductivity type MOS transistor of the second semiconductor layer is formed. The said upper surface of the second conductive layer is characterized in that not provided.

  Each of the semiconductor devices according to the present invention can supply electrons from an N-type MOS transistor and holes from a P-type MOS transistor to a common charge storage layer. By selectively supplying electrons and holes to the common charge storage layer, the potential can be changed, and the threshold voltage of each of the N-type and P-type MOS transistors can be controlled. For example, when writing data, electrons can be supplied to a common charge storage layer to change the threshold voltage of each MOS transistor. When erasing data, supply holes to the common charge storage layer to recombine the stored electrons with the holes (or cancel the negative charge of the trapped electrons with the positive charge of the holes). The threshold voltage of each MOS transistor can be returned to the state before writing.

  As described above, each of the semiconductor devices according to the present invention described above can realize writing and erasing with respect to the common charge storage layer by supplying two carriers of electrons and holes. Therefore, it is not necessary to apply a positive or negative voltage to the control gate at a high voltage when writing or erasing data, and the high voltage driving circuit can be omitted. Therefore, the chip area of the LSI can be reduced. At the same time, data can be written / erased by a low voltage source such as a battery.

  Further, in one of the semiconductor devices according to the present invention, the area of the channel of the second conductivity type MOS transistor is increased, so that the data writing operation and the erasing operation can be speeded up. Furthermore, according to the semiconductor device of the invention 3, the current controllability by the control gate of the second conductivity type MOS transistor is improved at the time of reading data, so that low voltage and high speed reading is possible.

  Each of the semiconductor devices according to the present invention includes both a P-channel MOS transistor and an N-channel MOS transistor, and these PN MOS transistors have a common control gate, so that the same timing is obtained. It is possible to switch on and off with. Therefore, the semiconductor devices according to the first to third aspects can be applied to, for example, a NOR circuit.

  Further, each of the semiconductor devices according to the present invention is characterized in that the drain of the first conductivity type MOS transistor and the drain of the second conductivity type MOS transistor are electrically connected. is there. With such a configuration, since the wiring connected to the drain can be shared between the drain of the first conductivity type MOS transistor and the second conductivity type MOS transistor, the area occupied by the wiring on the chip surface can be reduced. Is possible.

  One of the semiconductor devices according to the present invention is that a tunnel gate insulating film of a portion formed on the side surface of the second semiconductor layer of the second conductivity type MOS transistor is a portion of the second conductivity type MOS transistor. The second semiconductor layer is formed thinner than a portion of the gate insulating film formed on the upper surface.

  One of the semiconductor devices according to the present invention is a tunnel gate of a portion formed on the side surface of the second semiconductor layer of the second conductivity type MOS transistor with respect to barrier energy generated by contact with the second semiconductor layer. The insulating film is formed of a film having a lower barrier energy than the gate insulating film of the portion formed on the upper surface of the second semiconductor layer of the second conductivity type MOS transistor. It is. Since the barrier energy of the tunnel insulating film is small, hot carriers with low energy can be injected into the charge storage layer. Accordingly, the drive voltage can be lowered, and carriers can be efficiently injected into the charge storage layer without being injected into the gate film formed on the upper surface.

  In the semiconductor device according to the present invention described above, the tunnel gate insulating film has carriers (electrons or holes) rather than the gate insulating film formed on the upper surface of the second semiconductor layer of the second conductivity type MOS transistor. Therefore, it becomes easy to move carriers to the floating gate through the tunnel gate insulating film when writing or erasing data.

  In order to solve the above-described problems, a method of manufacturing a semiconductor device according to the present invention includes a step of sequentially stacking a first sacrificial semiconductor layer, a first semiconductor layer, a second sacrificial semiconductor layer, and a second semiconductor layer on a semiconductor substrate. And sequentially etching the second semiconductor layer, the second sacrificial semiconductor layer, the first semiconductor layer, and the first sacrificial semiconductor layer to form a first groove penetrating each semiconductor layer; Forming a support for supporting the first semiconductor layer and the second semiconductor layer in the first groove; and after forming the support, the second semiconductor layer and the second sacrificial semiconductor. Etching a layer, the first semiconductor layer, and the first sacrificial semiconductor layer partially sequentially to form a second groove exposing a side surface of each semiconductor layer; and the first semiconductor layer and the second semiconductor The first sacrificial semiconductor layer and the first Etching the first sacrificial semiconductor layer and the second sacrificial semiconductor layer through the second groove under an etching condition in which the sacrificial semiconductor layer is more easily etched, thereby forming the semiconductor substrate and the first semiconductor layer. Forming a first cavity therebetween, forming a second cavity between the first semiconductor layer and the second semiconductor layer; forming a first insulating film in the first cavity; Forming a second insulating film in the second cavity, and forming the first insulating film and the second insulating film on the side surface of the first semiconductor layer facing the second groove. Forming a first conductivity type MOS transistor, and forming the second conductivity type MOS transistor on a side surface facing the second groove of the second semiconductor layer, and forming the first conductivity type MOS transistor And before In the step of forming the second conductivity type MOS transistor, a tunnel gate insulating film is formed on each of a side surface of the first semiconductor layer facing the second groove and a side surface of the second semiconductor layer facing the second groove. And forming a common charge storage layer from the side surface of the first semiconductor layer to the side surface of the second semiconductor layer so as to cover the tunnel gate insulating film, and covering the charge storage layer. A gate insulating film is formed from the side surface of the layer to the side surface of the second semiconductor layer, and then shared from the side surface of the first semiconductor layer to the side surface of the second semiconductor layer so as to cover the gate insulating film. The control gate is formed.

Here, as described above, the “first semiconductor layer” and the “second semiconductor layer” of the present invention are, for example, single-crystal Si layers. The “first sacrificial semiconductor layer” and the “second sacrificial semiconductor layer” are, for example, single-crystal silicon germanium (SiGe) layers.
According to the semiconductor device manufacturing method of the present invention described above, the semiconductor devices of Inventions 1 to 6 can be manufactured by applying the so-called SBSI method. Therefore, since writing and erasing with respect to the charge storage layer can be realized by supplying two carriers of electrons and holes, it is possible to provide a semiconductor device that suppresses an increase in chip area by low voltage driving.

Hereinafter, a semiconductor device and a manufacturing method thereof according to the present invention will be described.
1A and 1B are diagrams showing a configuration example of a nonvolatile memory 100 according to an embodiment of the present invention. FIG. 1A is a plan view, and FIG. 1B is a cross-sectional view taken along line XX ′ in FIG. FIG. 1C is a cross-sectional view taken along the line YY ′ of FIG. 1A. In FIG. 1A, the interlayer insulating film is not shown for easy understanding of the configuration example of the nonvolatile memory 100 in a plan view.

As shown in FIGS. 1A to 1C, in the nonvolatile memory 100, a first single crystal Si layer 5 is formed on an Si substrate 1 with an insulating film 3 interposed therebetween. A second single crystal Si layer 9 is formed thereon with an insulating film 7 interposed. The insulating films 3 and 7 are, for example, silicon oxide (SiO ₂ ) films. The single-crystal Si layers (hereinafter simply referred to as “Si layers”) 5 and 9 are elongate rectangular parallelepipeds arranged so as to be parallel to the XX ′ line, for example. It arrange | positions so that a center part may overlap by planar view. A P-type MOS field effect transistor (hereinafter simply referred to as “PMOS”) 20 is formed on both side surfaces of the Si layer 5, and an N-type MOS field effect is formed on both side surfaces and the upper surface of the Si layer 9. A transistor (hereinafter simply referred to as “NMOS”) 30 is formed. That is, the channel region of the PMOS 20 is on the side surfaces on both sides of the Si layer 5, and the channel region of the NMOS 30 is on the side surfaces on both sides and the upper surface of the Si layer.

Here, the PMOS 20 and the NMOS 30 are nonvolatile memory transistors, and have a common floating gate 13 and a common control gate 17. That is, in FIG. 1C, the floating gate 13 is continuously formed on the right side surface of the Si layers 5 and 9 via the tunnel gate insulating film 11. A floating gate 13 is continuously formed on the left side surface of the Si layers 5 and 9 via the tunnel gate insulating film 11. Here, the material film constituting the tunnel gate insulating film 11 may be a SiO ₂ film, but the band gap (that is, the energy difference between the conduction band Ec and the valence band Ev) is smaller than that of SiO ₂ . It is more preferable that the insulating film has a barrier energy (potential barrier) with Si smaller than that of SiO ₂ . Examples of the insulating film having a small barrier energy include a Si ₃ N ₄ film, a Ta ₂ O ₅ film, a BaTiO ₃ film, a ZrO ₂ film, a HfO film, a Y ₂ O ₃ film, and a ZrSiO ₂ film.

As described above, when the tunnel gate insulating film 11 is constituted by the Si ₃ N ₄ film or the like, carriers (electrons or holes) moving from the Si layers 5 and 9 to the floating gate 13 are compared with the SiO ₂ film. ), The voltage necessary for data writing and erasing can be reduced.
The floating gate 13 is made of, for example, a semiconductor film such as polysilicon (Poly-Si) doped with P-type or N-type impurities, or a metal thin film such as Ti, Ta, TiN, or TaN. The tunnel gate insulating film 11 and the gate insulating film 15 are electrically insulated from the surrounding conductive layers (that is, are electrically floating). Further, a control gate 17 is continuously formed outside the floating gate 13 through a gate insulating film 15. As shown in FIGS. 1A to 1C, the control gate 17 is formed so as to straddle the vicinity of the center of the Si layers 5 and 9 stacked on the Si substrate 1. Then, the source / drain (P +) of the PMOS 20 is formed in the portion of the Si layer 5 that is out of the control gate 17, and the source / drain (N−) of the NMOS 30 is in the portion of the Si layer 9 that is out of the control gate 17. Is formed.

  Thus, in the nonvolatile memory 100 according to the present embodiment, the Si layers 5 and 9 are stacked on the Si substrate 1 via the insulating films 3 and 7, and the side surfaces on both sides of the Si layers 5 and 9 are stacked. In addition, PMOS 20 and NMOS 30 which are nonvolatile memory transistors are formed. The PMOS 20 and the NMOS 30 have a common floating gate 13 and a common control gate 17.

  With such a structure, not only can electrons be supplied from the NMOS 30 to the floating gate 13, but also holes can be supplied from the PMOS 20, and the amount of electrons or holes supplied to the floating gate 13 can be changed. , The threshold voltages of the PMOS 20 and the NMOS 30 can be controlled. That is, data writing and erasing with respect to the floating gate 13 can be realized by supplying two carriers of electrons and holes.

The energy required for forming an electron-hole pair in Si is about 1.1 eV, and the energy required for electrons to jump from Si to SiO ₂ when Si and SiO ₂ are in contact with each other. Is about 3.2 eV. In addition, the energy required for holes to jump from Si to SiO ₂ in the above contact state is about 4.8 eV. Therefore, in the PMOS 20 and the NMOS 30, the voltage required for the data writing operation and the erasing operation may be about 4.8V at the maximum (Max) value. Further, when a tunnel insulating film having a lower potential barrier than SiO ₂ is used, the voltage required for data writing / erasing can be further reduced.

Furthermore, due to the presence of lucky carriers, there are holes that jump from Si to SiO ₂ at a voltage lower than 4.8 V, but a certain amount of current is required to shorten the writing time and erasing time. A driving voltage of about 3 to 5 V is appropriate. Further, the voltage Vcg applied to the control gate 17 is set to the drain potential of the NMOS 30 (that is, the source potential of the PMOS) when electrons are injected into the floating gate 13, and when the holes are injected into the floating gate 13, the voltage of the NMOS 30 is set. What is necessary is just to set to source potential (namely, drain potential of PMOS). According to such a setting, the maximum potential difference between the source, body, drain, and gate of both the PMOS 20 and the NMOS 30 does not exceed 5V.

  Further, even when the non-volatile memory 100 shown in FIGS. 1A to 1C is combined with a low voltage drive logic circuit to constitute an LSI, the maximum voltage is about 5 V. It is possible to greatly improve the problem that the cost increases and the reliability of the low voltage drive circuit deteriorates. Further, in the device structure of the nonvolatile memory 100, the gate insulating film can be made thinner and the source / drain junction can be made sharper, and the device can be reduced. In addition, by reducing the thickness of the gate insulating film and sharpening the source / drain junction, the drain current is improved, and low voltage reading and high speed reading are possible.

Next, in the nonvolatile memory 100 shown in FIGS. 1A to 1C, a data writing method, an erasing method, and a reading method will be described.
Data writing and erasing can be performed as follows. For example, when the power supply voltages are Vss (0 V) and Vdd (5 V) and the common gate voltage and common drain voltage of PN are set to Vdd, the NMOS 30 is turned on and the PMOS 20 is turned off. Here, the PN common gate voltage is a voltage applied to the control gate 17. With such a voltage setting, electrons flow from the source to the drain in the NMOS 30 and are accelerated by a high electric field, or electron-hole pairs are formed by impact ionization, and hot carriers are generated. Hot electrons cross the oxide / silicon barrier, are pulled by the control gate 17 to which Vdd is applied, and injected into the floating gate 13. At the same time, carriers are supplied to the floating gate through the tunnel film as an FN current by the electric field between the source and the control gate electrode.

  On the other hand, when the gate voltage common to PN and the drain voltage common to PN are set to Vss, the NMOS 30 is turned off and the PMOS 20 is turned on. Holes flow from the source to the drain in the PMOS 20 and are accelerated by a high electric field, or form electron / hole pairs by impact ionization to generate hot carriers. The hot hole is pulled by the control gate 17 to which Vss is applied, over the oxide / silicon barrier, and injected into the floating gate 13. At the same time, carriers are supplied to the floating gate through the tunnel film as an FN current by the electric field between the source and the control gate electrode. Data can be written and erased by such injection of electrons or holes.

  Data can be read as follows. For example, if the power supply voltages are Vss (0 V) and Vdd (3 to 5 V), and the PN common gate voltage and PN common drain voltage are set to the same potential as the source of the PMOS 20 (for example, Vdd / 2), Since the channel is turned off and there is no potential difference between the source and drain, no current flows through the PMOS 20. On the other hand, in the NMOS 30, a potential of Vdd / 2−Vss is applied between the source and the drain, and the same potential is applied between the control gate 17 and the source. For this reason, in the NMOS 30, when there are many electrons stored in the floating gate 13, the channel is turned off and no current flows. However, when there are few electrons stored in the floating gate 13 or holes are stored. The channel is turned on, and electrons flow from the source to the drain.

  As shown in FIGS. 1A to 1C, a portion of the NMOS 30 formed on the upper surface of the Si layer 9 (hereinafter, this portion is also referred to as “NMOS 30a”) is a common control gate 17. Is used as the gate electrode and the floating gate 13 is not provided, the current controllability by the control gate 17 of the entire NMOS 30 is improved when reading data, and low voltage and high speed reading is possible. . On the other hand, when the NMOS 30a has the floating gate 13 (that is, when the floating gate 13 is disposed between the control gate 17 and the upper surface of the Si layer 9), the channel of the N-type nonvolatile memory transistor is used. Since the area of the region increases, high-speed writing and erasing are possible.

Next, an example of a circuit that uses the two Si layers 5 and 9 stacked on the Si substrate 1 as Vdd and Vss lines will be described. FIG. 23 is a plan view showing a configuration example of a Divorbit line NOR Flash Memory (DiNOR) circuit 200 according to the embodiment of the present invention. FIG. 24 is a circuit diagram showing a configuration example of the DiNOR circuit 200. In the DiNOR circuit 200, the 1-bit memory cell includes the nonvolatile memory 100 shown in FIGS.

  That is, as shown in FIG. 23, Si layers 5 and 9 are laminated on an Si substrate via an insulating film, and these form a grid of grids extending in the X and Y directions in plan view. Yes. Further, a word line (W / L) 201 is arranged on the Si substrate 1 along the Y direction so as to be orthogonal to the portion of the Si layers 5 and 9 extending in the X direction in plan view. Yes. This word line (W / L) 201 corresponds to the common control gate 17 shown in FIGS. Further, a bit line (B / L) 203 is disposed on the Si substrate so as to pass directly above the portion of the Si layers 5 and 9 extending in the X direction.

In this example, the bit line 203 passes over the word line 201 through an insulating film. In this example, a common contact electrode 211 is formed on the PMOS drain (D) and the NMOS drain (D), and the PMOS and NMOS drains are connected to the bit line via the common contact electrode 211. 203. Further, the source (S) of the PMOS is drawn out on the insulating film by the contact electrode 213, and is connected to, for example, the power supply Vdd by wiring as shown in FIG. The source (S) of the NMOS is drawn out on the insulating film by the contact electrode 215, and is connected to the power source Vss, for example, by wiring as shown in FIG. In FIGS. 23 and 24, a portion surrounded by a two-dot chain line is a 1-bit memory cell, that is, a nonvolatile memory 100.
In this way, in the DiNOR circuit 200 shown in FIGS. 23 and 24, the two Si layers 5 and 9 stacked on the Si substrate are used as the Vdd and Vss lines, respectively. As a result, the drain (D) contact electrode 211 can be shared by PN, and the number of contacts can be reduced, so that the integration degree of the DiNOR circuit 200 can be increased.

Next, a method for manufacturing the nonvolatile memory 100 shown in FIGS. 1A to 1C will be described.
2 to 21 are views showing a method of manufacturing the nonvolatile memory 100 according to the embodiment of the present invention, and FIGS. 2A to 21A are X-- up to FIG. 1B. FIG. 2B to FIG. 21B are process diagrams corresponding to the YY ′ section up to FIG. 1C. Here, manufacturing the nonvolatile memory 100 shown in FIGS. 1A to 1C by applying the SBSI method will be described.

  First, in FIGS. 2A and 2B, a silicon buffer (Si-buffer) layer (not shown) is formed on the Si substrate 1, and a single-crystal SiGe layer 51 and a single-crystal Si layer 5 are formed thereon. A single crystal SiGe layer 53 and a single crystal Si layer 9 are sequentially stacked. These Si-buffer layer, SiGe layer 51, Si layer 5, SiGe layer 53, and Si layer 9 are continuously formed by, for example, an epitaxial growth method.

Next, as shown in FIGS. 3A and 3B, the Si layer 9 is thermally oxidized to form a SiO ₂ film 55 on the surface thereof. Then, a SiN film 57 is formed on the entire surface of the SiO ₂ film 55 by the CVD method. The SiN film 57 functions as an antioxidant film for preventing the Si layers 5 and 9 and the SiGe layers 51 and 53 from being oxidized, and as a stopper layer when performing CMP (Chemical Mechanical Polishing) in a later process. Also works. The method for forming the SiO ₂ film 55 is not limited to thermal oxidation, and may be formed by, for example, a CVD method.

Next, as shown in FIGS. 4A and 4B, the SiN film 57, the SiO ₂ film 55, the Si layer 9, and the SiGe layer 53 are partially and sequentially etched using a photolithography technique and an etching technique. . Thus, a shallow support hole h1 having the Si layer 5 as a bottom through the Si layer 9 and the SiGe layer 53 is formed in a region overlapping the element isolation region (that is, a region where the SOI structure is not formed) in plan view. . Next, as shown in FIGS. 5A and 5B, by using a photolithography technique and an etching technique, the Si layer 5 exposed at the bottom surface of the shallow support hole h1, and the SiGe layer 51 and Si under the Si layer 5 are exposed. -The buffer layer is partially etched sequentially. As a result, a deep support hole h2 having the Si substrate 1 as the bottom surface is formed through the Si layer 5 and the SiGe layer 51 in a region overlapping the element isolation region in plan view. In the etching process for forming the deep support hole h2, the etching may be stopped on the surface of the Si substrate 1, or the Si substrate 1 may be over-etched to form a recess. Hereinafter, for convenience of explanation, the shallow support hole h1 and the deep support hole h2 are collectively referred to as a support hole h.

Next, as shown in FIGS. 6A and 6B, a support film 59 is formed on the entire surface of the Si substrate 1 so as to fill the support hole h. The support film 59 is, for example, a silicon oxide (SiO ₂ ) film, and is formed by, for example, a CVD method. Next, as shown in FIGS. 7A and 7B, the support film 59, the SiN film 57, the SiO ₂ film 55, the Si layer 9, the SiGe layer 53, and the Si layer using a photolithography technique and an etching technique. 5, the SiGe layer 51 and the Si-buffer layer (not shown) are partially etched sequentially to form the support 60 from the support film 59, and the surface of the Si substrate 1, the Si layer 9, and the SiGe layer 53, a groove H exposing each side surface of the Si layer 5 and the SiGe layer 51 is formed. In the etching process for forming the groove H, the etching may be stopped on the surface of the Si substrate 1, or the Si substrate 1 may be over-etched to form a recess.

  Next, in FIGS. 7A and 7B, the hydrofluoric acid solution is brought into contact with the side surfaces of the Si layers 5 and 9 and the SiGe layers 51 and 53 through the grooves H to select the SiGe layers 51 and 53. Etch away. As a result, as shown in FIGS. 8A and 8B, a first cavity 61 is formed between the Si substrate 1 and the Si layer 5, and between the Si layer 5 and the Si layer 9. A second cavity 63 is formed. Here, in wet etching using a hydrofluoric acid solution, the etching rate of SiGe is larger than that of Si (that is, the etching selectivity to Si is large), so only the SiGe layer is etched while leaving the Si layers 5 and 9. And can be removed. After the formation of the cavities 61 and 63, the Si layer 9 is supported by the support body 60 on the upper surface and side surfaces thereof, and the side surface of the Si layer 5 is supported by the support body 60.

Next, in FIGS. 8A and 8B, the Si substrate 1 is cleaned with a diluted hydrofluoric acid (HF) solution. Then, the Si substrate 1 is placed in an oxidizing atmosphere such as oxygen (O ₂ ) or ozone (O ₃ ), and the Si substrate 1 is subjected to heat treatment in this state. As a result, as shown in FIGS. 9A and 9B, the surface oxidation of Si proceeds on the respective surfaces of the Si layers 5 and 9, the Si-buffer layer (not shown), and the Si substrate 1. The portions 61 and 63 are filled with the SiO ₂ film 65. Of the SiO ₂ film 65, the portions formed in the cavity 61 and on the surface of the Si substrate 1 become the insulating film 3 shown in FIGS. 1B and 1C and are formed in the cavity 63. This portion becomes the insulating film 7.

Next, as shown in FIGS. 10A and 10B, an SiN film 69 is formed on the entire upper surface of the Si substrate 1. The SiN film 69 is formed by, for example, a CVD method. Subsequently, the SiN film 69 is etched back using anisotropic dry etching. As a result, as shown in FIGS. 11A and 11B, the sidewalls 70 are formed on the side surfaces of the Si layers 5 and 9, the SiO ₂ film 55, the SiN film 57, and the groove 60 of the support 60. .

Next, as shown in FIGS. 12A and 12B, the Si substrate 1 is subjected to thermal oxidation to thicken the portion of the SiO ₂ film 65 exposed from under the sidewall 70. To do. At this time, the side surfaces of the Si layers 5 and 9 are covered with the sidewall 70 made of the SiN film and the upper side thereof is covered with the SiN film 57, so that the Si layers 5 and 9 need not be oxidized. This thickening of the substrate surface SiO ₂ film 65 is because the surface of the Si substrate 1 is not exposed when the side surface facing the groove H of the Si layers 5 and 9 is exposed in the later step of FIG. . The presence of the thick SiO ₂ film 65 on the substrate surface can reduce the wiring capacitance in the word line of FIG.

Next, the support 60 is etched using, for example, a diluted HF solution to expose the surface of the SiN film 57, and further, the SiN film 57 is etched using, for example, a hot phosphoric acid solution. In this way, as shown in FIGS. 13A and 13B, the SiO ₂ film 55 on the Si layer 9 and the SiO ₂ film 65 on the side surfaces of the Si layers 5 and 9 are exposed. Next, the SiO ₂ films 55 and 65 are etched using, for example, a diluted HF solution. Thereby, as shown in FIGS. 14A and 14B, the side surface of the Si layers 5 and 9 facing the groove H and the upper surface of the Si layer 9 are exposed. In FIG. 14 and subsequent figures, in order to avoid the confusion of the correspondence with FIG. 1, the SiO ₂ film 65 between the Si substrate 1 and the Si layer 5 is referred to as an insulating film 3, and the Si layer 5 and the Si layer 9 The SiO ₂ film 65 between them is referred to as an insulating film 7.

Next, as shown in FIGS. 15A and 15B, the tunnel gate insulating film 11 is formed so as to cover at least the side surface of the Si layers 5 and 9 facing the groove H. Here, when an SiO ₂ film is used as the tunnel gate insulating film 11, the SiO ₂ film is formed by, for example, thermal oxidation of Si or CVD. Further, when a film having a band gap (that is, an energy difference between a valence band and a conduction band) smaller than that of SiO ₂ and having a small barrier energy with Si is used as the tunnel gate insulating film 11, for example, a CVD method is used. Further, an Si ₃ N ₄ film, a Ta ₂ O ₅ film, a BaTiO ₃ film, a ZrO ₂ film, an HfO film, a Y ₂ O ₃ film, a ZrSiO ₂ film, or the like is formed by the ALD method.

  Next, as shown in FIGS. 16A and 16B, a conductive film 73 is formed on the entire surface of the Si substrate 1 so as to cover the tunnel gate insulating film 11. For the conductive film 73, for example, a semiconductor film such as Poly-Si or a metal film can be used. Here, for example, Poly-Si is used as the conductive film 73. Poly-Si is formed by CVD, for example.

  Next, the conductive film 73 is etched back using anisotropic dry etching. Thus, as shown in FIGS. 17A and 17B, the conductive film is left only on the side surface of the Si layers 5 and 9 facing the groove H, and the conductive film is removed from the other regions. The conductive film left on the side surface of the Si layers 5 and 9 facing the groove H becomes the floating gate 13. After the floating gate 13 is formed, the Si substrate 1 is subjected to a cleaning process using, for example, a dilute HF solution, and the surface of the floating gate 13 or the tunnel gate insulating film 11 (exposed from the floating gate 13) ( That is, the surface of the tunnel gate insulating film 11 remaining on the upper surface of the Si layer 9 is cleaned. In this cleaning process, as shown in FIG. 22A, the portion of the tunnel gate insulating film 11 remaining on the upper surface of the Si layer 9 is completely removed to expose the upper surface of the Si layer 9. May be.

Next, as shown in FIGS. 18A and 18B, a gate insulating film 15 is formed on the surface of the floating gate 13. The formation method of the gate insulating film 15 is, for example, thermal oxidation or HTO (that is, thermal CVD at a high temperature of about 600 to 900 ° C.). For example, when the floating gate 13 is polysilicon, a SiO ₂ film is formed by thermal oxidation. When the insulator 11 is an oxide film such as SiO ₂ , HfO, or ZrO ₂ , the oxidized species diffuses in the insulating film 11 during thermal oxidation, and new SiO 2 is present at the interface between the insulating film 11 and the upper surface of the Si layer 9. ₂ is formed. Therefore, even when the insulating film 11 is formed of an oxide insulator having a small energy barrier, an SiO ₂ film having a large energy barrier exists only on the upper surface of the Si layer 9. In the step of forming the gate insulating film 15, when the upper surface of the Si layer 9 is exposed as shown in FIG. 22A, the Si layer 9 is formed as shown in FIG. A gate insulating film 15 is also formed on the upper surface. The gate insulating film 15 formed on the upper surface of the Si layer 9 becomes the gate insulating film of the NMOS 30a.

  Next, as shown in FIGS. 18A and 18B, a conductive film 75 is formed on the entire surface of the Si substrate 1 so as to cover the gate insulating film 15. Here, for the conductive film 75, for example, Poly-Si to which conductive impurities such as phosphorus (P) or boron (B) are added is used. Next, as shown in FIGS. 19A and 19B, a resist pattern 77 is formed on the conductive film, covering the formation region of the control gate 17 and exposing the other regions. Then, the control gate 17 is formed by dry etching the conductive film using the resist pattern 77 as a mask.

  Next, as shown in FIGS. 20A and 20B, a P-type impurity such as boron is ion-implanted toward the Si substrate 1 using the resist pattern 77 and the control gate 17 as a mask. Here, by matching the Rp (project range) of ion implantation to the Si layer 5, P-type impurities can be intensively introduced into the Si layer 5, and the PMOS source / drain (P +) can be introduced only into the Si layer 5. Can be formed.

Next, as shown in FIGS. 21A and 21B, N-type impurities such as arsenic are ion-implanted toward the Si substrate 1 using the resist pattern 77 and the control gate 17 as a mask. Here, by matching the ion implantation Rp (project range) to the Si layer 9, N-type impurities can be intensively introduced into the Si layer 9, and the NMOS source / drain (N +) can be introduced only into the Si layer 9. Can be formed. Thereafter, the resist pattern 77 is removed from the control gate 17. Thereby, the nonvolatile memory 100 shown in FIGS. 1A to 1C is completed.
It is also possible to form the DiNOR circuit 200 as shown in FIG. 23 by the method described with reference to FIGS. In that case, the support hole h and the groove H may be selectively disposed in a plurality of element isolation regions (that is, regions where the Si layers 5 and 9 are not left) 220 of the DiNOR circuit 200.

  As described above, according to the embodiment of the present invention, electrons can be supplied from the NMOS 30 and holes can be supplied from the PMOS 20 to the common floating gate 13. By selectively supplying electrons and holes to the floating gate 13, the potential can be changed, and the threshold voltages of the PMOS 20 and the NMOS 30 can be controlled. For example, when writing data, electrons can be supplied to the common floating gate 13 to lower the threshold of the PMOS 20 and raise the threshold of the NMOS 30. At the time of erasing data, holes can be supplied to the floating gate 13 to recombine the accumulated electrons with the holes, and the threshold voltages of the PMOS 20 and NMOS 30 can be returned to the state before writing.

  As described above, since writing and erasing with respect to the floating gate 13 can be realized by supplying two carriers of electrons and holes, compared with the conventional technique, the data is written and erased with respect to the control gate. There is no need to apply positive and negative voltages at a high voltage, and a high voltage driving circuit can be omitted. Therefore, the chip area of the LSI can be reduced. In addition, data writing / erasing can be performed with a low voltage power source using a battery or the like.

  In this embodiment, the Si substrate 1 corresponds to the “substrate” or “semiconductor substrate” of the present invention, the insulating film 3 corresponds to the “first insulating film” of the present invention, and the insulating film 7 corresponds to “ This corresponds to the “second insulating film”. The single crystal Si layer 5 corresponds to the “first semiconductor layer” of the present invention, the single crystal Si layer 9 corresponds to the “second semiconductor layer” of the present invention, and the floating gate 13 corresponds to the “first semiconductor layer” of the present invention. It corresponds to the “charge storage layer”. Further, the PMOS 20 formed on the side surface of the Si layer 5 corresponds to the “first conductivity type MOS transistor” of the present invention, and the NMOS 30 formed on the side surface of the Si layer 9 corresponds to the “second conductivity type MOS transistor” of the present invention. It corresponds to. The SiGe layer 51 corresponds to the “first sacrificial semiconductor layer” of the present invention, and the SiGe layer 53 corresponds to the “second sacrificial semiconductor layer” of the present invention. Further, the support hole h corresponds to the “first groove” of the present invention, and the groove H corresponds to the “second groove” of the present invention. The cavity 61 corresponds to the “first cavity” of the present invention, and the cavity 63 corresponds to the “second cavity” of the present invention.

  1A to 1C, the insulating film on the upper surface of the Si layer 9 (that is, the gate insulating film of the NMOS 30a) is thicker than the tunnel gate insulating film 11 on the side surfaces of the Si layers 5 and 9. Preferably it is formed. For example, as shown in FIGS. 22A and 22B, when the gate insulating film of the NMOS 30 a is composed of the gate insulating film 15, the gate insulating film 15 is more than the tunnel gate insulating film 11. It is preferable to form it thickly. With such a configuration, when electrons (or holes) are injected into the floating gate 13, the tunnel gate insulating film 11 has a potential barrier against carriers (electrons or holes) rather than the gate insulating film 15. Therefore, it becomes easy to move carriers to the floating gate 13 through the tunnel gate insulating film 11 when writing or erasing data.

Further, in the present invention, in FIGS. 1A to 1C, regarding the barrier energy generated by contact with Si, the tunnel gate insulating film 11 on the side surfaces of the Si layers 5 and 9 has a barrier energy higher than the gate insulating film of the NMOS 30a. Is preferably made of a material film having a small thickness. For example, in FIGS. 22A and 22B, the gate insulating film 15 is a SiO ₂ film, and the tunnel gate insulating film 11 is a Si ₃ N ₄ film, a Ta ₂ O ₅ film, a BaTiO ₃ film, a ZrO ₂ film, A HfO film, a Y ₂ O ₃ film, a ZrSiO ₂ film, or the like is preferable. With such a configuration, the potential barrier against carriers (electrons or holes) is smaller in the tunnel gate insulating film 11 than in the gate insulating film of the NMOS 30a, so that the data is written and erased through the tunnel gate insulating film 11. It becomes easy to move carriers to the floating gate 13.

Further, in the present invention, in FIGS. 1A to 1C, the floating gate 13 may be replaced with a charge trap film made of an insulating film. That is, the “charge storage layer” of the present invention is not limited to a semiconductor film such as Poly-Si or a metal film. For example, an insulating film such as a Si ₃ N ₄ film or an intrinsic Poly-Si film is used. Such a high resistance semiconductor may be used. Even with such a configuration, similarly to the above-described embodiment, writing and erasing with respect to the charge trapping film can be realized by supplying two carriers of electrons and holes. For example, when writing data, electrons can be supplied to the common charge trapping film to change the threshold voltages of the PMOS 20 and NMOS 30 respectively. When erasing data, holes are supplied to the charge trapping film so that the negative charges of the trapped electrons are canceled by the positive charges of the holes, and the threshold voltages of the PMOS 20 and NMOS 30 are returned to the state before writing. it can. Therefore, compared with the conventional technique, it is not necessary to apply a positive or negative voltage to the control gate at a high voltage at the time of data writing and erasing, and a high voltage driving circuit can be omitted.

1 is a diagram showing a configuration example of a nonvolatile memory 100 according to an embodiment. FIG. 3 is a diagram illustrating a method for manufacturing the nonvolatile memory 100 (part 1); FIG. 2 is a diagram illustrating a method for manufacturing the nonvolatile memory 100 (part 2); FIG. 3 is a diagram illustrating a method for manufacturing the nonvolatile memory 100 (No. 3). FIG. 4 is a diagram illustrating a method for manufacturing the nonvolatile memory 100 (part 4); FIG. 5 is a diagram illustrating a method for manufacturing the nonvolatile memory 100 (No. 5). FIG. 6 illustrates a method for manufacturing the nonvolatile memory 100 (No. 6). FIG. 7 shows a method for manufacturing the nonvolatile memory 100 (No. 7). FIG. 8 shows a method for manufacturing the nonvolatile memory 100 (No. 8). FIG. 9 shows a method for manufacturing the nonvolatile memory 100 (No. 9). FIG. 10 shows a method for manufacturing the nonvolatile memory 100 (No. 10). FIG. 11 shows a method for manufacturing the nonvolatile memory 100 (No. 11). FIG. 12 shows a method for manufacturing the nonvolatile memory 100 (No. 12). FIG. 13 shows a method for manufacturing the nonvolatile memory 100 (No. 13). FIG. 14 is a diagram showing a method for manufacturing the nonvolatile memory 100 (No. 14). FIG. 15 is a view showing a method for manufacturing the nonvolatile memory 100 (No. 15). FIG. 16 is a view showing the method of manufacturing the nonvolatile memory 100 (No. 16). FIG. 17 is a view showing a method for manufacturing the nonvolatile memory 100 (No. 17). FIG. 18 shows a method for manufacturing the nonvolatile memory 100 (No. 18). FIG. 19 is a diagram illustrating a method for manufacturing the nonvolatile memory 100 (19); FIG. 20 shows a method for manufacturing the nonvolatile memory 100 (No. 20). The figure which shows the other structural example of the non-volatile memory. The top view which shows the structural example of the DiNOR circuit 200 which concerns on embodiment. FIG. 2 is a circuit diagram showing a configuration example of a DiNOR circuit 200.

Explanation of symbols

1 Si substrate, 3, 7 insulating film, 5, 9 Si layer, 11 (tunnel) gate insulating film,
13 Floating gate, 15 Gate insulating film (for example, SiO ₂ film), 17 Control gate, 20 PMOS, 30 NMOS, 30a Si of NMOS
Portions formed on the upper surface of the layer 9 (that is, normal NMOS having no memory function), 51, 53
SiGe layer, 55, 65 SiO ₂ film, 57, 69 SiN film, 59 Support film, 60
Support, 61, 63 cavity, 70 sidewall, 73, 75 conductive film, 77 resist pattern, 100 nonvolatile memory, 200 DiNOR circuit, 201 word line, 203 bit line, 211, 213, 215 contact electrode, 220 element Separation region, H groove, h support hole, h1 (shallow) support hole, h2 (deep) support hole

Claims (7)

A first semiconductor layer formed on a substrate via a first insulating film;
A second semiconductor layer formed on the first semiconductor layer via a second insulating film;
A first conductivity type MOS transistor formed on at least one side surface of the first semiconductor layer;
A second conductivity type MOS transistor formed on at least one side surface of the second semiconductor layer,
The first conductivity type MOS transistor and the second conductivity type MOS transistor have a common charge storage layer and a common control gate,
The common charge storage layer is continuous from the side surface of the first semiconductor layer where the first conductive MOS transistor is formed to the side surface of the second semiconductor layer where the second conductive MOS transistor is formed. A semiconductor device characterized by being provided. A first semiconductor layer formed on a substrate via a first insulating film;
A second semiconductor layer formed on the first semiconductor layer via a second insulating film;
A first conductivity type MOS transistor formed on at least one side surface of the first semiconductor layer;
A second conductivity type MOS transistor formed on at least one side surface and an upper surface of the second semiconductor layer,
The first conductivity type MOS transistor and the second conductivity type MOS transistor have a common charge storage layer and a common control gate,
The common charge storage layer passes from the side surface of the first semiconductor layer on which the first conductivity type MOS transistor is formed, to the side surface of the second semiconductor layer on which the second conductivity type MOS transistor is formed. The semiconductor device is provided continuously over the upper surface of the second semiconductor layer. A first semiconductor layer formed on a substrate via a first insulating film;
A second semiconductor layer formed on the first semiconductor layer via a second insulating film;
A first conductivity type MOS transistor formed on at least one side surface of the first semiconductor layer;
A second conductivity type MOS transistor formed on at least one side surface and an upper surface of the second semiconductor layer,
The first conductivity type MOS transistor and the second conductivity type MOS transistor have a common charge storage layer and a common control gate,
The common charge storage layer is continuous from the side surface of the first semiconductor layer where the first conductive MOS transistor is formed to the side surface of the second semiconductor layer where the second conductive MOS transistor is formed. And the semiconductor device is not provided on the upper surface of the second conductive layer.   4. The semiconductor according to claim 1, wherein a drain of the first conductivity type MOS transistor and a drain of the second conductivity type MOS transistor are electrically connected. 5. apparatus. The tunnel gate insulating film of the portion formed on the side surface of the second semiconductor layer of the second conductivity type MOS transistor is:
5. The semiconductor according to claim 3, wherein the semiconductor is formed thinner than a portion of the gate insulating film formed on the upper surface of the second semiconductor layer of the second conductivity type MOS transistor. apparatus. Regarding barrier energy generated by contact with the second semiconductor layer,
The tunnel gate insulating film of the portion formed on the side surface of the second semiconductor layer of the second conductivity type MOS transistor is:
4. The device according to claim 3, wherein the barrier energy of the second conductive MOS transistor is smaller than that of a portion of the gate insulating film formed on the upper surface of the second semiconductor layer. 6. The semiconductor device according to any one of items 5. Sequentially stacking a first sacrificial semiconductor layer, a first semiconductor layer, a second sacrificial semiconductor layer, and a second semiconductor layer on a semiconductor substrate;
Partially etching the second semiconductor layer, the second sacrificial semiconductor layer, the first semiconductor layer, and the first sacrificial semiconductor layer sequentially to form a first groove penetrating each semiconductor layer;
Forming a support in the first groove to support the first semiconductor layer and the second semiconductor layer;
After forming the support, the second semiconductor layer, the second sacrificial semiconductor layer, the first semiconductor layer, and the first sacrificial semiconductor layer are partially and sequentially etched to expose the side surfaces of the respective semiconductor layers. Forming a second groove to be caused;
The first sacrificial semiconductor layer and the second sacrificial semiconductor layer are more easily etched than the first semiconductor layer and the second semiconductor layer, and the first sacrificial semiconductor layer and the second sacrificial semiconductor layer are etched through the second groove. By etching the second sacrificial semiconductor layer, a first cavity is formed between the semiconductor substrate and the first semiconductor layer, and a second cavity is formed between the first semiconductor layer and the second semiconductor layer. Forming two cavities;
Forming a first insulating film in the first cavity and forming a second insulating film in the second cavity;
After forming the first insulating film and the second insulating film, a first conductivity type MOS transistor is formed on a side surface of the first semiconductor layer facing the second groove, and the second semiconductor layer has the Forming the second conductivity type MOS transistor on a side surface facing the second groove,
In the process of forming the first conductivity type MOS transistor and forming the second conductivity type MOS transistor,
Forming a tunnel gate insulating film on each of a side surface of the first semiconductor layer facing the second groove and a side surface of the second semiconductor layer facing the second groove;
Forming a common charge storage layer from the side surface of the first semiconductor layer to the side surface of the second semiconductor layer so as to cover the tunnel gate insulating film;
Forming a gate insulating film from the side surface of the first semiconductor layer to the side surface of the second semiconductor layer so as to cover the charge storage layer;
A method of manufacturing a semiconductor device, comprising: forming a common control gate from the side surface of the first semiconductor layer to the side surface of the second semiconductor layer so as to cover the gate insulating film.

Images