JP2008140898A - Semiconductor device, and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of writing and deleting data with a low voltage, and to provide a method of manufacturing the semiconductor device. <P>SOLUTION: There are provided: an Si layer 5 formed on an Si layer 1 via an insulating film 3; an Si layer 9 formed on the Si layer 5 via an insulating film 7; a PMOS 20 formed on at least one side of the Si layer 5; and an NMOS 30 formed on at least one side of the Si layer 9. The PMOS 20 and the NMOS 30 have a common control gate 17 and a common floating gate 8. The common floating gate is arranged between the Si layers 5, 9. Writing and erasure to the common floating gate 8 are achieved by supplying two carriers of electrons and holes. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a technique capable of executing data writing and erasing at a low voltage as well as data reading.

As shown in Patent Documents 1 and 2, a conventional nonvolatile memory has a planar MOS structure, and a floating gate surrounded by a SiO ₂ insulating film is formed between a control gate and a silicon substrate (MOSFET channel). It had been. In the nonvolatile memory having such a structure, data is written by applying a large positive voltage of several tens of volts to the source / drain or body to the control gate and injecting electrons into the floating gate. . Further, data is erased by applying a large negative voltage of several tens of volts to the source / drain or body to the control gate and extracting electrons from the floating gate.
JP 2006-186300 A International Publication No. 2004/084314 Pamphlet JP 2005-327796 A JP 2005-322830 A T.A. Sakai et al. “Separation by Bonding Si Islands (SBSI) for LSI Applications”, Second International SiGe Technology and Device Meeting, Meeting Abstract, pp. 230-231, May (2004)

  In the conventional technology, data is written to and erased from the floating gate using only one carrier called electrons, so it is necessary to apply large positive and negative voltages to the control gate during writing and erasing. there were. For this reason, for example, even in an LSI in which a low-voltage drive logic circuit and a non-volatile memory are mixedly mounted, a high-voltage drive circuit operation is required, resulting in an increase in manufacturing cost due to an increase in the chip area of the LSI and deterioration in reliability of the low-voltage drive circuit. There was a risk of doing so.

Even in the device structure of non-volatile memory, the gate insulating film cannot be thinned or the source / drain junction cannot be sharpened in order to ensure high voltage drive reliability. was there. Furthermore, the fact that the gate insulating film cannot be thinned or the source / drain junction cannot be abrupt means that the drain current of the MOS transistor is small when reading data. For this reason, the conventional technology has not been able to sufficiently read at a low voltage or at a high speed.
Therefore, the present invention has been made in view of such circumstances, and a semiconductor device capable of executing data writing and erasing at a low voltage and reading data at a high speed at a low voltage and a method for manufacturing the same. For the purpose of provision.

  [Invention 1 and 2] In order to solve the above-described problems, a semiconductor device of Invention 1 includes a first semiconductor layer formed on a substrate via a first insulating film, and a second semiconductor layer on the first semiconductor layer. A second semiconductor layer formed through an insulating film; a first conductivity type MOS transistor formed on at least one side surface of the first semiconductor layer; and formed on at least one side surface of the second semiconductor layer. A second conductivity type MOS transistor, wherein the first conductivity type MOS transistor and the second conductivity type MOS transistor have a common charge accumulation layer and a common control gate, and the common charge accumulation layer is The semiconductor device is provided in the second insulating film sandwiched between the first semiconductor layer and the second semiconductor layer.

Here, the “first semiconductor layer” and the “second semiconductor layer” of the present invention are, for example, single crystal silicon (Si) layers. In the present invention, the “first conductivity type” is one of P type and N type, and the “second conductivity type” is the other of P type and N type. For example, when the first conductivity type is P type, the second conductivity type is N type. Furthermore, the “charge storage layer” of the present invention is a layer for storing electrons or holes that have passed through the second insulating film, such as polysilicon (Poly-Si) doped with P-type or N-type impurities. Or a metal thin film such as Ti, Ta, TiN, or TaN, or an insulating film such as a Si ₃ N ₄ film, or a high-resistance semiconductor such as intrinsic poly-Si. .

  According to a second aspect of the present invention, there is provided a semiconductor device including: a first semiconductor layer formed on a substrate via a first insulating film; a second semiconductor layer formed on the first semiconductor layer via a second insulating film; A first conductivity type MOS transistor formed on at least one side surface of the first semiconductor layer; and a second conductivity type MOS transistor formed on at least one side surface and the upper surface of the second semiconductor layer; The one conductivity type MOS transistor and the second conductivity type MOS transistor have a common charge storage layer and a common control gate, and the common charge storage layer includes the first semiconductor layer, the second semiconductor layer, and the second semiconductor layer. It is provided in the second insulating film sandwiched between two layers.

  According to the semiconductor devices of the first and second aspects, electrons can be supplied from the N-type MOS transistor to the common charge storage layer, and holes can be supplied from the P-type MOS transistor. By selectively supplying electrons and holes to the common charge storage layer, the potential can be changed, and the threshold voltage of each of the N-type and P-type MOS transistors can be controlled. For example, when writing data, electrons can be supplied to a common charge storage layer to change the threshold voltage of each MOS transistor. When erasing data, holes are supplied to the common charge storage layer to recombine the accumulated electrons with the holes (or the electric field due to the negative charge of the trapped electrons is changed to the electric field due to the positive charge of the hole. The threshold voltage of each MOS transistor can be returned to the state before writing.

  As described above, according to the semiconductor devices of the first and second aspects, writing and erasing with respect to the common charge storage layer can be realized by supplying two carriers of electrons and holes. It is not necessary to apply positive and negative voltages to the control gate at the time of data writing and erasing, and the high voltage driving circuit can be omitted. Therefore, the chip area of the LSI can be reduced. Further, according to the semiconductor device of the invention 2, compared with the semiconductor device of the invention 1, since the channel area of the MOS transistor for supplying electrons or holes to the charge storage layer can be increased, the data writing operation and the erasing operation can be performed. Speeding up is possible.

  The semiconductor device according to the first and second aspects includes both a P-channel MOS transistor and an N-channel MOS transistor, and since these PN MOS transistors have a common control gate, they are turned on and off at the same timing. Can be switched. Therefore, the semiconductor devices of the inventions 1 and 2 can be applied to, for example, a NOR circuit.

  [Invention 3] The semiconductor device of Invention 3 is the semiconductor device of Invention 1 or Invention 2, wherein the common charge storage layer is the second insulating film sandwiched between the first semiconductor layer and the second semiconductor layer. It is provided only inside. With such a configuration, there is no charge storage layer on the side surfaces of the first and second semiconductor layers, and only the gate insulating film exists between the control gate and the first and second semiconductor layers. (2) Channel controllability on the side surface of the semiconductor layer is high, and high-speed reading is possible with a low voltage.

[Invention 4] The semiconductor device of Invention 4 is the semiconductor device according to any one of Inventions 1 to 3, wherein the drain of the first conductivity type MOS transistor and the drain of the second conductivity type MOS transistor are electrically connected. It is characterized by being connected.
With such a configuration, for example, the drain of the N-type MOS transistor and the drain of the P-type MOS transistor are always at the same potential. Therefore, when electrons (or holes) are injected, an N-type (or P-type) MOS transistor is used. The generated hot electrons (or hot holes) are pulled not only by the source potential of the P-type (or N-type) MOS transistor but also by the drain potential. Therefore, the efficiency of injecting electrons (or holes) into the charge storage layer can be increased. In addition, since the wiring connected to the drains of the P-type and N-type MOS transistors can be made common, it is possible to reduce the area occupied by the wiring on the chip surface.

  [Invention 5] The semiconductor device according to Invention 5 is the semiconductor device according to any one of Inventions 1 to 4, wherein the first semiconductor layer and the second semiconductor layer are silicon, and the barrier energy generated by contact with silicon is The second insulating film is formed of a film having a lower barrier energy than both the gate insulating film of the first conductive MOS transistor and the gate insulating film of the second conductive MOS transistor. To do.

  According to the semiconductor device of the fifth aspect of the present invention, the potential barrier against carriers (electrons or holes) is smaller in the second insulating film than in the gate insulating film. It becomes easy to move to (for example, a floating gate). In addition, since carriers are not injected into the gate insulating film having a large barrier, the MOS transistor characteristics are not deteriorated and the reliability is excellent.

  [Invention 6] A method of manufacturing a semiconductor device according to Invention 6 includes a step of sequentially stacking a first sacrificial semiconductor layer, a first semiconductor layer, a second sacrificial semiconductor layer, and a second semiconductor layer on a semiconductor substrate, and the second semiconductor. Etching the layer, the second sacrificial semiconductor layer, the first semiconductor layer, and the first sacrificial semiconductor layer partially sequentially to form a first groove penetrating each of the semiconductor layers; and the first semiconductor layer Forming a support in the first groove, and supporting the second semiconductor layer, the second sacrificial semiconductor layer, and the first semiconductor after forming the support. Etching a layer and the first sacrificial semiconductor layer partially sequentially to form a second groove exposing a side surface of each semiconductor layer; and the first semiconductor layer and the second semiconductor layer more than the first semiconductor layer. The sacrificial semiconductor layer and the second sacrificial semiconductor layer are more efficient. By etching the first sacrificial semiconductor layer and the second sacrificial semiconductor layer through the second groove under etching conditions that are likely to be etched, a first cavity is formed between the semiconductor substrate and the first semiconductor layer. Forming a second cavity between the first semiconductor layer and the second semiconductor layer, forming a first insulating film in the first cavity, and forming the second cavity Forming a second insulating film on the upper surface of the first semiconductor layer and the lower surface of the second semiconductor layer facing the second cavity, respectively, and leaving the first insulating film and the second insulating film After the formation, a first conductivity type MOS transistor is formed on the side surface of the first semiconductor layer facing the second groove, and the second conductive layer is formed on the side surface of the second semiconductor layer facing the second groove. Forming a MOS transistor; In the step of forming the first conductivity type MOS transistor and the second conductivity type MOS transistor, a common charge storage layer is formed in the second cavity where the second insulating film is formed, A gate insulating film is formed on each of a side surface of the first semiconductor layer facing the second groove and a side surface of the second semiconductor layer facing the second groove, and then the first insulating layer is formed so as to cover the gate insulating film. A common control gate is formed from the side surface of one semiconductor layer to the side surface of the second semiconductor layer.

Here, as described above, the “first semiconductor layer” and the “second semiconductor layer” of the present invention are, for example, single-crystal Si layers. The “first sacrificial semiconductor layer” and the “second sacrificial semiconductor layer” are, for example, single-crystal silicon germanium (SiGe) layers.
According to the semiconductor device manufacturing method of the invention 6, the so-called SBSI method can be applied to manufacture the semiconductor devices of the inventions 1 to 5. Therefore, since writing and erasing with respect to the charge storage layer can be realized by supplying two carriers of electrons and holes, it is possible to provide a semiconductor device that suppresses an increase in chip area by low voltage driving.

Hereinafter, a semiconductor device and a manufacturing method thereof according to the present invention will be described.
1A and 1B are diagrams showing a configuration example of a nonvolatile memory 100 according to an embodiment of the present invention. FIG. 1A is a plan view, and FIG. 1B is a cross-sectional view taken along line XX ′ in FIG. FIG. 1C is a cross-sectional view taken along the line YY ′ of FIG. 1A. In FIG. 1A, the interlayer insulating film is not shown for easy understanding of the configuration example of the nonvolatile memory 100 in a plan view. As shown in FIGS. 1A to 1C, in the nonvolatile memory 100, a first single crystal Si layer 5 is formed on an Si substrate 1 via an insulating film 3 or the like, and this single crystal Si layer is formed. A second single crystal Si layer 9 is formed on 5 via an insulating film 7 or the like.

The insulating films 3 and 7 are, for example, silicon oxide (SiO ₂ ) films. The single-crystal Si layers (hereinafter simply referred to as “Si layers”) 5 and 9 are elongate rectangular parallelepipeds arranged so as to be parallel to the XX ′ line, for example. It arrange | positions so that a center part may overlap by planar view. A P-type MOS transistor (hereinafter simply referred to as “PMOS”) 20 is formed on both side surfaces of the Si layer 5, and an N-type MOS transistor (hereinafter referred to as “P-type MOS transistor”) is formed on both side surfaces and the upper surface of the Si layer 9. This is simply referred to as “NMOS”) 30. That is, the channel region of the PMOS 20 is on the side surfaces on both sides of the Si layer 5, and the channel region of the NMOS 30 is on the side surfaces on both sides and the upper surface of the Si layer.

  Here, the PMOS 20 and the NMOS 30 are nonvolatile memory transistors, and share the charge storage layer (for example, floating gate) 8 and the control gate 17. That is, as shown in FIGS. 1B and 1C, a floating gate 8 is provided between the Si layer 5 in which the PMOS 20 is formed and the Si layer 9 in which the NMOS 30 is formed. Yes. The floating gate 8 is made of, for example, a semiconductor film such as polysilicon (Poly-Si) into which a P-type or N-type impurity is introduced, or a metal thin film such as Ti, Ta, TiN, or TaN. Examples of the P-type impurity include boron, and examples of the N-type impurity include phosphorus and arsenic. As shown in FIGS. 1B and 1C, the floating gate 8 is sandwiched from above and below by an insulating film 7 and insulated from the Si layers 5 and 9.

  Further, as shown in FIG. 1C, a gate insulating film 11 is continuously formed on the side surfaces of the Si layers 5 and 9 and the upper surface of the Si layer 9. Further, a control gate 17 is continuously formed on the Si substrate 1 so as to cover the gate insulating film 11. As shown in FIGS. 1A to 1C, the control gate 17 is shaped so as to straddle the vicinity of the center of the Si layers 5 and 9 stacked on the Si substrate 1. The control gate 17 is made of, for example, Poly-Si into which P-type or N-type impurities are introduced. Then, the source / drain (P +) of the PMOS 20 is formed in the portion of the Si layer 5 that is separated from the control gate 17, and the source / drain (N−) of the NMOS 30 is formed in the portion of the Si layer 9 that is separated from the control gate 17. Is formed.

  With such a structure, in the nonvolatile memory 100, electrons can be supplied from the NMOS 30 and holes can be supplied from the PMOS 20 to the common floating gate 8. Then, by selectively supplying electrons and holes to the floating gate 8, the potential can be changed, and the threshold voltages of the PMOS 20 and NMOS 30 can be controlled. For example, when writing data, electrons can be supplied to the common floating gate 8 to change the threshold voltages of the PMOS 20 and NMOS 30 respectively. At the time of erasing data, holes can be supplied to the common floating gate 8 to recombine the accumulated electrons with the holes, and the threshold voltages of the PMOS 20 and NMOS 30 can be returned to the state before writing.

Next, in the nonvolatile memory 100 shown in FIGS. 1A to 1C, a data writing method, an erasing method, and a reading method will be described.
Data writing and erasing can be performed as follows. For example, in FIGS. 1A to 1C, the power supply voltages are Vss (0 V) and Vdd (5 V), and the voltage applied to the control gate 17 and the voltages applied to the drains of the PMOS 20 and NMOS 30 are all Vdd. When set to, the NMOS 30 is turned on (ON) and the PMOS 20 is turned off (OFF). With such a voltage setting, electrons flow from the source to the drain in the NMOS 30 and are accelerated by a high electric field, or electron-hole pairs are formed by impact ionization, and hot carriers are generated. Hot electrons pass through the barrier of the Si layer 9 / insulating film 7, are pulled to the source and drain of the PMOS to which Vdd is applied, and are injected into the floating gate 8. Here, if a positive voltage larger than Vdd is applied to at least one diffusion layer of the source or drain of the PMOS 20, the carrier injection efficiency to the floating gate 8 can be further increased.

  On the other hand, when the voltage applied to the control gate 17 and the voltages applied to the drains of the PMOS 20 and the NMOS 30 are all set to Vss, the NMOS 30 is turned off and the PMOS 20 is turned on. Holes flow from the source to the drain in the PMOS 20 and are accelerated by a high electric field, or form electron / hole pairs by impact ionization to generate hot carriers. The hot holes are passed through the barrier of the insulating film 7 / Si layer 5, pulled to the source / drain of the NMOS to which Vss is applied, and injected into the floating gate 8. Here, if a negative voltage (that is, a negative voltage) greater than Vss is applied to at least one diffusion layer of the source or drain of the NMOS 30, the carrier injection efficiency to the floating gate 8 can be further increased. Data can be written and erased in the nonvolatile memory 100 by such injection of electrons or holes.

  Data can be read as follows. For example, the power supply voltages are Vss (0 V) and Vdd (5 V), and the voltage applied to the control gate 17 and the voltages applied to the drains of the PMOS 20 and NMOS 30 are all the same potential as the source of the PMOS 20 (for example, Vdd / 2). In the PMOS 20, the channel is turned off in the PMOS 20, and no current flows because there is no potential difference between the source and the drain. On the other hand, in the NMOS 30, a potential of Vdd / 2−Vss is applied between the source and the drain, and the same potential is applied between the control gate 17 and the source. For this reason, in the NMOS 30, when there are many electrons stored in the floating gate 8, the channel is turned off and no current flows, but when there are few electrons stored in the floating gate 8, or in the floating gate 8. When holes are stored, the channel is turned on and current flows between the source and drain.

  As described above, in the nonvolatile memory 100 shown in FIGS. 1A to 1C, not only can electrons be supplied from the NMOS 30 to the floating gate 8, but also holes can be supplied from the PMOS 20, and the floating gate 8 can be supplied. However, the threshold values of the PMOS 20 and the NMOS 30 can be controlled by changing the supply amount of electrons or holes. That is, data writing and erasing with respect to the floating gate 8 can be realized by supplying two carriers of electrons and holes.

  In particular, in the nonvolatile memory 100 shown in FIGS. 1A to 1C, there are no floating gates or charge traps on the side surfaces of the Si layers 5 and 9, and the channels of the Si layers 5 and 9 are not present. Since the gate insulating film 11 is formed only between the side surface and the control gate 17, the channel controllability by the control gate 17 is excellent, the MOS driving capability is high, and high-speed reading is performed at a low voltage. Is possible.

The energy required for forming an electron-hole pair in Si is about 1.1 eV, and the energy required for electrons to jump from Si to SiO ₂ when Si and SiO ₂ are in contact with each other. Is about 3.2 eV. In addition, the energy required for holes to jump from Si to SiO ₂ in the above contact state is about 4.8 eV. Therefore, in the PMOS 20 and the NMOS 30, the voltage required for the data writing operation and the erasing operation may be about 4.8V at the maximum (Max) value.

Also, due to the presence of lucky carriers, there are holes that jump from Si to SiO ₂ at a voltage lower than 4.8 V, but a certain amount of current is required to shorten the writing time and erasing time. A drive voltage of about 5V is appropriate. Further, when a material having a small barrier to Si is applied to the insulating film 7, writing / erasing can be easily performed at a voltage lower than 5V. Further, the voltage Vcg applied to the control gate 17 is set to the drain potential of the NMOS 30 (that is, the source potential of PMOS) when electrons are injected into the floating gate 8, and the voltage of the NMOS 30 is injected when holes are injected into the floating gate 8. What is necessary is just to set to source potential (namely, drain potential of PMOS). According to such a setting, the maximum potential difference between the source, body, drain, and gate of both the PMOS 20 and the NMOS 30 does not exceed 5V.

  Further, even when the non-volatile memory 100 shown in FIGS. 1A to 1C is mixedly mounted with a low-voltage drive logic circuit to configure an LSI, the maximum voltage is about 5 V or 5 V or less. It is possible to greatly improve the problem that the cost of LSI increases due to the increase and the reliability of the low voltage drive circuit deteriorates. Further, in the device structure of the nonvolatile memory 100, the gate insulating film can be made thinner and the source / drain junction can be made sharper, and the device can be reduced. In addition, by reducing the thickness of the gate insulating film and sharpening the source / drain junction, the drain current is improved, and low voltage reading and high speed reading are possible.

Next, an example of a circuit that uses the two Si layers 5 and 9 stacked on the Si substrate 1 as Vdd and Vss lines will be described.
FIG. 24 is a plan view showing a configuration example of a DivOR (Divided bit line NOR Flash Memory) circuit 200 according to the embodiment of the present invention. FIG. 25 is a circuit diagram showing a configuration example of the DiNOR circuit 200. In the DiNOR circuit 200, the 1-bit memory cell includes the nonvolatile memory 100 shown in FIGS.

  That is, as shown in FIG. 24, Si layers 5 and 9 are laminated on an Si substrate via an insulating film, and these form a grid of grids extending in the X and Y directions in plan view. Yes. Further, a word line (W / L) 201 is arranged on the Si substrate 1 along the Y direction so as to be orthogonal to the portion of the Si layers 5 and 9 extending in the X direction in plan view. Yes. This word line (W / L) 201 corresponds to the common control gate 17 shown in FIGS. Further, a bit line (B / L) 203 is disposed on the Si substrate so as to pass directly above the portion of the Si layers 5 and 9 extending in the X direction.

In this example, the bit line 203 passes over the word line 201 through an insulating film. In this example, a common contact electrode 211 is formed on the PMOS drain (D) and the NMOS drain (D), and the PMOS and NMOS drains are connected to the bit line via the common contact electrode 211. 203. Further, the source (S) of the PMOS is drawn out on the insulating film by the contact electrode 213, and is connected to, for example, the power supply Vdd by wiring as shown in FIG. The source (S) of the NMOS is drawn out on the insulating film by the contact electrode 215, and is connected to the power source Vss, for example, by wiring as shown in FIG. 24 and 25, a portion surrounded by a two-dot chain line is a 1-bit memory cell, that is, a nonvolatile memory 100.
In this way, in the DiNOR circuit 200 shown in FIGS. 24 and 25, the two Si layers 5 and 9 stacked on the Si substrate are used as the Vdd and Vss lines, respectively. As a result, the drain (D) contact electrode 211 can be shared by PN, and the number of contacts can be reduced, so that the integration degree of the DiNOR circuit 200 can be increased.

Next, a method for manufacturing the nonvolatile memory 100 shown in FIGS. 1A to 1C will be described.
2 to 21 are views showing a method of manufacturing the nonvolatile memory 100 according to the embodiment of the present invention, and FIGS. 2A to 21A are X-- up to FIG. 1B. FIG. 2B to FIG. 21B are process diagrams corresponding to the YY ′ section up to FIG. 1C. Here, manufacturing the nonvolatile memory 100 shown in FIGS. 1A to 1C by applying the SBSI method will be described.

  First, in FIGS. 2A and 2B, a silicon buffer (Si-buffer) layer (not shown) is formed on the Si substrate 1, and a single-crystal SiGe layer 51 and a single-crystal Si layer 5 are formed thereon. A single crystal SiGe layer 53 and a single crystal Si layer 9 are sequentially stacked. These Si-buffer layer, SiGe layer 51, Si layer 5, SiGe layer 53, and Si layer 9 are continuously formed by, for example, an epitaxial growth method.

Next, as shown in FIGS. 3A and 3B, the Si layer 9 is thermally oxidized to form a SiO ₂ film 55 on the surface thereof. Then, a SiN film 57 is formed on the entire surface of the SiO ₂ film 55 by the CVD method. The SiN film 57 functions as an antioxidant film for preventing the Si layers 5 and 9 and the SiGe layers 51 and 53 from being oxidized, and as a stopper layer when performing CMP (Chemical Mechanical Polishing) in a later process. Also works. The method for forming the SiO ₂ film 55 is not limited to thermal oxidation, and may be formed by, for example, a CVD method.

Next, as shown in FIGS. 4A and 4B, the SiN film 57, the SiO ₂ film 55, the Si layer 9, and the SiGe layer 53 are partially and sequentially etched using a photolithography technique and an etching technique. . Thus, a shallow support hole h1 having the Si layer 5 as a bottom through the Si layer 9 and the SiGe layer 53 is formed in a region overlapping the element isolation region (that is, a region where the SOI structure is not formed) in plan view. . Next, as shown in FIGS. 5A and 5B, by using a photolithography technique and an etching technique, the Si layer 5 exposed at the bottom surface of the shallow support hole h1, and the SiGe layer 51 and Si under the Si layer 5 are exposed. -The buffer layer is partially etched sequentially. As a result, a deep support hole h2 having the Si substrate 1 as the bottom surface is formed through the Si layer 5 and the SiGe layer 51 in a region overlapping the element isolation region in plan view. In the etching process for forming the deep support hole h2, the etching may be stopped on the surface of the Si substrate 1, or the Si substrate 1 may be over-etched to form a recess. Hereinafter, for convenience of explanation, the shallow support hole h1 and the deep support hole h2 are collectively referred to as a support hole h.

Next, as shown in FIGS. 6A and 6B, a support film 59 is formed on the entire surface of the Si substrate 1 so as to fill the support hole h. The support film 59 is a silicon oxide (SiO ₂ ) film, for example, and is formed by, for example, a CVD method. Next, as shown in FIGS. 7A and 7B, the support film 59, the SiN film 57, the SiO ₂ film 55, the Si layer 9, the SiGe layer 53, and the Si layer using a photolithography technique and an etching technique. 5, the SiGe layer 51 and the Si-buffer layer (not shown) are partially etched sequentially to form the support 60 from the support film 59, and the surface of the Si substrate 1, the Si layer 9, and the SiGe layer 53, a groove H exposing each side surface of the Si layer 5 and the SiGe layer 51 is formed. In the etching process for forming the groove H, the etching may be stopped on the surface of the Si substrate 1, or the Si substrate 1 may be over-etched to form a recess.

  Next, in FIGS. 7A and 7B, the hydrofluoric acid solution is brought into contact with the side surfaces of the Si layers 5 and 9 and the SiGe layers 51 and 53 through the grooves H to select the SiGe layers 51 and 53. Etch away. As a result, as shown in FIGS. 8A and 8B, a first cavity 61 is formed between the Si substrate 1 and the Si layer 5, and between the Si layer 5 and the Si layer 9. A second cavity 63 is formed. Here, in wet etching using a hydrofluoric acid solution, the etching rate of SiGe is larger than that of Si (that is, the etching selectivity to Si is large), so only the SiGe layer is etched while leaving the Si layers 5 and 9. And can be removed. After the formation of the cavities 61 and 63, the Si layer 9 is supported by the support body 60 on the upper surface and side surfaces thereof, and the side surface of the Si layer 5 is supported by the support body 60.

Next, in FIGS. 8A and 8B, the Si substrate 1 is cleaned with a diluted hydrofluoric acid (HF) solution. Then, the Si substrate 1 is placed in an oxidizing atmosphere such as oxygen (O ₂ ) or ozone (O ₃ ), and the Si substrate 1 is subjected to heat treatment in this state. As a result, as shown in FIGS. 9A and 9B, Si surface oxidation proceeds on the Si layers 5 and 9, the Si-buffer layer (not shown), and the surface of the Si substrate 1, respectively. _Two films 65 are formed. Here, in the present embodiment, the SiO ₂ film 65 is formed so that the cavities 61 and 63 are left (that is, the cavities 61 and 63 are not blocked). Of the SiO ₂ film 65, the portions formed in the cavity 61 and on the surface of the Si substrate 1 become the insulating film 3 shown in FIGS. 1B and 1C and are formed in the cavity 63. This portion becomes the insulating film 7. Here, the thin film 65 made of a material having a small energy barrier with Si may be formed by a CVD method or an ALD method.

Next, as shown in FIGS. 10A and 10B, a film 68 for forming the floating gate 8 is formed on the entire upper surface of the Si substrate 1, and the SiO ₂ film 65 is formed. Embed the cavity. As the film 68 for forming the floating gate 8, a semiconductor film such as polysilicon (Poly-Si) into which P-type or N-type impurities are introduced, or a metal film can be used. In the embodiment, a Poly-Si film into which a P-type or N-type impurity is introduced is used. The formation of the Poly-Si film 68 is performed by, for example, a CVD method.

Then, using the SiO ₂ film 55, the Si ₃ N ₄ film 57, the SiO ₂ film 60, and the SiO ₂ film 65 as a mask, the Poly-Si film 68 is formed by using anisotropic and isotropic dry etching. Etch. Thus, as shown in FIGS. 11A and 11B, the Poly-Si film 68 is left only in the cavity, and the Poly-Si film 68 is removed from other regions. In FIG. 11 and subsequent figures, in order to avoid confusion with the correspondence with FIG. 1, the Poly-Si film 68 between the Si substrate 1 and the Si layer 5 is referred to as the conductive film 4, and the Si layer 5 and the Si layer The Poly-Si film 68 between them is described as a floating gate 8. Further, the SiO ₂ film 65 sandwiching from above and below the conductive film 4 in sectional view describes an insulating film 3, an SiO ₂ film 65 sandwiching the floating gate 8 from the top and bottom as viewed in cross-section referred to as an insulating film 7.

Next, as shown in FIGS. 12A and 12B, a SiO ₂ film, for example, is formed on the side surface of the floating gate 8 or the conductive film 3 facing the groove H by thermal oxidation or CVD. Then, a SiN film 69 is formed on the entire upper surface of the Si substrate 1. The SiN film 69 is formed by, for example, a CVD method. Subsequently, the SiN film 69 is etched back using anisotropic dry etching. As a result, as shown in FIGS. 13A and 13B, the sidewalls 70 are formed on the side surfaces of the Si layers 5 and 9, the SiO ₂ film 55, the SiN film 57, and the groove 60 of the support 60. .

Next, as shown in FIGS. 14A and 14B, the Si substrate 1 is subjected to thermal oxidation to thicken the portion of the SiO ₂ film 65 exposed from under the sidewall 70. To do. At this time, since the side surfaces of the Si layers 5 and 9 and the floating gate 8 are covered with the sidewall 70 made of the SiN film and the upper side thereof is covered with the SiN film 57, it is not necessary to be oxidized. The thickening of the SiO ₂ film 65 is because the surface of the Si substrate 1 is not exposed when the side surface facing the groove H of the Si layers 5 and 9 is exposed in the subsequent step of FIG. In addition, the wiring capacity of the word line (control gate 17) can be reduced, and data can be read at high speed.

Next, the support 60 is etched using, for example, a diluted HF solution to expose the surface of the SiN film 57, and the SiN film 57 and the sidewalls 70 are etched using, for example, a hot phosphoric acid solution. In this way, as shown in FIGS. 15A and 15B, the surface of the insulating film is exposed at the side surface facing the groove H of the Si layers 5 and 9. Next, the insulating film and the SiO ₂ films 55 and 65 are etched using, for example, a diluted HF solution. As a result, as shown in FIGS. 16A and 16B, the side surface of the Si layers 5 and 9 facing the groove H, the upper surface of the Si layer 9, and the side surface of the floating gate 8 facing the groove H are exposed. Let A thick SiO ₂ film 65 remains on the surface of the substrate 1.

Next, as shown in FIGS. 17A and 17B, the side surface of the Si layers 5 and 9 facing the groove H and the side surface of the floating gate 8 facing the groove H are continuously covered. Then, the gate insulating film 11 is formed. Here, when an SiO ₂ film is used as the gate insulating film 11, the SiO ₂ film is formed by, for example, thermal oxidation of Si or CVD.
Next, as shown in FIGS. 18A and 18B, a conductive film 75 is formed on the entire surface of the Si substrate 1 so as to cover the gate insulating film 15. Here, for the conductive film 75, for example, Poly-Si to which conductive impurities such as phosphorus (P) or boron (B) are added is used. Next, as shown in FIGS. 19A and 19B, a resist pattern 77 is formed on the conductive film, covering the formation region of the control gate 17 and exposing the other regions. Then, the control gate 17 is formed by dry etching the conductive film using the resist pattern 77 as a mask.

  Next, as shown in FIGS. 20A and 20B, a P-type impurity such as boron is ion-implanted toward the Si substrate 1 using the resist pattern 77 and the control gate 17 as a mask. Here, by matching the Rp (project range) of ion implantation to the Si layer 5, P-type impurities can be intensively introduced into the Si layer 5, and the PMOS source / drain (P +) can be introduced only into the Si layer 5. Can be formed. Here, the film thickness of the resist 77 and the control gate 17 is set to a thickness that can serve as a mask for implanted ions.

Next, as shown in FIGS. 21A and 21B, N-type impurities such as arsenic are ion-implanted toward the Si substrate 1 using the resist pattern 77 and the control gate 17 as a mask. Here, by matching the ion implantation Rp (project range) to the Si layer 9, N-type impurities can be intensively introduced into the Si layer 9, and the NMOS source / drain (N +) can be introduced only into the Si layer 9. Can be formed. Thereafter, the resist pattern 77 is removed from the control gate 17. Thereby, the nonvolatile memory 100 shown in FIGS. 1A to 1C is completed.
It is also possible to form the DiNOR circuit 200 as shown in FIG. 24 by the method described with reference to FIGS. In that case, the support hole h and the groove H may be selectively disposed in a plurality of element isolation regions (that is, regions where the Si layers 5 and 9 are not left) 220 of the DiNOR circuit 200.

  As described above, according to the embodiment of the present invention, electrons can be supplied from the NMOS 30 and holes can be supplied from the PMOS 20 to the common floating gate 8. Then, by selectively supplying electrons and holes to the common floating gate 8, the potential can be changed, and the threshold voltages of the PMOS 20 and NMOS 30 can be controlled. For example, when writing data, electrons can be supplied to the common floating gate 8 to change the threshold voltages of the PMOS 20 and NMOS 30 respectively. At the time of erasing data, holes can be supplied to the common floating gate 8 to recombine the accumulated electrons with the holes, and the threshold voltages of the PMOS 20 and NMOS 30 can be returned to the state before writing.

  In this way, writing and erasing to the common floating gate 8 can be realized by supplying two carriers of electrons and holes, so that the control gate can be used for writing and erasing data compared to the conventional technique. On the other hand, it is not necessary to apply positive and negative voltages at a high voltage, and the high voltage driving circuit can be omitted. Therefore, the chip area of the LSI can be reduced.

  Further, in the nonvolatile memory 100 shown in FIGS. 1A to 1C, since the floating gate 8 is not formed between the control gate 17 and the side surfaces of the Si layers 5 and 9, the control is performed. -Excellent channel controllability by the gate 17, high MOS driving capability, and high-speed reading with low voltage. Further, it is possible to mount the CMOS-LSI with a nonvolatile memory at a low cost because it can be mounted in the same process as the stacked Fin-type CMOS device (for example, see Patent Documents 3 and 4). .

  In the above embodiment, the case where the conductive film 4 is left between the Si substrate 1 and the Si layer 5 as shown in FIGS. 1A to 1C has been described. The film 4 is not necessarily required in the present invention. For example, as shown in FIGS. 22A to 22C, the space between the Si substrate 1 and the Si layer 5 may be constituted only by the insulating film 3. . In such a structure, for example, in FIGS. 9A and 9B, the film thickness of the SiGe layer 51 (see FIG. 2) is set to be thin in advance so that the cavity 61 is completely embedded by the insulating film 65. It is possible to form it.

  Alternatively, as shown in FIGS. 23A to 23C, the Si substrate 1 and the Si layer 5 may be constituted only by the thick insulating layer 82. In such a structure, for example, an SOI wafer 80 having a structure in which an insulating layer 82 and a Si layer 5 are stacked on a Si substrate 1 is prepared, and a SiGe layer 53 and a Si layer 9 are sequentially formed on the SOI wafer 80. The layers can be stacked and thereafter formed by performing a simpler manufacturing process as shown in FIGS. 3 to 11 and FIGS. 16 to 21.

  22 and 23, as in the nonvolatile memory 100 shown in FIG. 1, writing and erasing to the common floating gate 8 are realized by supplying two carriers of electrons and holes. And a high voltage driving circuit can be omitted. Moreover, since the conductive film 4 is replaced with an insulating film (layer), the parasitic capacitance of the Si layer 5 is reduced, which can contribute to an improvement in the operating speed of the MOS formed in the Si layer 5.

  In this embodiment, the Si substrate 1 corresponds to the “substrate” or “semiconductor substrate” of the present invention, the insulating film 3 corresponds to the “first insulating film” of the present invention, and the insulating film 7 corresponds to “ This corresponds to the “second insulating film”. The single crystal Si layer 5 corresponds to the “first semiconductor layer” of the present invention, the single crystal Si layer 9 corresponds to the “second semiconductor layer” of the present invention, and the floating gate 8 corresponds to the “first semiconductor layer” of the present invention. It corresponds to the “charge storage layer”. Further, the PMOS 20 formed on the side surface of the Si layer 5 corresponds to the “first conductivity type MOS transistor” of the present invention, and the NMOS 30 formed on the side surface of the Si layer 9 corresponds to the “second conductivity type MOS transistor” of the present invention. It corresponds to. The SiGe layer 51 corresponds to the “first sacrificial semiconductor layer” of the present invention, and the SiGe layer 53 corresponds to the “second sacrificial semiconductor layer” of the present invention. Further, the support hole h corresponds to the “first groove” of the present invention, and the groove H corresponds to the “second groove” of the present invention. The cavity 61 corresponds to the “first cavity” of the present invention, and the cavity 63 corresponds to the “second cavity” of the present invention.

  In the present invention, the insulating film 7 formed above and below the floating gate 8 in FIGS. 1A to 1C is preferably thinner than the gate insulating film 11. In such a configuration, the insulating film 7 has a smaller potential barrier against carriers (electrons or holes) than the gate insulating film 11, so that carriers can be floated through the insulating film 7 during data writing and erasing. It becomes easy to move to the gate 8.

In the present invention, in FIGS. 1A to 1C, the insulating film 7 has a band gap (that is, an energy difference between the conduction band Ec and the valence band Ev) smaller than that of SiO ₂ , More preferably, the insulating film has a potential barrier (barrier energy) smaller than that of SiO ₂ . Examples of the insulating film having a small potential barrier include a Si ₃ N ₄ film, a Ta ₂ O ₅ film, a BaTiO ₃ film, a ZrO ₂ film, a HfO film, a Y ₂ O ₃ film, and a ZrSiO ₂ film. As described above, when the insulating film 7 is constituted by the Si ₃ N ₄ film or the like, the carrier (electrons or holes) moving from the Si layers 5 and 9 to the floating gate 8 is compared with the SiO ₂ film. Since the potential barrier is reduced, the voltage required for writing and erasing data can be reduced.

Furthermore, in the present invention, in FIGS. 1A to 1C, the floating gate 8 may be replaced with a charge trap film made of an insulating film. That is, the “charge storage layer” of the present invention is not limited to a semiconductor film such as Poly-Si or a metal film. For example, an insulating film such as a Si ₃ N ₄ film or an intrinsic Poly-Si film is used. Such a high resistance semiconductor may be used. Even with such a configuration, similarly to the above-described embodiment, writing and erasing with respect to the charge trapping film can be realized by supplying two carriers of electrons and holes. For example, when writing data, electrons can be supplied to the common charge trapping film to change the threshold voltages of the PMOS 20 and NMOS 30 respectively. When erasing data, holes are supplied to the charge trapping film so that the negative charges of the trapped electrons are canceled by the positive charges of the holes, and the threshold voltages of the PMOS 20 and NMOS 30 are returned to the state before writing. it can. Therefore, compared with the conventional technique, it is not necessary to apply a positive or negative voltage to the control gate at a high voltage at the time of data writing and erasing, and a high voltage driving circuit can be omitted. Further, a semiconductor device capable of writing / erasing data at a low voltage and capable of processing data reading at a high speed with a low voltage is provided.

1 is a diagram showing a configuration example of a nonvolatile memory 100 according to an embodiment. FIG. 3 is a diagram illustrating a method for manufacturing the nonvolatile memory 100 (part 1); FIG. 2 is a diagram illustrating a method for manufacturing the nonvolatile memory 100 (part 2); FIG. 3 is a diagram illustrating a method for manufacturing the nonvolatile memory 100 (No. 3). FIG. 4 is a diagram illustrating a method for manufacturing the nonvolatile memory 100 (part 4); FIG. 5 is a diagram illustrating a method for manufacturing the nonvolatile memory 100 (No. 5). FIG. 6 illustrates a method for manufacturing the nonvolatile memory 100 (No. 6). FIG. 7 shows a method for manufacturing the nonvolatile memory 100 (No. 7). FIG. 8 shows a method for manufacturing the nonvolatile memory 100 (No. 8). FIG. 9 shows a method for manufacturing the nonvolatile memory 100 (No. 9). FIG. 10 shows a method for manufacturing the nonvolatile memory 100 (No. 10). FIG. 11 shows a method for manufacturing the nonvolatile memory 100 (No. 11). FIG. 12 shows a method for manufacturing the nonvolatile memory 100 (No. 12). FIG. 13 shows a method for manufacturing the nonvolatile memory 100 (No. 13). FIG. 14 is a diagram showing a method for manufacturing the nonvolatile memory 100 (No. 14). FIG. 15 is a view showing a method for manufacturing the nonvolatile memory 100 (No. 15). FIG. 16 is a view showing the method of manufacturing the nonvolatile memory 100 (No. 16). FIG. 17 is a view showing a method for manufacturing the nonvolatile memory 100 (No. 17). FIG. 18 shows a method for manufacturing the nonvolatile memory 100 (No. 18). FIG. 19 is a diagram illustrating a method for manufacturing the nonvolatile memory 100 (19); FIG. 20 shows a method for manufacturing the nonvolatile memory 100 (No. 20). The figure which shows the other structural example (the 1) of the non-volatile memory. The figure which shows the other structural example (the 2) of the non-volatile memory. The top view which shows the structural example of the DiNOR circuit 200 which concerns on embodiment. FIG. 2 is a circuit diagram showing a configuration example of a DiNOR circuit 200.

Explanation of symbols

1 Si substrate, 3, 7 insulating film, 5, 9 Si layer, 8 floating gate, 11 gate insulating film, 17 control gate, 20 PMOS, 30 NMOS, 51, 53 SiGe layer, 55, 65 SiO ₂ film, 57, 69 SiN film, 59 support film, 60 support, 61, 63 cavity, 68, 75 conductive film, 70 sidewall, 77 resist pattern, 100 nonvolatile memory, 200 DiNOR circuit, 201 word line, 203 bits Wire, 211, 213, 215 contact electrode, 220 element isolation region, H groove, h support hole, h1 (shallow) support hole, h2 (deep) support hole

Claims (6)

A first semiconductor layer formed on a substrate via a first insulating film;
A second semiconductor layer formed on the first semiconductor layer via a second insulating film;
A first conductivity type MOS transistor formed on at least one side surface of the first semiconductor layer;
A second conductivity type MOS transistor formed on at least one side surface of the second semiconductor layer,
The first conductivity type MOS transistor and the second conductivity type MOS transistor have a common charge storage layer and a common control gate,
The semiconductor device according to claim 1, wherein the common charge storage layer is provided in the second insulating film sandwiched between the first semiconductor layer and the second semiconductor layer. A first semiconductor layer formed on a substrate via a first insulating film;
A second semiconductor layer formed on the first semiconductor layer via a second insulating film;
A first conductivity type MOS transistor formed on at least one side surface of the first semiconductor layer;
A second conductivity type MOS transistor formed on at least one side surface and an upper surface of the second semiconductor layer,
The first conductivity type MOS transistor and the second conductivity type MOS transistor have a common charge storage layer and a common control gate,
The semiconductor device according to claim 1, wherein the common charge storage layer is provided in the second insulating film sandwiched between the first semiconductor layer and the second semiconductor layer.   The common charge storage layer is provided only in the second insulating film sandwiched between the first semiconductor layer and the second semiconductor layer. Semiconductor device.   4. The semiconductor according to claim 1, wherein a drain of the first conductivity type MOS transistor and a drain of the second conductivity type MOS transistor are electrically connected. 5. apparatus. The first semiconductor layer and the second semiconductor layer are silicon, and regarding barrier energy generated by contact with silicon,
The second insulating film is formed of a film having a lower barrier energy than both the gate insulating film of the first conductive MOS transistor and the gate insulating film of the second conductive MOS transistor. The semiconductor device as described in any one of Claims 1-4. Sequentially stacking a first sacrificial semiconductor layer, a first semiconductor layer, a second sacrificial semiconductor layer, and a second semiconductor layer on a semiconductor substrate;
Partially etching the second semiconductor layer, the second sacrificial semiconductor layer, the first semiconductor layer, and the first sacrificial semiconductor layer sequentially to form a first groove penetrating each semiconductor layer;
Forming a support in the first groove to support the first semiconductor layer and the second semiconductor layer;
After forming the support, the second semiconductor layer, the second sacrificial semiconductor layer, the first semiconductor layer, and the first sacrificial semiconductor layer are partially and sequentially etched to expose the side surfaces of the respective semiconductor layers. Forming a second groove to be caused;
The first sacrificial semiconductor layer and the second sacrificial semiconductor layer are more easily etched than the first semiconductor layer and the second semiconductor layer, and the first sacrificial semiconductor layer and the second sacrificial semiconductor layer are etched through the second groove. By etching the second sacrificial semiconductor layer, a first cavity is formed between the semiconductor substrate and the first semiconductor layer, and a second cavity is formed between the first semiconductor layer and the second semiconductor layer. Forming two cavities;
A first insulating film is formed in the first cavity, and a second insulating layer is formed on the upper surface of the first semiconductor layer and the lower surface of the second semiconductor layer facing the second cavity, leaving the second cavity. Forming an insulating film;
After forming the first insulating film and the second insulating film, a first conductivity type MOS transistor is formed on a side surface of the first semiconductor layer facing the second groove, and the second semiconductor layer has the Forming the second conductivity type MOS transistor on a side surface facing the second groove,
In the step of forming the first conductivity type MOS transistor and the second conductivity type MOS transistor,
Forming a common charge storage layer in the second cavity where the second insulating film is formed;
Forming a gate insulating film on each of a side surface of the first semiconductor layer facing the second groove and a side surface of the second semiconductor layer facing the second groove;
A method of manufacturing a semiconductor device, wherein a common control gate is formed from the side surface of the first semiconductor layer to the side surface of the second semiconductor layer so as to cover the gate insulating film.

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