JP2013239516A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve performance of a semiconductor device by achieving microfabrication of the semiconductor device; and to simplify a manufacturing process of the semiconductor device.SOLUTION: A semiconductor device manufacturing method comprises the step of forming on a semiconductor substrate Sb having an SOI region 1A and a bulk silicon region 1B on a top face, an ONO film C2 which is an insulation film formed between the semiconductor substrate Sb of the SOI region 1A and a silicon layer S1, and an ONO film C3 including a charge retention film of a MONOS memory Qb formed in the bulk silicon region 1B, using the same ONO films. With this configuration, a transistor formed in the SOI region 1A and a nonvolatile memory formed in the bulk silicon region 1B are mixed loaded on the one semiconductor substrate Sb.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, for example, a technology effective when applied to a semiconductor device using an SOI (Silicon On Insulator) substrate and a manufacturing method thereof.

  Currently, semiconductor devices using an SOI substrate are used as semiconductor devices capable of suppressing the generation of parasitic capacitance. In the SOI substrate, a BOX (Buried Oxide) film (buried oxide film) is formed on a support substrate made of high-resistance Si (silicon) or the like, and a thin layer (silicon layer) mainly containing Si (silicon) on the BOX film. ). When a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is formed on an SOI substrate, parasitic capacitance generated in a diffusion region formed in a silicon layer can be reduced. For this reason, manufacturing a semiconductor device using an SOI substrate can be expected to improve the integration density and operation speed of the semiconductor device, and to make the latch-up free.

  In addition, in a microcomputer, etc., a technology for mounting a nonvolatile memory such as a flash memory in the device is used to store a program necessary for controlling the microcomputer or to store data necessary for the operation of the device including the microcomputer. It has been. It is known that these nonvolatile memories are formed not on the above-described SOI substrate but on the surface of a semiconductor substrate, for example, on bulk silicon.

  Patent Document 1 (Japanese Patent Laid-Open No. 2011-049580) and Patent Document 2 (Japanese Patent Laid-Open No. 2007-243095) describe a side wall of a memory gate in a split gate type MONOS (Metal Oxide Nitride Oxide Semiconductor) type nonvolatile memory. It is described that a low breakdown voltage region is prevented from being generated in a sidewall-shaped silicon oxide film formed in contact with the substrate.

  In Patent Document 3 (Japanese Patent Laid-Open No. 2007-103629), an SRAM (Static Random Access Memory) memory cell configured using an FD-SOI (Fully Doped SOI) transistor or the like includes a drive transistor. It is described that the memory cell is stably operated by controlling the well potential under the BOX layer.

  In Patent Document 4 (US Patent Application Publication No. 2008/0239789), a semiconductor layer is formed on a back gate via a charge trap film (ONO film), and an upper portion between a drain and a source on the semiconductor layer is formed. Describes forming a nonvolatile memory by forming a gate electrode through a gate insulating film. This nonvolatile memory includes the aforementioned gate electrode, drain and source. Here, it is described that the threshold voltage and drain current of the nonvolatile memory are changed according to the number of majority carriers in the body region between the drain and the source and the amount of charge in the charge trap film.

JP 2011-049580 A JP 2007-243095 A JP 2007-103629 A US Patent Application Publication No. 2008/0239789

  In recent years, with the progress of miniaturization of devices, there has been a problem that variations in characteristics of transistors constituting a microcomputer become remarkable. As a transistor structure capable of reducing variation in characteristics, there is a transistor in which channel impurities are reduced or channel impurities are not used, such as FD-SOI or Fin-FET.

  When an FD-SOI formed on an SOI substrate and a non-volatile memory formed on bulk silicon are used in the device, if an SOI substrate and a bulk silicon substrate are prepared, the number of semiconductor chips provided in the device increases. There is a problem that miniaturization of a semiconductor device becomes difficult.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  Of the embodiments disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A semiconductor device according to one embodiment forms a silicon layer formed over an insulating film on a semiconductor substrate and a field effect transistor formed on the silicon layer, and in another region of the semiconductor substrate, A non-volatile memory having a charge holding film formed in the same layer as the insulating film is formed.

  In another method for manufacturing a semiconductor device, an insulating film formed between a semiconductor substrate and a silicon layer in an SOI region where a field effect transistor is formed is formed in another region of the semiconductor substrate. It is used as a film constituting a tunnel oxide film of a nonvolatile memory.

  According to one embodiment disclosed in the present application, the performance of a semiconductor device can be improved.

2 is a plan layout showing the semiconductor device according to the first embodiment of the present invention; It is sectional drawing which shows the semiconductor device which is Embodiment 1 of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which is Embodiment 1 of this invention. FIG. 4 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 3. It is sectional drawing in the direction orthogonal to sectional drawing shown in FIG. FIG. 5 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 4. It is sectional drawing in the direction orthogonal to sectional drawing shown in FIG. FIG. 7 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 6; It is sectional drawing in the direction orthogonal to sectional drawing shown in FIG. FIG. 9 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 8. FIG. 11 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 10; FIG. 12 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 11; FIG. 13 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 12; 4 is a plan layout showing a semiconductor device according to a second embodiment of the present invention. It is sectional drawing which shows the semiconductor device which is Embodiment 2 of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which is Embodiment 2 of this invention. FIG. 17 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 16; FIG. 18 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 17; It is sectional drawing in the direction orthogonal to sectional drawing shown in FIG. FIG. 19 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 18; It is sectional drawing in the direction orthogonal to sectional drawing shown in FIG. FIG. 21 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 20; FIG. 23 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 22; FIG. 24 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 23; It is sectional drawing in the direction orthogonal to sectional drawing shown in FIG.

  Hereinafter, embodiments will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

(Embodiment 1)
A structure including a MOSFET and a nonvolatile memory according to the present embodiment will be described with reference to the drawings. FIG. 1 shows a planar layout of a nonvolatile memory cell that is a part of the semiconductor device according to the present embodiment. 2 is a cross-sectional view of the semiconductor device according to the present embodiment, including a cross-sectional view taken along line AA of FIG. FIG. 2 shows a semiconductor device according to the present embodiment, which has, for example, an n-channel MOSFET on an SOI substrate and a nonvolatile memory element on a bulk silicon semiconductor substrate.

  The SOI region (first region) 1A is shown on the left side of the cross-sectional view of FIG. 2, and the bulk silicon region (second region) 1B is shown on the right side of the cross-sectional view of FIG. That is, the planar layout shown in FIG. 1 shows the structure of the bulk silicon region 1B (see FIG. 2) in plan view, and the SOI region 1A of FIG. 2 is not shown in FIG.

  As shown in FIG. 1, a plurality of semiconductor substrates Sb (see FIG. 2) extend in the first direction along the main surface of the semiconductor substrate Sb and are arranged in a second direction orthogonal to the first direction. The active region AR arranged in (1) is formed. The active region AR is surrounded by the element isolation region IR, and each active region AR is isolated by the element isolation region IR. On the active region AR, a plurality of gate electrodes CG1 extending in the second direction and arranged in the first direction are formed. FIG. 1 shows a plurality of MONOS memories formed at the intersections of the active region AR and the gate electrode CG1 and arranged in a matrix in a plan view. The plurality of active regions AR function as bit lines, and the plurality of gate electrodes CG1 function as word lines.

  Since the gate electrode CG1 and the active region AR intersect each other in plan view, the plurality of active regions AR and the plurality of gate electrodes CG1 are arranged in a lattice pattern. The active region AR is a semiconductor region, the element isolation region IR is an insulating film including, for example, a silicon oxide film, and the gate electrode CG1 is a semiconductor film including, for example, polysilicon. Contact plugs Cp connected to the upper surface of the active region AR are formed at both ends in the extending direction (first direction) of the active region AR.

  In FIG. 2, the SOI region 1A and the bulk silicon region 1B are shown separately on the left and right, but the SOI region 1A and the bulk silicon region 1B are formed on the same semiconductor substrate Sb, and the lower semiconductor substrates are respectively provided. Sb is the same substrate. As shown in FIG. 2, on the semiconductor substrate Sb in the SOI region 1A, for example, a logic circuit of a microcomputer is provided on a silicon layer (SOI layer, semiconductor layer) S1 formed via an ONO film C2 which is an insulating film. A plurality of n-channel MOSFETs Qa are formed. MOSFET Qa is a field effect transistor having a relatively lower breakdown voltage than a high breakdown voltage MOSFET used in an I / O circuit or the like.

  A MONOS memory Qb, which is a MONOS nonvolatile memory, is formed on the semiconductor substrate Sb in the bulk silicon region 1B. FIG. 1 shows a diagram in which five gate electrodes CG1 are arranged in the first direction on the active region AR surrounded by the element isolation region IR, but is a cross-sectional view on the right side of FIG. In the cross-sectional view taken along line A), the number of gate electrodes CG1 arranged in the first direction, that is, the number of MONOS memories Qb is three in order to make the drawing easier to understand.

  The SOI region here is a region in which a silicon layer is formed on a semiconductor substrate Sb via an insulating film such as a BOX film, and a semiconductor element such as a MOSFET is formed on the silicon layer. Unlike the SOI region, the bulk silicon region is a region where a semiconductor element such as a nonvolatile memory is formed on the upper surface of the semiconductor substrate without the BOX film and the silicon layer interposed therebetween.

  The MONOS memory here has a gate electrode through an ONO (Oxide Nitride Oxide) film, which is a laminated film formed in the order of an oxide film, a nitride film, and an oxide film on a semiconductor substrate. This is a non-volatile memory device that traps and accumulates charges in the nitride film. There are two methods for taking in and out the electric charge, and one is a method in which writing and erasing are performed by taking in and out electrons with a tunnel current over the entire surface of the nitride film under the gate electrode. Another method is a method of performing writing / erasing using hot carriers (hot holes or hot electrons). The method using the tunnel current can increase the number of times of rewriting and ensure high reliability. On the other hand, the method using hot carriers can reduce the voltage of the write / erase operation and increase the speed.

  In the SOI region 1A, between the element isolation regions IR embedded in the upper surface of the semiconductor substrate Sb, the upper surface of the semiconductor substrate Sb is an ONO film C2 formed instead of the BOX film and the silicon layer S1 on the ONO film C2. Are all covered. Here, in the SOI region 1A, the extension region 5 constituting the MOSFET Qa is formed not in the upper surface of the semiconductor substrate Sb but in the silicon layer S1. On the other hand, in the bulk silicon region 1B, between the plurality of element isolation regions IR on the upper surface of the semiconductor substrate Sb, the upper surface of the semiconductor substrate Sb is covered with the ONO film C3 only in the region immediately below the gate electrode CG1. In addition, an extension region 4 constituting the MONOS memory Qb is formed on the upper surface of the semiconductor substrate Sb.

  The semiconductor substrate Sb is a support substrate made of, for example, Si (silicon), and the element isolation region IR is an insulating film made of a silicon oxide film or the like. An ONO film C2 is formed on the main surface of the semiconductor substrate Sb in the SOI region 1A. The ONO film C2 is a stacked film in which a silicon oxide film (bottom oxide film) Ox1, a silicon nitride film SN, and a silicon oxide film (top oxide film) Ox2 are sequentially stacked from the semiconductor substrate Sb side. On the left side of the cross-sectional view showing the SOI region 1A in FIG. 2, the cross-sectional view of the laminated structure of the ONO film C2 is enlarged. On the ONO film C2, a silicon layer S1 which is a semiconductor layer made of single crystal silicon having a resistance of about 1 to 10 Ωcm is formed.

  In the silicon layer S1, an extension region 5 which is a semiconductor region into which an n-type impurity (for example, As (arsenic)) is introduced at a relatively low concentration is formed. That is, the silicon layer S1 includes the extension region 5.

  A gate electrode (conductor layer) G1 made of, for example, polysilicon is formed on the silicon layer S1 in the SOI region 1A via a gate insulating film (insulating film) 2, and an oxide film is formed on the sidewall of the gate electrode G1, for example Sidewalls SW made of a silicon film or the like are formed in a self-aligning manner. In plan view, the extension region 5 is formed so as to sandwich the gate electrode G1 in the first direction. That is, a pair of extension regions 5 are formed in the silicon layer S1 on both sides of the gate electrode G1. In the silicon layer S1 immediately below the gate electrode G1, there is a region where the extension region 5 is not formed, and this region becomes a channel region of the MOSFET Qa.

  In the SOI region 1A, an epitaxial layer (semiconductor layer) Ep1 is formed on the silicon layer S1 exposed from the gate electrode G1, the gate insulating film 2, and the sidewall SW so as to sandwich the gate electrode G1. An n-type impurity (for example, As (arsenic)) is introduced into each of the pair of epitaxial layers Ep1 formed on both sides of the gate electrode G1, thereby forming a diffusion layer 10 that is an n-type semiconductor layer. Yes. An n-type impurity (for example, As (arsenic)) is introduced into the diffusion layer 10 at a higher concentration than the extension region 5. The epitaxial layer Ep1 is a semiconductor layer formed for the purpose of preventing difficulty in recovering the damage received by the silicon layer S1 when impurities are implanted into the silicon layer S1.

  Of the semiconductor layers on both sides of the gate electrode G1, one diffusion layer 10 and the extension region 5 constitute the source region of the MOSFET Qa, and the other diffusion layer 10 and extension region 5 constitute the drain region of the MOSFET Qa. Here, the case where an n-type impurity (for example, As (arsenic)) is introduced into the entire region of the epitaxial layer Ep1 and the diffusion layer 10 is formed in the region has been described. The impurity to be formed may be introduced into a part of the silicon layer S1 below the epitaxial layer Ep1.

  Since the epitaxial layer Ep1 is formed on the silicon layer S1 by the epitaxial growth method, the height of the upper surface of the epitaxial layer Ep1 is higher than the upper surface of the silicon layer S1 and higher than the upper surface of the gate insulating film 2. The MOSFET Qa is a field effect transistor having the silicon layer S1 as a channel region, a gate electrode G1, and source / drain regions.

  As described above, the source / drain region includes the extension region 5 and the diffusion layer 10 and is formed on the semiconductor layer. In other words, the source / drain regions of the MOSFET Qa are formed not in contact with the upper surface of the semiconductor substrate Sb but in contact with the upper surface of the silicon layer S1. Therefore, the channel region of the MOSFET Qa is formed not in the upper surface of the semiconductor substrate Sb but in the silicon layer S1. The MOSFET Qa is, for example, a fully depleted transistor (FD-SOI transistor).

  In the bulk silicon region 1B, the MONOS memory Qb including the epitaxial layer Ep2 is formed on the semiconductor substrate Sb not having the SOI structure on the upper portion. That is, the MONOS memory Qb in the bulk silicon region 1B has a source / drain region formed by implanting impurities into the upper surface of the semiconductor substrate Sb and the epitaxial layer Ep2 using a part of the upper surface of the semiconductor substrate Sb as a channel region. Yes. That is, the source / drain regions of the MONOS memory Qb are formed on the semiconductor substrate Sb. In other words, the source / drain regions of the MONOS memory Qb are formed in contact with the upper surface of the semiconductor substrate Sb. Therefore, the channel region of the MONOS memory Qb is formed on the upper surface of the semiconductor substrate Sb.

  An ONO film C3, which is a gate insulating film of the MONOS memory Qb, is formed on and in contact with the upper surface of the semiconductor substrate Sb, and a gate electrode (conductor layer) CG1 made of, for example, polysilicon via the ONO film C3 on the semiconductor substrate Sb. A sidewall SW made of, for example, a silicon oxide film is formed in a self-aligned manner on the sidewall of the gate electrode CG1. As described above, the MONOS memory Qb forms an n-channel field effect transistor.

  The ONO film C3 is the same layer as the ONO film C2, and has a structure in which a silicon oxide film Ox1, a silicon nitride film SN, and a silicon oxide film Ox2 are sequentially stacked on the semiconductor substrate Sb, similarly to the ONO film C2. ing. Since the ONO films C2 and C3 are films formed by processing and separating the ONO film formed on the entire main surface of the semiconductor substrate Sb in the manufacturing process of the semiconductor device, as will be described later, It has a laminated structure.

  In addition, the film | membrane of the same layer here refers to the film | membrane integrated before it isolate | separated by processing. That is, when a single film is originally processed into a plurality of films by an etching method or the like, each of the separated films is in the same layer. Therefore, it can be considered that the films in the same layer have the same film thickness, film quality, composition, or internal laminated structure. Here, since the ONO film C2 and the ONO film C3 are films of the same layer, a silicon nitride film (charge holding film) SN is sandwiched between the two silicon oxide films Ox1 and Ox2. It has a laminated structure. Further, the silicon oxide films Ox1, the silicon nitride films SN, or the silicon oxide films Ox2 constituting the ONO films C2 and C3 all have the same film thickness and the same composition.

  On the upper surface of the semiconductor substrate Sb, an extension region 4 which is a semiconductor region into which an n-type impurity (for example, As (arsenic)) is introduced at a relatively low concentration is formed so as to sandwich the gate electrode CG1 in plan view. Yes. That is, a pair of extension regions 4 is formed on the upper surface of the semiconductor substrate Sb on both sides in the gate length direction (first direction) of the gate electrode CG1. There is a region where the extension region 4 is not formed on the upper surface of the semiconductor substrate Sb immediately below the gate electrode CG1, and this region becomes a channel region of the MONOS memory Qb.

  In the bulk silicon region 1B, an epitaxial layer (semiconductor layer) Ep2 is formed on the semiconductor substrate Sb exposed from the gate electrode CG1, the ONO film C2, and the sidewall SW so as to sandwich the gate electrode CG1. An n-type impurity (for example, As (arsenic)) is introduced into each of the pair of epitaxial layers Ep2 formed on both sides of the gate electrode CG1, thereby forming a diffusion layer 9 that is an n-type semiconductor layer. Yes. An n-type impurity (for example, As (arsenic)) is introduced into the diffusion layer 9 at a higher concentration than the extension region 4.

  Of the semiconductor layers on both sides of the gate electrode CG1, one diffusion layer 9 and the extension region 4 constitute a source region of the MONOS memory Qb, and the other diffusion layer 9 and the extension region 4 constitute a drain region of the MONOS memory Qb. doing. Here, a case is described in which an n-type impurity (for example, As (arsenic)) is introduced into the entire region of the epitaxial layer Ep2, and the diffusion layer 9 is formed in that region. The impurity to be formed may be introduced into a part of the semiconductor substrate Sb below the epitaxial layer Ep2.

  Since the epitaxial layer Ep2 is formed on the semiconductor substrate Sb by the epitaxial growth method, the height of the upper surface of the epitaxial layer Ep2 is higher than the upper surface of the semiconductor substrate Sb and higher than the upper surface of the ONO film C3. The MONOS memory Qb is a nonvolatile memory element having a channel region on the upper surface of the semiconductor substrate Sb, a gate electrode CG1, source / drain regions, and a silicon nitride film SN constituting the ONO film C3 as a charge retention film. is there. As described above, the source / drain region includes the extension region 4 and the diffusion layer 9.

  As described above, the semiconductor device according to the present embodiment has the SOI region 1A and the bulk silicon region 1B on one semiconductor substrate Sb, the MOSFET Qa in the SOI region 1A, and the MONOS memory in the bulk silicon region 1B. Qb is included. When an SOI substrate is used for a semiconductor device, it is conceivable to form a BOX film made of a silicon oxide film between the semiconductor substrate and the silicon layer on the upper surface thereof, but here, on the semiconductor substrate Sb in the SOI region 1A. For this, an ONO film C2 is formed instead of the BOX film. Since the ONO film C2 is an insulating film including a silicon oxide film and a silicon nitride film, similarly to the BOX film, the semiconductor substrate Sb and the silicon layer S1 are insulated and separated from the semiconductor substrate Sb in the SOI region 1A. It can be used to form the silicon layer S1.

  As shown in FIG. 2, adjacent MOSFETs Qa in SOI region 1A are separated by element isolation region IR and do not share a source region or a drain region, but adjacent MONOS memory in bulk silicon region 1B. The element isolation region IR is not formed between Qb, and the MONOS memories Qb adjacent in the first direction share each other's source region or drain region. In the SOI region 1A, the MOSFETs Qa adjacent in the first direction may share the source / drain region.

  Further, the contact plug Cp is not connected on the diffusion layer 9 between the adjacent gate electrodes CG1, and the contact plug Cp is connected only to the diffusion layers 9 at both ends of the plurality of MONOS memories Qb arranged in the first direction. Yes. This is also shown in the layout of FIG. The active region AR shown in FIG. 1 is a region including the upper surface of the semiconductor substrate exposed from the element isolation region IR, the diffusion layer 9 aligned in the first direction, and the extension region 4 in FIG.

  In the present embodiment, the ONO film C3 including the charge holding film of the MONOS memory Qb in the bulk silicon region 1B is the same layer as the ONO film C2 in the SOI region 1A. Therefore, the MONOS memory Qb is formed at a lower position as a whole, that is, at a position closer to the semiconductor substrate Sb than the MOSFET Qa formed on the silicon layer S1 on the ONO film C2. That is, for example, the height of the lower surface of the epitaxial layer Ep1 is higher than the height of the lower surface of the epitaxial layer Ep2. Further, the upper surface of the extension region 5 is located higher than the upper surface of the extension region 4. The lower surface of the gate insulating film 2 is located higher than the lower surface of the ONO film C3.

  As described above, the SOI region 1A and the bulk silicon region 1B are provided on one semiconductor substrate Sb, the relatively low breakdown voltage MOSFET Qa that constitutes a logic circuit or the like is formed in the SOI region 1A, and the bulk silicon region 1B is formed. By forming the MONOS memory Qb that is a non-volatile memory, a transistor formed on the SOI substrate and a non-volatile memory element can be mounted together.

  Therefore, for example, a nonvolatile memory that stores a program for operating a microcomputer and a transistor that forms a logic circuit that executes the program can be arranged on one substrate (chip). Accordingly, it is possible to prevent the semiconductor device from becoming large by forming the SOI substrate having the transistor and the bulk silicon substrate having the nonvolatile memory in separate semiconductor chips. That is, since the semiconductor device can be miniaturized, the performance of the semiconductor device can be improved.

As shown in FIG. 2, silicide layers 15 are formed on the upper surfaces of the diffusion layers 9 and 10 and the gate electrodes G1 and CG1, respectively. For example, the silicide layer 15 is mainly made of NiSi ₂ (nickel silicide). Further, not only nickel silicide but also titanium silicide, cobalt silicide, or platinum silicide may be used. The silicide layer 15 reduces the sheet resistance of the gate electrodes G1, CG1, and the diffusion layers 9 and 10, and reduces the contact resistance with the contact plug Cp above them.

  An insulating film (etching stopper film) 16 is formed so as to cover the surfaces of the silicide layer 15, the sidewall SW, and the element isolation region IR, and the film thickness is larger than that of the insulating film 16 on the insulating film 16. A thick interlayer insulating film 17 is formed. In the laminated film composed of the insulating film 16 and the interlayer insulating film 17, a plurality of contact holes (connection holes) exposing the upper surface of the silicide layer 15 are formed penetrating from the upper surface to the lower surface of the laminated film. A contact plug Cp mainly made of, for example, W (tungsten) is formed inside each of the plurality of contact holes. The contact plug Cp is a connection member having a columnar shape.

  On the interlayer insulating film 17 and the contact plug Cp, a wiring 21 that is a pattern of a metal film electrically connected to the contact plug Cp is formed. The wiring 21 is a metal wiring for supplying a predetermined potential to the source region, the drain region, and the gate electrodes G1 and CG1 of the MOSFET Qa and the MONOS memory Qb, and mainly includes, for example, Cu (copper). In FIG. 2, the contact plug Cp and the wiring 21 connected to the gate electrodes G1 and CG1 are not shown. The wiring 21 is a damascene wiring formed in a wiring trench that penetrates a laminated film composed of an insulating film (etching stopper film) 19 and an interlayer insulating film 20 that are sequentially laminated on the interlayer insulating film 17. For example, the insulating films 16 and 19 are made of a silicon nitride film, the interlayer insulating film 17 is made of a silicon oxide film, and the interlayer insulating film 20 is made of SiOC.

  As described above, there are the SOI region 1A and the bulk silicon region 1B on the semiconductor substrate Sb constituting the semiconductor device of the present embodiment, and the SOI region 1A and the bulk silicon region 1B are suitable for the respective regions. A semiconductor element is formed. That is, in the SOI region 1A, a low-breakdown-voltage MOSFET Qa that requires a signal processing function at a particularly high speed is formed, thereby improving the integration density of elements in the SOI region 1A, reducing the power consumption, or improving the operation speed. Such effects can be obtained. Such an advantage can be obtained because the value of the current flowing through the MOSFET Qa is small.

  Further, an ONO film C2 is formed in place of the BOX film in the SOI region 1A, and the ONO film C3, which is the same layer as the ONO film C2, is used as the charge holding film of the MONOS memory Qb, so that the bulk silicon region 1B is formed. The MONOS memory Qb can be formed, and the MOSFET Qa on the SOI substrate and the MONOS memory Qb which is a nonvolatile memory can be mixedly mounted on the same substrate.

  Next, the manufacturing process of the MOSFET and the MONOS memory according to the present embodiment will be described with reference to FIGS. 3, 4, 6, 8, and 10 to 13 are semiconductor devices according to the present embodiment, each having an n-channel MOSFET and a MONOS memory on the SOI region and in the bulk silicon region. It is sectional drawing in the manufacturing process of an apparatus. 5, FIG. 7, and FIG. 9 are cross-sectional views in directions orthogonal to the cross sections shown in FIG. 4, FIG. 6, and FIG.

  First, as shown in FIG. 3, a semiconductor substrate Sb having an ONO film C1 and a silicon layer (SOI layer) S1 stacked thereon is prepared. The semiconductor substrate Sb is a support substrate made of Si (silicon), and the ONO film C1 on the semiconductor substrate Sb is an insulating film made of a laminated body having a thickness of 10 to 20 nm, for example. The silicon layer S1 on the ONO film C1 has a resistance of about 1 to 10 Ωcm, and is made of, for example, single crystal silicon having a thickness of 10 to 20 nm.

  When the ONO film C1 and the silicon layer S1 are formed on the semiconductor substrate Sb, first, two silicon wafers (semiconductor substrates) are prepared, and the first silicon oxide film is formed on the upper surface of one silicon wafer (semiconductor substrate Sb). After the formation, a silicon nitride film is formed on the first silicon oxide film, and then a second silicon oxide film is formed on the silicon nitride film. The first silicon oxide film formed on the upper surface of the silicon wafer (semiconductor substrate Sb) is formed using, for example, a thermal oxidation method, and the silicon nitride film is formed using, for example, a CVD (Chemical Vapor Deposition) method. The second silicon oxide film on the silicon nitride film is formed by oxidizing SiN, or is formed (deposited) using a CVD method or the like. A third silicon oxide film is also formed on the upper surface of the other silicon wafer by using, for example, a thermal oxidation method.

  Next, the top surfaces of the two silicon wafers are bonded together to form a single substrate. Here, it is the upper surface of one silicon wafer, that is, the surface on which the first silicon oxide film, the silicon nitride film, and the second silicon oxide film are sequentially laminated, and the upper surface of the other silicon wafer, which is the third oxide film. The surface on which the silicon film is formed is bonded and bonded by applying high heat and pressure. Thus, a structure in which the first silicon oxide film, the silicon nitride film, the second silicon oxide film, the third silicon oxide film, and the silicon wafer are stacked on the semiconductor substrate Sb can be formed.

  The first silicon oxide film here is the silicon oxide film Ox1 shown in FIG. 2, and the film thickness thereof is, for example, 5 nm. The silicon nitride film is the silicon nitride film SN shown in FIG. 2, and the film thickness is, for example, 5 nm. The second silicon oxide film and the third silicon oxide film are the silicon oxide film Ox2 shown in FIG. 2, and the total thickness of the two layers is, for example, 10 nm. In the following description, it is assumed that the second silicon oxide film and the third silicon oxide film are one silicon oxide film Ox2. As shown in FIG. 3, the silicon oxide film Ox1, the silicon nitride film SN, and the silicon oxide film Ox2 constitute an ONO film C1.

  Next, the back surface of the silicon wafer in contact with the silicon oxide film Ox2, that is, the surface of the silicon wafer exposed above the semiconductor substrate Sb and opposite to the surface in contact with the silicon oxide film Ox2, for example, Smart A silicon layer S1 made of the silicon wafer is formed by peeling using the Cut method. The film thickness of the silicon layer S1 is about 10 to 20 nm, and is 10 to 15 nm, for example. Through the above steps, the structure shown in FIG. 3 is obtained. In FIG. 3, the separate areas of one substrate are shown separately on the left and right. In addition, the stacked structure of the silicon oxide film Ox1, the silicon nitride film SN, and the silicon oxide film Ox2 constituting the ONO film C1 is shown in an enlarged manner.

  Next, as shown in FIG. 4, by using a well-known STI (Shallow Trench Isolation) method, an element isolation region IR made of an insulating film that penetrates the silicon layer S1 and the ONO film C1 and reaches the intermediate depth of the semiconductor substrate Sb. Form.

  That is, by sequentially dry-etching the silicon layer S1, ONO film C1 (see FIG. 3) and the semiconductor substrate Sb using a photoresist film (not shown) as an etching mask, a groove (element) is formed in the semiconductor substrate Sb in the element isolation formation scheduled region. After the separation grooves are formed, the photoresist film is removed by ashing. Subsequently, for example, a two-layer insulating film is stacked on the main surface of the semiconductor substrate Sb including the inside (side wall and bottom) of the groove, thereby filling the inside of the groove. These members of the laminated insulating film are, for example, silicon oxide films and are formed (deposited) by a CVD method or the like.

  Thereafter, the laminated insulating film is polished by a CMP (Chemical Mechanical Polishing) method to expose the upper surface of the silicon layer S1, thereby forming an element isolation region (element isolation) IR made of the laminated insulating film. Form. Thereby, the ONO film C1 is separated into the ONO film C2 and the ONO film C3.

  Here, as shown in FIG. 4, the element isolation region IR made of the laminated insulating film is shown as a single layer film. In the present embodiment, the element isolation region IR has been described as being formed by the STI method, but may be formed by a LOCOS (Local Oxidization of Silicon) method.

  Although not shown, after forming the element isolation region IR, a p-type impurity (for example, B (boron)) is implanted into the semiconductor substrate Sb by an ion implantation method. This impurity implantation forms a p-type well in the semiconductor substrate Sb and further adjusts the threshold value of the MOSFET Qa formed on the silicon layer S1 or the threshold value of the MONOS memory Qb formed on the semiconductor substrate Sb. It is intended.

  Here, FIG. 5 shows a cross section of the semiconductor substrate Sb in the second direction, which is a point in time when the element isolation region IR is formed and is perpendicular to the cross sectional view shown in FIG. FIG. 5 is a cross-sectional view at the same position as the cross section taken along line BB in FIG. In FIG. 5, in order to make the drawing easier to understand, the numbers formed in the second direction such as the element isolation region IR are partially omitted. As shown in FIG. 5, a plurality of element isolation regions IR are formed side by side on the upper surface of the semiconductor substrate Sb, and an ONO film C3 is interposed on the semiconductor substrate Sb between adjacent element isolation regions IR. Thus, a silicon layer S1 is formed.

  Next, as shown in FIG. 6, a photoresist film (not shown) that covers the upper surface of a part of the silicon layer S1 defined by the element isolation region IR is formed. Here, the silicon layer S1 on the ONO film C2 is covered, and the silicon layer S1 on the ONO film C3 is exposed from the photoresist film. Subsequently, using the photoresist film as a mask, the silicon layer S1 exposed from the photoresist film is removed using, for example, a wet etching method, and the upper surface of the ONO film C3 is exposed. Thereafter, the photoresist film is removed. As a result, a laminated film composed of the ONO film C2 and the silicon layer S1 remains on the semiconductor substrate Sb in the region covered with the photoresist film.

  At this time, as shown in FIG. 7, even in the cross section along the second direction, the upper surface of the ONO film C3 is exposed by removing the silicon layer S1 on the ONO film C3.

  Next, as shown in FIG. 8, gate electrodes G1 and CG1 and a gate insulating film 2 are formed on the semiconductor substrate, and the ONO film is processed to partially expose the upper surface of the semiconductor substrate Sb. Here, a region having an SOI structure in which the ONO film C2 and the silicon layer S1 are formed is referred to as an SOI region 1A. In FIG. 8, the SOI region 1A is shown on the left side of the figure. In the active region sandwiched between the element isolation regions IR, the upper surface of the semiconductor substrate Sb, that is, a region where the bulk silicon is exposed from the ONO film C3 and the silicon layer S1 is not formed is referred to as a bulk silicon region 1B. In FIG. 8, the bulk silicon region 1B is shown on the right side of the figure.

  When the gate electrodes G1 and CG1 and the gate insulating film 2 are formed on the semiconductor substrate and the ONO film is processed, first, a silicon oxide film is formed on the silicon layer S1 in the SOI region 1A by using a thermal oxidation method or the like. An insulating film is formed. Thereafter, a polysilicon film is formed (deposited) on the insulating film in the SOI region 1A and on the ONO film C3 in the bulk silicon region 1B by using a CVD method or the like.

  Subsequently, after patterning the polysilicon film, the insulating film, and the ONO film C3 using a photolithography technique and a dry etching method, cleaning is performed to remove etching residues and the like. Thus, the gate electrode G1 made of the polysilicon film is formed on the silicon layer S1 in the SOI region 1A via the gate insulating film 2 made of the insulating film. Further, the upper surface of the semiconductor substrate Sb is exposed by patterning the polysilicon film and the ONO film C3 as described above, and the polysilicon film is disposed on the semiconductor substrate Sb in the bulk silicon region 1B via the ONO film C3. A gate electrode CG1 made of a film is formed.

  For example, the thickness of the gate insulating film 2 is about 2 to 3 nm, and the thickness of the ONO film C3 is about 10 to 20 nm. The film thicknesses of the gate electrodes G1 and CG1 are, for example, about 100 to 140 nm.

  Note that the polysilicon film constituting the gate electrodes G1 and CG1 is a low-resistance n-type semiconductor film (doped polysilicon) by ion implantation of an n-type impurity such as P (phosphorus) or As (arsenic). Film). The polysilicon film, which was an amorphous silicon film at the time of film formation, can be changed to a polycrystalline silicon film by heat treatment after film formation (after ion implantation).

  Further, as shown in FIG. 9 which is a cross-sectional view of the structure shown in FIG. 8 in the second direction of the bulk silicon region 1B, the second direction (horizontal of FIG. 9) is formed on the ONO film C3 and the element isolation region IR. A gate electrode CG1 having a pattern extending in the direction) is formed. Thus, the pattern of the gate electrode CG1 extending in the second direction corresponds to the pattern of the gate electrode CG1 shown in FIG.

Next, as shown in FIG. 10, n-type impurities such as P (phosphorus) or As (arsenic) are ion-implanted into the upper surface of the silicon layer S1 in the SOI region 1A, so that a part immediately below the gate electrode G1. A pair of extension regions 5 which are n ⁻ type semiconductor regions are formed in the silicon layer S1 excluding. That is, in the SOI region 1A, a pair of extension regions 5 are formed in the silicon layer S1 on both sides of the gate electrode G1.

Similarly, an n-type impurity such as P (phosphorus) or As (arsenic) is ion-implanted into the upper surface of the semiconductor substrate Sb in the bulk silicon region 1B, thereby laterally extending the gate electrode CG1 in the gate length direction (first direction). A pair of extension regions 4 which are n ⁻ type semiconductor regions are formed on the upper surface of the semiconductor substrate Sb. That is, in the bulk silicon region 1B, a pair of extension regions 4 are formed on the upper surface of the semiconductor substrate Sb in the regions on both sides of the gate electrode CG1.

  Note that either of the manufacturing processes of the extension regions 4 and 5 described above may be performed first. Each of the extension regions 4 and 5 may be formed by the same ion implantation process, or may be formed by separate processes in the SOI region 1A and the bulk silicon region 1B. When each of the extension regions 4 and 5 is formed in a separate process, when forming one extension region, for example, a photoresist film is used as a mask so that impurity ions are not introduced into the region in which the other extension region is formed. To.

  Thereafter, the sidewall SW is formed on the side wall of the stacked body including the gate electrode G1 and the gate insulating film 2, and the sidewall SW is formed on the side wall of the stacked body including the gate electrode CG1 and the ONO film C3. For example, the sidewall SW is formed by sequentially depositing a silicon nitride film and a silicon oxide film on the entire surface of the semiconductor substrate Sb by using the CVD method, and then combining the silicon nitride film and the silicon oxide film by using a dry etching method or the like. It can be formed by removing the part and exposing the upper surfaces of the silicon layer S1 and the semiconductor substrate Sb. That is, the sidewall SW is constituted by, for example, a laminated film of the silicon oxide film and the silicon nitride film.

  Next, as shown in FIG. 11, epitaxial layers Ep1 and Ep2 are formed on the exposed upper surface of the silicon layer S1 and the exposed upper surface of the semiconductor substrate Sb, respectively, using an epitaxial growth method. At this time, as a method of not forming the epitaxial layer on the upper surfaces of the gate electrodes G1 and CG1, it is conceivable to cover the upper surfaces of the gate electrodes G1 and CG1 with a silicon nitride film or the like.

  In the case of using the silicon nitride film, for example, in the process described with reference to FIG. 8, after forming the silicon nitride film on the polysilicon film, the silicon nitride film is patterned using a photoresist film, and then the silicon nitride film is patterned. It is conceivable to process the gate electrodes G1, CG1, the gate insulating film 2, and the ONO film C3 using the silicon nitride film as a mask. In this case, the silicon nitride film is removed after the epitaxial layers Ep1 and Ep2 are formed.

  Subsequently, in the SOI region 1A, n-type impurities (for example, As (arsenic)) are ion-implanted from above the silicon layer S1 at a relatively high concentration using the gate electrode G1 and the sidewall SW as a mask. In the SOI region 1A, an n-type impurity (for example, As (arsenic)) is implanted into the epitaxial layer Ep1 exposed from the gate electrode G1 and the sidewall SW, whereby the diffusion layer 10 is formed. Thus, in the SOI region 1A, an n-channel MOSFET Qa including the gate electrode G1, the extension region 5, and the diffusion layer 10 with the silicon layer S1 as a channel region is formed. The diffusion layer 10 and the extension region 5 are semiconductor regions constituting the source / drain regions of the MOSFET Qa in the SOI region 1A.

  In the bulk silicon region 1B, n-type impurities (for example, As (arsenic)) are ion-implanted at a relatively high concentration from above the semiconductor substrate Sb using the gate electrode CG1 and the sidewall SW as a mask. In the bulk silicon region 1B, the diffusion layer 9 is formed by implanting n-type impurities (for example, As (arsenic)) into the epitaxial layer Ep2 exposed from the gate electrode CG1 and the sidewall SW. Thus, an n-channel MONOS memory Qb including the gate electrode CG1, the ONO film C3, the extension region 4 and the diffusion layer 9 is formed in the bulk silicon region 1B with the main surface of the semiconductor substrate Sb as a channel region. The diffusion layer 9 and the extension region 4 are semiconductor regions constituting source / drain regions of the MONOS memory Qb in the bulk silicon region 1B.

  In the ion implantation for forming the diffusion layers 9 and 10, since the semiconductor layer in the region where the impurity ions are implanted is damaged and becomes amorphous, the ion implantation is performed after the ion implantation for the purpose of recrystallization. Annealing (heat treatment) at about 1000 ° C. is performed.

  Each of the source / drain regions of the MOSFET Qa and the MONOS memory Qb has an LDD (Lightly Doped Drain) structure having a diffusion layer into which impurities are introduced at a high concentration and an extension region containing impurities at a low concentration. That is, the impurity concentration of the diffusion layers 9 and 10 is higher than the impurity concentration of the extension regions 4 and 5.

  Next, as shown in FIG. 12, a silicide layer 15 is formed on the upper surfaces of the gate electrodes G1, CG1, and the diffusion layers 9 and 10 using a known salicide technique, and then the MOSFET Qa and the MONOS memory Qb are Cover with an insulating film (etching stopper film) 16. The insulating film 16 is made of, for example, a silicon nitride film, and is formed on the entire surface of the semiconductor substrate Sb by using a CVD method or the like.

  Next, as shown in FIG. 13, an interlayer insulating film 17 is formed on the insulating film 16. The interlayer insulating film 17 is made of, for example, a silicon oxide film, and is formed on the entire surface of the semiconductor substrate Sb by using a CVD method or the like. Thereafter, a plurality of contact plugs Cp penetrating through the interlayer insulating film 17 and the insulating film 16 and connected to the silicide layer 15 are formed. For the contact plug Cp, a contact hole formed using a photolithography technique and a dry etching method is filled with, for example, a tungsten (W) film, and then the tungsten film on the interlayer insulating film 17 is removed using a CMP method. Thus, a tungsten film is buried in the contact hole.

  Subsequently, an insulating film (etching stopper film) 19 and an interlayer insulating film 20 are sequentially formed on the interlayer insulating film 17, and are formed on the upper surface of the contact plug Cp in a wiring groove that penetrates the insulating film 19 and the interlayer insulating film 20. By forming the connected wiring 21, the semiconductor device of this embodiment shown in FIG. 13 is completed. The insulating film 19 is made of, for example, a silicon nitride film, and the interlayer insulating film 20 is made of, for example, SiOC. The insulating film 19 and the interlayer insulating film 20 can be formed by, for example, a CVD method. At this point, the gate electrode CG1 has a shape extending in the second direction so as to cover the plurality of element isolation regions IR and the plurality of ONO films C3, similarly to the structure shown in FIG. Yes.

  The wiring 21 is a metal wiring mainly including, for example, copper (Cu), and is specified to the source / drain region and the gate electrode G1 of the MOSFET Qa and the source / drain region and the gate electrode CG1 of the MONOS memory Qb via the contact plug Cp. Is provided to supply a potential of. In FIG. 13, the contact plug Cp and the wiring 21 connected to the gate electrodes G1 and CG1 are not shown. Further, the contact plug Cp is not connected to a part of the source / drain region of the MONOS memory Qb, and the contact plug Cp is provided only in the source / drain region at both ends of the plurality of source / drain regions arranged in the first direction. Connected.

  Below, the effect of the manufacturing method of the semiconductor device of this Embodiment is demonstrated.

  In a semiconductor substrate having an SOI region and a bulk silicon region, when a MOSFET is formed in the SOI region and a MONOS memory is formed in the bulk silicon region, the SOI region is formed on a silicon layer formed on the semiconductor substrate via a BOX oxide film. It is conceivable to form an element and form a memory element including an ONO film on a semiconductor substrate not covered with the BOX film in the bulk silicon region. In this case, after forming the SOI substrate having the BOX film and the silicon layer on the semiconductor substrate, the BOX film and the silicon layer in the bulk silicon region are removed, and then the ONO film is formed on the semiconductor substrate, and then the SOI region is formed. It is conceivable to perform a step of removing the ONO film.

  When the above process is used, a process for forming both the ONO film and the BOX film is required, and a process for removing the ONO film from the SOI region before forming the gate electrode is required. There is a problem that the manufacturing process becomes complicated and the manufacturing cost increases. As described above, the problem that the film forming process and the processing process increase is that the bulk silicon region is not formed, and the MOSFET and the MONOS memory are formed on the SOI substrate in which the upper surface of the semiconductor substrate is entirely covered with the BOX film and the silicon layer. It also occurs when formed.

  Therefore, in this embodiment, as described with reference to FIGS. 3 to 13, instead of forming a BOX film, an ONO film C2 is formed between the silicon layer S1 and the semiconductor substrate Sb in the SOI region 1A. The BOX film C3, which is the same layer as the ONO film C2, is used as the charge holding film of the MONOS memory Qb in the bulk silicon region 1B. Therefore, the step of forming the BOX film, the step of removing the BOX film in the bulk silicon region 1B, and the step of removing the ONO film in the SOI region 1A can be omitted. For this reason, the manufacturing process of a semiconductor device can be simplified and the manufacturing cost of a semiconductor device can be reduced.

  Further, since the nonvolatile memory and the transistor provided in the SOI region can be provided over one substrate (chip), the semiconductor device can be miniaturized and the performance of the semiconductor device can be improved.

(Embodiment 2)
In the present embodiment, unlike the first embodiment, a semiconductor device having a floating gate memory instead of a MONOS memory as a nonvolatile memory in a bulk silicon region will be described.

  First, the semiconductor device according to the present embodiment is shown in FIGS. 14 shows a planar layout of the semiconductor device of this embodiment, as in FIG. 1. FIG. 15 shows the semiconductor of this embodiment including a cross-sectional view taken along the line CC of FIG. Figure 2 shows a cross-sectional view of the device.

  As shown in FIG. 14, the planar layout of the semiconductor device of the present embodiment has the same structure as that of FIG. Here, a plurality of active regions AR extending in the first direction and a plurality of control gate electrodes CG2 extending in the second direction intersect, and a floating gate memory is formed at each intersection. In other words, the semiconductor device of the present embodiment has a plurality of floating gate memories arranged in a matrix in a plan view. Here, the plurality of active regions AR function as bit lines and a plurality of control gates. The electrode CG2 functions as a word line.

  As in FIG. 2, FIG. 15 shows the SOI region 1A on the left side of the drawing and the bulk silicon region 1B on the right side of the drawing. A bulk silicon region 1B in FIG. 15 is a cross-sectional view taken along the line CC in FIG. In the SOI region 1A, the structure of the MOSFET Qa formed on the silicon layer S1 is the same as that of the first embodiment, but the ONO film C2 is not formed below the silicon layer S1, and is a single silicon oxide film. A BOX film (insulating film) Ox3 is formed. Note that the BOX film Ox3 may have a structure in which a plurality of silicon oxide films are stacked, but here, it is assumed that it is a single layer film.

  Further, as shown in FIG. 15, a plurality of floating gate memories Qc are formed side by side in the first direction in the bulk silicon region 1B. On the semiconductor substrate Sb in the bulk silicon region 1B of the semiconductor device of the present embodiment, a floating gate memory Qc is formed instead of the MONOS memory.

  In the bulk silicon region 1B, the gate electrode CG1 is formed on the semiconductor substrate Sb via the ONO film C3 in FIG. 2, whereas in FIG. 15, the insulating film (gate insulating film) Ox4 is formed on the semiconductor substrate Sb. The floating gate electrode FG, the ONO film C4, and the control gate electrode CG2 are sequentially formed. That is, the floating gate memory Qc shown in FIG. 15 has the insulating film Ox4, the floating gate electrode FG, the ONO film C4, and the control gate electrode CG2 formed in order on the semiconductor substrate Sb, and is formed on the upper surface of the semiconductor substrate Sb. The source / drain region includes the extension region 4 and the diffusion layer 9 formed in the epitaxial layer Ep2 on the semiconductor substrate Sb. Thus, the floating gate memory Qc forms an n-channel field effect transistor.

  The insulating film Ox4 is a silicon oxide film in the same layer as the BOX film Ox3, and the floating gate electrode FG is a semiconductor layer in the same layer as the silicon layer S1. The insulating film Ox4 is a tunnel oxide film for transmitting charges into the floating gate electrode FG. The ONO film C4 is a film formed by laminating a silicon oxide film, a silicon nitride film, and a silicon oxide film in order from the upper surface side of the semiconductor substrate Sb, as in the ONO film C2 shown in FIG. It is shown as a film. The control gate electrode CG2 is a polysilicon film in the same layer as the gate electrode G1. As described above, instead of the ONO film C3 and the gate electrode CG1 shown in FIG. 2, the insulating film Ox4, the floating gate electrode FG, the ONO film C4, and the control gate electrode CG2 shown in FIG. 15 are formed on the semiconductor substrate Sb. In that respect, the structure of the floating gate memory Qc of the present embodiment is different from that of the MONOS memory Qb shown in FIG.

  Since the insulating film Ox4 is a silicon oxide film in the same layer as the BOX film Ox3, each film is made of a silicon oxide film and has the same film thickness. Since the floating gate electrode FG is a semiconductor layer that is the same layer as the silicon layer S1, each of the layers is formed of, for example, single crystal silicon and has the same film thickness. However, since different silicon oxide films are formed on the upper surfaces of the floating gate electrode FG and the silicon layer S1 in different processes using, for example, a thermal oxidation method, the respective films of the floating gate electrode FG and the silicon layer S1. The thickness can be different.

  The floating gate memory Qc writes and erases information by putting electrons into and out of the floating gate electrode FG below the control gate electrode CG2, thereby allowing a current to flow between the source and drain regions of the transistor. It is a nonvolatile memory element that changes the threshold voltage.

  The lower surface and the upper surface of the floating gate electrode FG are covered with the insulating film Ox4 and the ONO film C4, respectively, the side surfaces on both sides in the first direction are covered with the sidewall SW, and the side surfaces on both sides in the second direction are element isolation. Covered by a region (not shown). That is, the floating gate electrode FG is not connected to other contact plugs, wirings, or semiconductor regions, and is in an electrically independent floating state. Therefore, the floating gate electrode FG can hold charges therein.

  That is, the insulating film Ox4 and the ONO film C4 have a role of insulating the floating gate electrode FG from the semiconductor substrate Sb and the control gate electrode CG2. The ONO film C4 has a role of improving the breakdown voltage of the control gate electrode CG2.

  As in the first embodiment, the semiconductor device according to the present embodiment includes an SOI region 1A and a bulk silicon region 1B on one semiconductor substrate Sb, a transistor on the SOI substrate that constitutes a logic circuit, etc. It is possible to mount the volatile memory on the same substrate. As described above, the BOX film Ox3 in the SOI region 1A and the insulating film Ox4 in the bulk silicon region 1B are formed of the same layer and the silicon layer in the SOI region 1A in order to mount different types of elements together. A major feature of the semiconductor device of the present embodiment is that S1 and the floating gate electrode FG in the bulk silicon region 1B are formed of the same layer.

  Next, the manufacturing process of the MOSFET and the floating gate memory according to the present embodiment will be described with reference to FIGS. FIGS. 16 to 18, 20, and 22 to 24 are semiconductor devices according to the present embodiment, each having an n-channel MOSFET and a floating gate memory on an SOI region and a bulk silicon semiconductor substrate. It is sectional drawing in the manufacturing process of a semiconductor device. 19, FIG. 21, and FIG. 25 are cross-sectional views in directions orthogonal to the cross sections of FIG. 18, FIG. 20, and FIG.

  First, as shown in FIG. 16, an SOI substrate in which a BOX film Ox3 and a silicon layer S1 are sequentially stacked on a semiconductor substrate Sb is formed. In this case, first, two silicon wafers (semiconductor substrates) are prepared, a silicon oxide film is formed on the upper surfaces of both silicon wafers, and then the upper surfaces of the two silicon wafers, that is, the silicon oxide film is formed. A single substrate is formed by bonding the surfaces on which the surfaces are formed. The silicon oxide film formed on the upper surface of each silicon wafer is formed using, for example, a thermal oxidation method. Note that a two-layer silicon oxide film is formed between the bonded silicon wafers in contact with each other. In the following description, it is assumed that the two-layer silicon oxide film is a one-layer BOX film Ox3. .

  In FIG. 16, different regions of one substrate are shown separately in the left and right views. Here, the cross-sectional view on the right side of FIG. 16 is a cross-sectional view at a position corresponding to the cross section taken along the line CC of FIG.

  Here, one of the silicon wafers is a semiconductor substrate Sb as a supporting substrate, and the other silicon wafer formed on the semiconductor substrate Sb via the BOX film Ox3 is peeled off using the Smart Cut method. Layer S1 is formed. The film thickness of the silicon layer S1 is, for example, 10 to 15 nm, and the film thickness of the BOX film Ox3 is, for example, 10 to 20 nm.

  Next, as shown in FIG. 17, a plurality of element isolation regions IR are formed on the upper surface of the semiconductor substrate Sb in the same manner as described with reference to FIGS. Thereby, the silicon layer S1 is divided into a plurality of layers. Here, the upper surface height of the element isolation region IR is formed in a region higher than the upper surface of the silicon layer S1.

  Subsequently, an ONO film C4 is formed on the silicon layer S1. The ONO film C4 includes a silicon oxide film, a silicon nitride film, and a silicon oxide film that are sequentially formed on the silicon layer S1. Each insulating film constituting the ONO film C4 can be formed by, for example, a CVD method. It is conceivable that the ONO film C4 is also formed on the element isolation region IR, but here, for the sake of clarity, the illustration is omitted and only the ONO film C4 covering the upper surface of the silicon layer S1 is shown. ing.

  Next, as shown in FIG. 18, a part of the ONO film C4 is removed by using a photolithography technique and an etching method to expose the upper surface of the silicon layer S1, and then exposed by using a thermal oxidation method or the like. A silicon oxide film Ox5 is formed on the upper surface of the silicon layer S1.

  FIG. 19 is a cross-sectional view at this time, and is a cross-sectional view in a direction orthogonal to the direction along the cross-section of FIG. FIG. 19 is a cross-sectional view of a position corresponding to a cross section taken along line DD of FIG. As shown in FIG. 19, a BOX film Ox3 and a silicon layer S1 are formed on a semiconductor substrate Sb having a plurality of element isolation regions IR formed on the upper surface so as to be sandwiched between the element isolation regions IR. That is, the plurality of silicon layers S1 are separated by the element isolation region IR and are insulated from each other. The upper surface of the silicon layer S1 is covered with an ONO film C4.

  Next, as shown in FIG. 20, a gate electrode G1 is formed on the silicon layer S1 via the gate insulating film 2 in the same manner as described with reference to FIGS. The gate insulating film 2 is a film formed by processing the silicon oxide film Ox5, and has a film thickness of, for example, 2 or 3 nm. In addition, by this step, the control gate electrode CG2 made of a conductor film in the same layer as the gate electrode G1 is formed on the ONO film C4. At this time, it is considered that the ONO film C4 next to the control gate electrode CG2 is partially removed, but it is not completely removed.

  Further, FIG. 21 shows a cross-sectional view in a direction orthogonal to the cross section of FIG. 20 at this time. FIG. 21 is a cross-sectional view of a position corresponding to the cross section along the line DD of FIG. As shown in FIG. 21, the control gate electrode CG2 is formed on the semiconductor substrate Sb, and the upper surface of each ONO film C4 and the upper surface of each element isolation region IR are covered with the control gate electrode CG2 extending in the second direction. .

  Next, as shown in FIG. 22, a region including the gate electrode G1 formed on the silicon layer S1 via the gate insulating film 2 is covered with a photoresist film P1. The photoresist film P1 exposes the ONO film C4 and the control gate electrode CG2. Thereafter, the ONO film C4, the silicon layer S1, and the BOX film Ox3 exposed from the photoresist film P1 and the control gate electrode CG2 are removed by using, for example, a dry etching method, and the upper surface of the semiconductor substrate Sb is exposed. This leaves the ONO film C4, the floating gate electrode FG made of the silicon layer S1, and the insulating film Ox4 made of the BOX film Ox3 only under the control gate electrode CG2 in the bulk silicon region 1B.

  Hereinafter, a region where the upper surface of the semiconductor substrate Sb is exposed from the BOX film Ox3 and the silicon layer S1 is referred to as a bulk silicon region 1B. A region where the gate electrode G1 is formed via the film 2 is referred to as an SOI region 1A.

  In this way, in the bulk silicon region 1B, a plurality of laminated film patterns including the insulating film Ox4, the floating gate electrode FG, the ONO film C4, and the control gate electrode CG2 formed in order on the semiconductor substrate Sb are formed. As shown in the above process, the BOX film Ox3 in the SOI region 1A and the insulating film Ox4 in the bulk silicon region 1B are the same insulating films made of the same film. Further, the silicon layer S1 in the SOI region 1A and the floating gate electrode FG in the bulk silicon region 1B are semiconductor layers of the same layer made of the same film.

  Next, as shown in FIG. 23, after removing the photoresist film P <b> 1, the same process as described with reference to FIGS. 10 and 11 is performed. That is, the extension region 5 is formed in the silicon layer S1 of the SOI region 1A, the sidewall SW is formed on the sidewall of the gate electrode G1, and the diffusion layer 10 made of the epitaxial layer Ep1 is formed on the silicon layer S1 exposed from the sidewall SW. Form. Thereby, the MOSFET Qa having the gate electrode G1, the extension region 5 and the diffusion layer 10 is formed.

  Further, the extension region 4 is formed on the upper surface of the semiconductor substrate Sb in the bulk silicon region 1B, the sidewall SW is formed on the sidewalls of the control gate electrode CG2 and the floating gate electrode FG, and the semiconductor substrate Sb exposed from the sidewall SW is formed. A diffusion layer 9 made of the epitaxial layer Ep2 is formed. Thereby, the floating gate memory Qc having the control gate electrode CG2, the floating gate electrode FG, the extension region 4 and the diffusion layer 9 is formed.

  Subsequent steps are the same as those described with reference to FIGS. 12 and 13, whereby the semiconductor device shown in FIG. 24 is completed. That is, after the silicide layer 15 is formed on the upper surfaces of the diffusion layers 9 and 10, the gate electrode G1, and the control gate electrode CG2, which are semiconductor layers exposed from the sidewall SW, the insulating film 16 is formed on the entire surface of the semiconductor substrate Sb. Then, the contact plug Cp is formed after covering with the interlayer insulating film 17. Thereafter, an insulating film 19 and an interlayer insulating film 20 are formed on the interlayer insulating film 17, and a wiring 21 is formed in a trench that penetrates the insulating film 19 and the interlayer insulating film 20 and exposes the upper surface of the contact plug Cp.

  In the completed semiconductor device, a cross-sectional view taken along line DD in FIG. 14 has a structure as shown in FIG. The structure shown in FIG. 25 is similar to the structure shown in FIG. 21 in the second direction, which is formed by floating gate electrodes FG that are intermittently arranged in the cross-sectional direction, and an ONO film C4 formed thereon. And a control gate electrode CG2 extending continuously.

  As described above, the control gate electrode CG2 functions as a word line of the floating gate memory Qc, and the charges retained as information in the floating gate memory Qc are accumulated in the floating gate electrode FG whose surface is surrounded by the insulating film.

  Below, the effect in the manufacturing method of the semiconductor device of this Embodiment is demonstrated.

  In a semiconductor substrate having an SOI region and a bulk silicon region, when a MOSFET is formed in the SOI region and a floating gate memory is formed in the bulk silicon region, the SOI region is formed on a silicon layer formed on the semiconductor substrate via a BOX oxide film. In the bulk silicon region, it is conceivable to form a memory element on a semiconductor substrate not covered with the BOX film. In this case, after an SOI substrate having a BOX film and a silicon layer is formed on the semiconductor substrate, the BOX film and the silicon layer in the bulk silicon region are removed, and then an insulating film (gate insulation) is formed on the semiconductor substrate in the bulk silicon region. It is conceivable to form a film, a tunnel oxide film) and a floating gate electrode in this order.

  When the above process is used, a process of forming an insulating film (gate insulating film, tunnel oxide film) and a film constituting the floating gate electrode on the semiconductor substrate in the bulk silicon region is required. That is, in addition to the step of forming the BOX film constituting the SOI substrate and the silicon layer thereon, a film forming step for forming the floating gate electrode and the gate insulating film therebelow is required.

  In addition to removing the BOX film and silicon layer formed in the bulk silicon region and exposing the upper surface of the semiconductor substrate, patterning for forming a gate insulating film and a floating gate electrode is necessary. The process increases. For this reason, when the gate insulating film and the floating gate electrode are formed using a film different from the BOX film and the silicon layer, the film forming process and the processing process increase, so the manufacturing process of the semiconductor device becomes complicated and the manufacturing cost is reduced. There are increasing problems. As described above, the problem that the film forming process and the processing process increase is that the bulk silicon region is not formed, and the MOSFET and the floating gate memory are formed on the SOI substrate in which the upper surface of the semiconductor substrate is entirely covered with the BOX film and the silicon layer. This also occurs when forming.

  Therefore, in the present embodiment, as described with reference to FIGS. 16 to 25, the insulating film (gate insulating film) Ox4 of the floating gate memory Qc formed in the bulk silicon region 1B is formed in the BOX formed in the SOI region 1A. It is formed of the same layer as the film Ox3. Further, the floating gate electrode FG of the floating gate memory Qc formed in the bulk silicon region 1B is formed of a film in the same layer as the silicon layer S1 formed in the SOI region 1A. That is, the silicon layer S1 and the floating gate electrode FG are formed from the same film, and the BOX film Ox3 and the insulating film Ox4 are formed from the same film.

  Thereby, it is possible to omit the film forming process for forming the insulating film Ox4 and the floating gate electrode FG. Further, by performing the step of removing the BOX film Ox3 and the silicon layer S1 (see FIG. 20) covering the bulk silicon region 1B described with reference to FIG. 22, the pattern of the insulating film Ox4 and the floating gate electrode FG is simultaneously formed. It becomes possible to do. That is, in addition to the step of exposing the upper surface of the semiconductor substrate Sb in the bulk silicon region 1B, it is not necessary to further provide a step of processing the insulating film Ox4 and the floating gate electrode FG. For this reason, the manufacturing process of a semiconductor device can be simplified and the manufacturing cost of a semiconductor device can be reduced.

  Further, since the nonvolatile memory and the transistor provided in the SOI region can be provided over one substrate (chip), the semiconductor device can be miniaturized and the performance of the semiconductor device can be improved.

  Although the invention made by the present inventors has been specifically described based on the embodiment, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the first and second embodiments, the case where the n-channel MOSFET is formed on the semiconductor substrate has been described. However, the semiconductor element may be a p-channel MOSFET, or a MIS (Metal Insulator Semiconductor) type. It may be an FET. Similarly, the MONOS memory and the floating gate memory may constitute a p-channel field effect transistor.

1A SOI region 1B Bulk silicon region 2 Gate insulating film 4 Extension region 5 Extension region 9 Diffusion layer 10 Diffusion layer 15 Silicide layer 16 Insulating film 17 Interlayer insulating film 19 Insulating film 20 Interlayer insulating film 21 Wiring AR Active regions C1 to C4 ONO film CG1 Gate electrode CG2 Control gate electrode Cp Contact plug Ep1 Epitaxial layer Ep2 Epitaxial layer FG Floating gate electrode G1 Gate electrode IR Element isolation region Ox1 Silicon oxide film Ox2 Silicon oxide film Ox3 BOX film Ox4 Insulating film (gate insulating film, tunnel oxide film)
Ox5 silicon oxide film P1 photoresist film Qa MOSFET
Qb MONOS memory Qc Floating gate memory S1 Silicon layer SN Silicon nitride film SW Side wall Sb Semiconductor substrate

Claims (14)

A semiconductor substrate having a first region and a second region on a main surface;
A first insulating film formed on the semiconductor substrate in the first region;
A second insulating film formed on the first insulating film;
A semiconductor layer formed on the second insulating film;
A field effect transistor formed on the semiconductor layer;
A non-volatile memory formed on the semiconductor substrate in the second region;
Have
The nonvolatile memory is
A third insulating film formed on the semiconductor substrate in the second region, the third insulating film being the same layer as the first insulating film;
A charge retention film that is formed on the third insulating film and is the same layer as the second insulating film;
A semiconductor device having a gate insulating film including: A fourth insulating film is formed between the second insulating film and the semiconductor layer,
The semiconductor device according to claim 1, wherein a fifth insulating film that is a film in the same layer as the fourth insulating film is formed on the charge retention film. The first insulating film and the third insulating film have the same film thickness,
The semiconductor device according to claim 1, wherein the second insulating film and the charge retention film have the same film thickness. The field effect transistor includes a first gate insulating film formed on the semiconductor layer,
A first source / drain region formed on the semiconductor layer;
The nonvolatile memory includes a second gate electrode formed on the charge retention film;
The semiconductor device according to claim 1, further comprising a second source / drain region formed on an upper portion of the semiconductor substrate. The first insulating film, the fourth insulating film, the third insulating film, and the fifth insulating film are silicon oxide films;
The semiconductor device according to claim 2, wherein the second insulating film and the charge retention film are silicon nitride films. A semiconductor substrate having a first region and a second region on a main surface;
A first insulating film formed on the semiconductor substrate in the first region;
A first semiconductor layer formed on the first insulating film;
A field effect transistor formed on the first semiconductor layer;
A non-volatile memory formed on the semiconductor substrate in the second region;
Have
The nonvolatile memory is
A first gate insulating film formed on the semiconductor substrate in the second region, the first gate insulating film being the same layer as the first insulating film;
A second semiconductor layer which is formed on the first gate insulating film and is in the same layer as the semiconductor layer and is in an electrically floating state;
A first gate electrode formed on the second semiconductor layer via a second insulating film;
A semiconductor device. The first insulating film and the first gate insulating film have the same film thickness,
The semiconductor device according to claim 6, wherein the first semiconductor layer and the second semiconductor layer have the same film thickness.   The semiconductor device according to claim 6, wherein the second insulating film has a stacked structure in which a first silicon oxide film, a silicon nitride film, and a second silicon oxide film are sequentially formed from the semiconductor substrate side. The field effect transistor includes a second gate electrode formed on the semiconductor layer,
A first source / drain region formed on the first semiconductor layer;
The semiconductor device according to claim 6, wherein the nonvolatile memory includes a second source / drain region formed on an upper portion of the semiconductor substrate. (A) forming a first insulating film, a second insulating film, a third insulating film, and a semiconductor layer in order on a semiconductor substrate having a first region and a second region on a main surface;
(B) removing the semiconductor layer in the second region;
(C) After the step (b), forming a fourth insulating film on the semiconductor layer;
(D) forming a conductor film on the fourth insulating film in the first region and on the third insulating film in the second region;
(E) processing the conductor film and the fourth insulating film to form a first gate electrode made of the conductor film and a gate insulating film made of the fourth insulating film in the first region;
Processing the conductor film, the third insulating film, the second insulating film, and the first insulating film to form a second gate electrode made of the conductor film and a charge holding film made of the second insulating film Forming in the second region;
(F) forming a field effect transistor including the first gate electrode in the first region;
Forming a nonvolatile memory including the charge retention film and the second gate electrode in the second region;
A method for manufacturing a semiconductor device, comprising: The first insulating film and the third insulating film are silicon oxide films,
The method of manufacturing a semiconductor device according to claim 10, wherein the second insulating film and the charge retention film are silicon nitride films. (A) forming a first insulating film, a first semiconductor layer, and a second insulating film in order on a semiconductor substrate having a first region and a second region on a main surface;
(B) forming a third insulating film on an upper surface of the first semiconductor layer in the first region after removing the second insulating film in the first region;
(C) after the step (b), forming a first gate insulating film on the first semiconductor layer in the first region;
Forming a second gate electrode on the second insulating film in the second region;
(D) removing the second insulating film, the first semiconductor layer, and the first insulating film exposed from the second gate electrode;
Exposing the upper surface of the semiconductor substrate, forming a second semiconductor layer made of the first semiconductor layer, and forming a fourth insulating film made of the first insulating film;
(E) forming a field effect transistor including a first gate electrode on the semiconductor layer in the first region;
Forming a nonvolatile memory including the second semiconductor layer and the second gate electrode on the semiconductor substrate in the second region;
A method for manufacturing a semiconductor device, comprising:   13. The method of manufacturing a semiconductor device according to claim 12, wherein the second insulating film has a stacked structure in which a first silicon oxide film, a silicon nitride film, and a second silicon oxide film are formed in order from the semiconductor substrate side.   The method of manufacturing a semiconductor device according to claim 12, wherein the second semiconductor layer is in an electrically floating state.

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