WO2011036779A1

WO2011036779A1 - Volatile semiconductor memory device

Info

Publication number: WO2011036779A1
Application number: PCT/JP2009/066701
Authority: WO
Inventors: 潤藤木; 敏典沼田; 悠介東; 究佐久間; 直樹安田; 浩一村岡
Original assignee: 株式会社東芝
Priority date: 2009-09-25
Filing date: 2009-09-25
Publication date: 2011-03-31

Abstract

The disclosed volatile semiconductor memory device is provided with a semiconductor substrate, an insulating layer provided on parts of the aforementioned semiconductor substrate, a semiconductor layer provided on the aforementioned insulating layer, and a first through a third memory cell. Each of the aforementioned first through third memory cells is equipped with: a MOSFET that is provided to the aforementioned semiconductor substrate and that has a source, a drain, and a first gate; and a thyristor that is provided to the aforementioned semiconductor layer and that has an anode, a cathode, and a second gate. The aforementioned drain and the aforementioned cathode are electrically connected. The sources of the aforementioned first and second memory cells are electrically connected, and the anodes of the aforementioned first and third memory cells are electrically connected.

Description

Volatile semiconductor memory device

The present invention relates to a volatile semiconductor memory device using a thyristor as a memory element.

Since the negative resistance element has a high resistance state and a low resistance state, it can be used as a storage element for storing data “0” and data “0”. A thyristor is known as a negative resistance element. A memory device in which a thyristor and an access transistor are connected in series using the turn-off / turn-on characteristics of the thyristor has been proposed (for example, Patent Documents 1 and 2). This memory device mainly applied as SRAM is composed of high-speed and area-saving memory cells. This memory device is called Thyristor-RAM (Random Access Memory), and is hereinafter abbreviated as TRAM.

The miniaturization of the unit cell is a problem for the problem of increasing the capacity of the TRAM. As seen in Patent Document 3, when a contact is formed for each unit cell, or when the cell is separated by element isolation, the area of the unit cell is reduced due to the wiring area and the area of the element isolation region. It becomes difficult.

US Pat. No. 6,462,359 US Pat. No. 6,888,176 JP 2009-135187 A

The present invention provides a volatile semiconductor memory device capable of further reducing the area of the memory cell array.

A volatile semiconductor memory device according to one embodiment of the present invention includes a semiconductor substrate, an insulating layer partially provided over the semiconductor substrate, a semiconductor layer provided over the insulating layer, and first to third elements. Memory cells. Each of the first to third memory cells is provided on the semiconductor substrate, has a MOSFET having a source, a drain, and a first gate, and is provided on the semiconductor layer, and has an anode, a cathode, and a second gate. A thyristor, and the drain is electrically connected to the cathode. The first and second memory cells have their sources electrically connected, and the first and third memory cells have their anodes electrically connected.

A volatile semiconductor memory device according to one embodiment of the present invention includes a MOSFET having a source, a drain, a first gate, and a substrate gate, and a thyristor having an anode, a cathode, and a second gate, and the drain Comprises first to third memory cells electrically connected to the cathode. The sources of the first and second memory cells are electrically connected, the anodes of the first and third memory cells are electrically connected, and the first to third memory cells are The substrate gates are electrically connected.

According to the present invention, it is possible to provide a volatile semiconductor memory device that can further reduce the area of the memory cell array.

1 is a schematic diagram showing a volatile semiconductor memory device 10 according to a first embodiment. FIG. 2 is an equivalent circuit diagram showing a part of the semiconductor memory device 10 extracted. The figure which shows the current-voltage characteristic in case the memory cell MC hold | maintains data. The figure which shows the current-voltage characteristic in the case of reading the data hold | maintained at the memory cell MC. The figure which shows the current-voltage characteristic in the case of writing data "1" in the memory cell MC. FIG. 6 is a diagram showing current-voltage characteristics when data “0” is written to a memory cell MC. 1 is a layout diagram showing a part of a semiconductor memory device 10 according to a first embodiment. FIG. 8 is a cross-sectional view of the semiconductor memory device 10 taken along line II ′ shown in FIG. FIG. 8 is a cross-sectional view of the semiconductor memory device 10 taken along the line II-II ′ shown in FIG. 7. FIG. 6 is a diagram showing a manufacturing process of the semiconductor memory device 10 according to the first embodiment. FIG. 11 shows a manufacturing process of the semiconductor memory device 10 following FIG. 10; FIG. 12 is a diagram showing a manufacturing process of the semiconductor memory device 10 following FIG. 11. FIG. 13 shows a manufacturing process of the semiconductor memory device 10 following FIG. 12. FIG. 14 is a diagram showing a manufacturing process of the semiconductor memory device 10 following FIG. 13. FIG. 15 is a diagram showing a manufacturing process of the semiconductor memory device 10 following FIG. 14. FIG. 16 is a diagram showing manufacturing steps of the semiconductor memory device 10 following FIG. 15. FIG. 17 is a diagram showing manufacturing steps of the semiconductor memory device 10 following FIG. 16. FIG. 4 is a layout diagram of a volatile semiconductor memory device 10 according to a second embodiment. FIG. 19 is a cross-sectional view of the semiconductor memory device 10 along the line II ′ shown in FIG. Sectional drawing which shows the structure of the volatile semiconductor memory device 10 which concerns on 3rd Embodiment. The energy band figure explaining operation | movement of the thyristor 12. FIG. The energy band figure explaining operation | movement of the thyristor 12. FIG. The energy band figure explaining operation | movement of the thyristor 12. FIG. Sectional drawing which shows the structure of the volatile semiconductor memory device 10 which concerns on 4th Embodiment. Sectional drawing which shows the other structural example of the thyristor 12. FIG.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
Note that the drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio coefficient of the size between the parts, and the like are not necessarily the same as actual ones. Further, even when the same part is represented, the dimensions and ratio coefficient may be represented differently depending on the drawing.
Moreover, in the following description, the same code | symbol is attached | subjected to the element similar to what was mentioned above regarding the previous figure, and duplication description is abbreviate | omitted suitably.

[First Embodiment]
[1. Circuit configuration]
FIG. 1 is a schematic diagram showing a configuration of a volatile semiconductor memory device (TRAM) 10 according to the first embodiment of the present invention. FIG. 2 is an equivalent circuit diagram showing a part of the volatile semiconductor memory device 10 extracted.

The semiconductor memory device 10 includes a plurality of memory cells MC arranged in a matrix. Further, the semiconductor memory device 10 has (n + 1) bit lines BL0 to BLn extending in the X direction, (m + 1) word lines WL1_0 to WL1_m extending in the Y direction intersecting the X direction, and (m + 1) extending in the Y direction. This includes word lines WL2_0 to WL2_m and a plurality of anode lines AL. One bit line BL, two word lines WL1, WL2, and one anode line AL are connected to one memory cell MC.

As shown in FIG. 2, one memory cell MC includes one access transistor 11 and one negative resistance element 12 connected in series. The access transistor 11 is composed of, for example, an N channel MOSFET (Metal | Oxide | Semiconductor | Field | Effect | Transistor). The negative resistance element 12 is composed of a thyristor.

The memory cell MC will be described in detail. The access transistor 11 has a source terminal S, a drain terminal D, a gate terminal G1, and a substrate gate terminal SG as terminals for connecting to an external circuit. The thyristor 12 has an anode terminal A, a cathode terminal C, and a gate terminal G2 as terminals for connecting to an external circuit. The source terminal S is electrically connected to the bit line BL via the bit line contact BC, the drain terminal D is electrically connected to the cathode terminal C, and the anode terminal A is electrically connected to the anode line AL via the anode contact AC. The gate terminal G1 is electrically connected to the word line WL1, and the gate terminal G2 is electrically connected to the word line WL2.

Further, assuming that the memory cells MC1 to MC3 are arranged in order along the X direction, the memory cells MC1 and MC2 are electrically connected to each other and share the bit line contact BC. The memory cells MC2 and MC3 are electrically connected to each other and share an anode contact AC. The memory cell groups for one row arranged in the X direction are formed in the same element region AA, and the substrate gate terminals SG of these memory cell groups are electrically connected in common by the source line SL. Further, the memory cell group commonly connected to the source line SL is electrically connected to the same bit line BL via the bit line contact BC. Other than the above connection, the terminals are not connected to each other.

One of the features of the semiconductor memory device 10 of the present embodiment is that adjacent memory cells are connected to each other, and the adjacent memory cells share a bit line contact BC or an anode contact AC. In this manner, a memory cell array with a small area can be realized by reducing the number of wirings.

Next, data write, hold, and read operations of the semiconductor memory device 10 will be described.

FIG. 3 is a diagram schematically showing current-voltage characteristics when the memory cell MC holds data. The solid line represents the current-voltage characteristic of the thyristor 12, and the broken line represents the current-voltage characteristic of the access transistor 11. Data retention is performed by setting the anode line AL to a high potential with respect to the bit line BL and applying no voltage to the word lines WL1 and WL2. The intersection of the current-voltage characteristics of the thyristor 12 and the access transistor 11 is the holding state. That is, the intersection of the low resistance characteristic of the thyristor 12 and the current-voltage characteristic of the access transistor 11 is “1”, and the intersection of the high resistance characteristic of the thyristor 12 and the current-voltage characteristic of the access transistor 11 is “0”. is there. Each state is maintained while the potential is applied. Note that the intersection between the low resistance characteristic of the thyristor 12 and the current voltage characteristic of the access transistor 11 is set to the “0” state, and the intersection of the high resistance characteristic of the thyristor 12 and the current voltage characteristic of the access transistor 11 is set to the “1” state. good.

FIG. 4 is a diagram schematically showing current-voltage characteristics when data held in the memory cell MC is read. Reading is performed by setting the anode line AL to a high potential with respect to the bit line BL, further setting the word line WL1 to a high potential, and applying no voltage to WL2. An intersection of the current-voltage characteristics of the thyristor 12 and the access transistor 11 is realized at the time of reading. That is, the intersection between the low resistance characteristic of the thyristor 12 and the current voltage characteristic of the access transistor 11 is “1” reading, and the intersection of the high resistance characteristic of the thyristor 12 and the current voltage characteristic of the access transistor 11 is “0”. Reading of the state.

FIG. 5 is a diagram schematically showing current-voltage characteristics when data “1” is written to the memory cell MC. While the write voltage is applied to the word line WL2 of the thyristor 12, the current-voltage characteristics of the thyristor 12 are as shown in FIG. A write voltage is applied to the word lines WL1 and WL2, the anode line AL is set to a high potential with respect to the bit line BL, and the thyristor 12 is set in a low resistance state to write data “1”.

FIG. 6 is a diagram schematically showing current-voltage characteristics when data “0” is written to the memory cell MC. While the write voltage is applied to the word line WL2 of the thyristor 12, the current-voltage characteristics of the thyristor 12 are as shown in FIG. A write voltage is applied to the word lines WL1 and WL2, the bit line BL is set to a high potential with respect to the anode line AL, and the thyristor 12 is set in a high resistance state to write data “0”.

As described above, data holding, reading, and writing are performed on the memory cell MC. The adjacent memory cells MC1 and MC2 share the bit line contact BC, and the adjacent memory cells MC2 and MC3 share the anode contact AC, but each has the word lines WL1 and WL2 individually, so that the memory The cells MC1 to MC3 can be controlled independently.

[2. Device structure]
Next, the structure of the memory cell MC for realizing the circuit diagram of FIG. 1 will be described. Note that when the semiconductor conductivity type is specified, the conductivity type 1 and the conductivity type 2 are used. Conductive type 1 and conductive type 2 have opposite polarities and are n-type or p-type. In the following description, it is assumed that the conductivity type 1 is n-type and the conductivity type 2 is p-type. However, the present embodiment is not limited to the designation of the above conductivity type. That is, the present embodiment can be applied by setting the conductivity type 1 to p-type and the conductivity type 2 to n-type. In this case, the polarity of all voltages for driving the semiconductor memory device 10 is reversed.

In the following description, not only silicon but also various materials such as germanium, silicon germanium (SiGe), indium phosphide (InP), polysilicon, silicon carbide (SiC) are applicable as semiconductor materials.

FIG. 7 is a layout diagram showing a part of the semiconductor memory device 10 according to the first embodiment. FIG. 8 is a cross-sectional view of the semiconductor memory device 10 taken along the line II ′ shown in FIG. FIG. 9 is a cross-sectional view of the semiconductor memory device 10 taken along the line II-II ′ shown in FIG.

The semiconductor substrate (or well) 20 includes an element isolation insulating layer 21 in the surface region, and a region where the element isolation insulating layer 21 is not formed becomes an element region (active region) AA in which an element is formed. The element isolation insulating layer 21 is configured by, for example, STI (Shallow Trench Isolation). For example, silicon oxide (SiO ₂ ) is used as the STI.

A plurality of element regions AA exist in the Y direction via the element isolation insulating layer 21, and each element region AA extends in the X direction. Adjacent element regions AA are not electrically connected because the element isolation insulating layer 21 exists.

The bit line BL is disposed above the element area AA and extends in the X direction so as to be parallel to the element area AA. The bit line BL is connected to the bit line contact BC. The word lines WL1 and WL2 and the anode line AL extend in the Y direction. In FIG. 7, illustration of the anode line AL is omitted, and only the anode contact AC is illustrated, but actually, the anode line AL wider than the anode contact AC is on the anode contact AC in the Y direction. It is provided so as to extend.

Each element region AA is provided with a plurality of memory cells MC to which adjacent ones are connected. The plurality of memory cells MC provided in the same element region AA are arranged in the X direction so that the word lines WL1 and the word lines WL2 face each other alternately.

Hereinafter, a specific structure of the memory cell MC will be described with reference to FIG. The memory cell MC includes an access transistor 11 and a thyristor 12. The semiconductor substrate (or well) 20 is a p-type semiconductor substrate (p-sub).

The access transistor 11 includes a source region S and a drain region D that are provided separately in the semiconductor substrate 20, and a gate electrode that is provided on the semiconductor substrate 20 between the source region S and the drain region D via a gate insulating film. G1. The source region S and the drain region D are n ⁺ type semiconductor regions. Side walls 22 are provided on both side surfaces of the gate electrode G1.

The first memory cell and the second memory cell adjacent to one of the first memory cells are arranged so that the access transistors 11 included in the first memory cell face each other, and the source region S of the access transistor 11 is Sharing. A bit line contact BC is provided on the source region S shared by the access transistors 11 of the first memory cell and the second memory cell. That is, the first memory cell and the second memory cell also share the bit line contact BC. A bit line BL extending in the X direction is provided on the bit line contact BC. A plurality of memory cells formed in the same element area AA are connected to each other by a bit line BL.

The thyristor 12 includes a semiconductor layer in which a cathode region C made of an n ⁺ type semiconductor layer, a p ⁻ type semiconductor layer 26, an n ⁻ type semiconductor layer 27, and an anode region A made of a p ⁺ type semiconductor layer are sequentially joined. . Note that the minus or plus notation added to the conductivity type means the concentration of impurities, minus indicates a low concentration, and plus indicates a high concentration.

The cathode region C is provided on the drain region D of the access transistor 11. The p ⁻ type semiconductor layer 26, the n ⁻ type semiconductor layer 27, and the anode region A are provided on an insulating layer 28 provided on the semiconductor substrate 20. That is, the p ⁻ type semiconductor layer 26, the n ⁻ type semiconductor layer 27, and the semiconductor layer including the anode region A are made of partial SOI (Silicon On Insulator) partially formed on the semiconductor substrate 20. On the p ⁻ type semiconductor layer 26, a gate electrode G2 is provided via a gate insulating film. Side walls 30 are provided on the side surfaces of the gate electrode G2.

The thyristor 12 is electrically insulated from the semiconductor substrate 20 via the insulating layer 28 except that the cathode region C is connected to the drain region D. For example, when a thyristor is directly formed on a semiconductor substrate, adjacent diffusion thyristors cannot be controlled independently because part of diffusion regions constituting the thyristor are electrically connected to each other. However, in this embodiment, since the thyristor 12 is formed in the partial SOI, adjacent thyristors can be controlled independently.

The first memory cell and the third memory cell adjacent to the first memory cell in the opposite direction to the second memory cell are arranged so that the thyristor 12 included in the first memory cell faces each other, and The anode region A of the thyristor 12 is shared. An anode contact AC is provided on the anode region A shared by the thyristors 12 of the first memory cell and the third memory cell. That is, the first memory cell and the third memory cell also share the anode contact AC. An anode line AL extending in the Y direction is provided on the anode contact AC.

Also, adjacent memory cells have a cross-sectional structure that is line symmetric with respect to the boundary line of these memory cells.

The element region AA is connected to, for example, a source line SL (not shown) via a contact, and is set to a ground voltage, for example, by the source line SL. Accordingly, as in the circuit diagram of FIG. 1, the access transistors 11 included in the plurality of memory cells MC formed in the same element region AA have the substrate gate terminals SG corresponding to the element regions AA connected to the source line SL. And the substrate gate terminal SG is grounded via the source line SL.

For example, when the access transistor 11 is provided in the SOI where the thyristor 12 is formed, the substrate gate terminal SG of the access transistor 11 cannot be commonly connected to the source line SL. That is, the circuit configuration of FIG. 2 cannot be realized. On the other hand, in this embodiment, since the voltage of the substrate gate terminal SG of the access transistor 11 can be controlled, for example, the threshold voltage of the access transistor 11 can be adjusted. Thereby, the operating characteristics of the access transistor 11 can be improved.

Between the semiconductor substrate 20 and the bit line BL, an interlayer insulating layer 25 (including insulating layers 25A to 25C) is buried. Thus, the semiconductor memory device 10 according to the first embodiment is configured.

[3. Production method]
Next, an example of a method for manufacturing the semiconductor memory device 10 according to the first embodiment will be described with reference to the drawings. The cross-sectional view showing the manufacturing process is taken along the line II ′ of FIG.

First, a plurality of element isolation insulating layers 21 extending in the X direction are formed in the semiconductor substrate (p-sub) 20 to form a plurality of element regions AA in the surface region of the semiconductor substrate 20.

Subsequently, as illustrated in FIG. 10, the gate electrode G <b> 1 of the access transistor 11 is formed on the semiconductor substrate 20 (element region AA) via a gate insulating film. The gate electrode G1 functions as the word line WL1 shown in FIG. Various conductive materials such as polysilicon, TaN, Ti, Al, TaC, TiN, TiAlN, Cu, Au, and RrO can be applied to the gate electrode G1. As the gate insulating film, various insulating materials such as silicon oxide, silicon oxynitride, AlO, SiN, HfO ₂ , HfAlO, ZrO ₂ , Ta ₂ O ₅ , La ₂ O ₃ , LaAlO ₃ can be applied, and A laminated structure of these insulating films is also applicable. Subsequently, sidewalls 22 made of, for example, silicon nitride are formed on both side surfaces of the gate electrode G1.

Subsequently, as shown in FIG. 11, a SiGe layer 23 is formed as a sacrificial layer on the exposed element region AA. SiGe may be deposited or epitaxially grown. Thereby, the SiGe layer 23 is formed up to the end of the side wall 22.

Subsequently, as shown in FIG. 12, the side wall 22 is once etched to expose the element region AA in a portion excluding the gate electrode G1 and the SiGe layer 23. Subsequently, n-type impurities are ion-implanted into the element region AA to form the source region S and the drain region D of the access transistor 11. Subsequently, sidewalls 22 are formed on both side surfaces of the gate electrode G1, and sidewalls 24 are formed on both side surfaces of the SiGe layer.

Subsequently, as illustrated in FIG. 13, an insulating layer 25 </ b> A made of, for example, silicon oxide is formed on the gate electrode G <b> 1 and the source region S, and then a semiconductor layer 26 is formed on the drain region D and the SiGe layer 23. As a result, the semiconductor layer 26 has a bridge shape including an extending portion formed on the SiGe layer 23 and two supporting portions connecting the two drain regions D from both ends of the extending portion. The width of the semiconductor layer 26 is substantially the same as the width of the element region AA. The semiconductor layer 26 is formed by polysilicon deposition or silicon epitaxial growth. The semiconductor layer 26 is ion-implanted with p-type impurities, and the semiconductor layer 26 becomes a p ⁻ -type semiconductor layer.

Subsequently, as shown in FIG. 14, the SiGe layer 23 is removed by selective etching, and the removed hollow region is filled with an insulating layer 28 made of, for example, silicon oxide. Subsequently, a gate electrode G2 of the thyristor 12 is formed on the semiconductor layer 26 via a gate insulating film, and a dummy insulating layer 29 made of, for example, silicon nitride is further formed on the gate electrode G2. Various conductive materials such as polysilicon, TaN, Ti, Al, TaC, TiN, TiAlN, Cu, Au, and RrO can be applied to the gate electrode G2. As the gate insulating film, various insulating materials such as silicon oxide, silicon oxynitride, AlO, SiN, HfO ₂ , HfAlO, ZrO ₂ , Ta ₂ O ₅ , La ₂ O ₃ , LaAlO ₃ can be applied, and A laminated structure of these insulating films is also applicable.

Subsequently, the gate electrode G2 and the dummy insulating layer 29 are processed to expose only the semiconductor layer 26 on the drain region D. Subsequently, n-type impurities are ion-implanted into the exposed semiconductor layer 26 to form a cathode region C made of an n ⁺ -type semiconductor layer on the drain region D.

Subsequently, as shown in FIG. 15, the dummy insulating layer 29 is back-etched to retreat the dummy insulating layer 29 inward. Subsequently, an insulating layer 25B made of, for example, silicon oxide is deposited on the entire surface of the device, and the insulating layer 25B is planarized and the dummy insulating layer 29 is exposed by CMP (Chemical-Mechanical-Polishing).

Subsequently, as shown in FIG. 16, the dummy insulating layer 29 is selectively etched to partially expose the gate electrode G2. Subsequently, the gate electrode G2 is processed by RIE (Reactive Ion Etching), and the semiconductor layer 26 is exposed. The last remaining gate electrode G2 serves as the gate (word line WL2) of the thyristor 12. Subsequently, n-type impurities are ion-implanted into the exposed semiconductor layer 26. As a result, only the exposed portion of the semiconductor layer 26 becomes the n ⁻ type semiconductor layer 27, and the portion immediately below the gate electrode G 2 remains the p ⁻ type semiconductor layer 26.

Subsequently, as shown in FIG. 17, after forming a side wall 30 made of, for example, silicon nitride on the side surface of the gate electrode G <b> 2, p-type impurities are ion-implanted into the exposed semiconductor layer 27. Thus, only becomes p ⁺ -type semiconductor layer exposed portion of the semiconductor layer 27, the p ⁺ -type semiconductor layer becomes an anode region A. On the other hand, the semiconductor layer 27 covered with the sidewall 30 remains an n ⁻ type semiconductor layer.

Subsequently, the bit line contact BC is formed on the source region S, and the anode contact AC is formed on the anode region A. Finally, the bit line BL connected to the bit line contact BC and the anode line AL connected to the anode contact AC are formed.

By applying the manufacturing method as described above, the memory cell MC according to the first embodiment is manufactured, and a memory cell array with a reduced area in which the number of wirings is reduced is realized.

The above manufacturing method is an example, and another process is appropriately employed to realize the memory cell structure of FIG. For example, the thyristor 12 may be formed before the gate electrode G1 of the access transistor 11 is formed. Further, instead of epitaxially growing the semiconductor layer 26 on the SiGe layer 23, the semiconductor layer 26 may be formed on the insulating layer 28 after the insulating layer 28 is formed. Further, instead of processing the gate electrode G2 of the thyristor 12 using the dummy insulating layer 29, the gate electrode G2 may be processed using lithography.

As described above in detail, in the first embodiment, the access transistor 11 and the thyristor 12 constitute a memory cell. The first memory cell and the second memory cell adjacent to one of the memory cell are The source region S and the bit line contact BC provided on the source region S are shared. Further, the first memory cell and the third memory cell adjacent to the other one share the anode region A of the thyristor 12 and the anode contact AC and the anode line AL provided on the anode region A. Yes. Furthermore, the substrate gates of the access transistors 11 are commonly connected to the plurality of memory cells formed in the same element region AA. Since the plurality of memory cells individually have the word line WL1 connected to the access transistor 11 and the word line WL2 connected to the thyristor 12, they can be controlled independently.

Therefore, according to the first embodiment, the number of anode contacts AC and anode lines AL can be reduced. In addition, the number of bit line contacts BC can be reduced. As a result, the wiring area can be reduced, so that the area of the memory cell array can be reduced.

Further, since the source region S of the access transistor 11 or the anode region A of the thyristor 12 is shared by adjacent memory cells, it is not necessary to provide an element isolation region between the memory cells. As a result, the area of the memory cell array can be further reduced because there is no element isolation region.

The thyristor 12 is provided on a partial SOI formed on the semiconductor substrate 20, and the semiconductor substrate 20 is interposed via an insulating layer 28 except that the cathode region C is connected to the drain region D. Are electrically insulated. As a result, the adjacent thyristors can be controlled independently, so that the connection relationship of the present embodiment shown in FIG. 2 can be realized.

Further, since the access transistor 11 is formed on the semiconductor substrate 20, the voltage (substrate voltage) of the substrate gate terminal SG of the access transistor 11 can be controlled. Thereby, the operating characteristics of the access transistor 11 can be improved.

[Second Embodiment]
In the second embodiment, a volatile semiconductor memory device is configured such that adjacent memory cells share a bit line contact BC or an anode line AL, and the thyristor 12 has a vertical structure.

FIG. 18 is a layout diagram showing a configuration of the volatile semiconductor memory device 10 according to the second embodiment of the present invention. FIG. 19 is a cross-sectional view of the semiconductor memory device 10 along the line II ′ shown in FIG. A cross-sectional view of the semiconductor memory device 10 taken along line II-II ′ shown in FIG. 18 is the same as FIG. An equivalent circuit diagram of the volatile semiconductor memory device 10 according to the second embodiment is the same as FIG.

The bit line BL is disposed above the element area AA and extends in the X direction so as to be parallel to the element area AA. The bit line BL is connected to the bit line contact BC. The word lines WL1 and WL2 and the anode line AL extend in the Y direction. Each element region AA is provided with a plurality of memory cells MC to which adjacent ones are connected. The plurality of memory cells MC are arranged in the X direction so that the word lines WL1 and the word lines WL2 face each other alternately.

The memory cell MC includes an access transistor 11 and a thyristor 12. The semiconductor substrate (or well) 20 is a p-type semiconductor substrate (p-sub).

The thyristor 12 is provided on the cathode region C made of an n ⁺ type semiconductor layer provided in the semiconductor substrate 20, the p ⁻ type semiconductor layer 26 provided on the cathode region C, and the p ⁻ type semiconductor layer 26. The n ⁻ type semiconductor layer 27 and the anode region A made of a p ⁺ type semiconductor layer provided on the n ⁻ type semiconductor layer 27 are provided. That is, the semiconductor layer including the p ⁻ type semiconductor layer 26, the n ⁻ type semiconductor layer 27, and the anode region A is a pillar-shaped semiconductor layer. The cathode region C of the thyristor 12 is connected to the drain region D of the access transistor 11. In the present embodiment, the cathode region C and the drain region D are configured by the same semiconductor region. A gate electrode G2 is provided on the side surface of the p ⁻ type semiconductor layer 26 via a gate insulating film.

On the anode region A, an anode line AL extending in the Y direction is provided. The first memory cell and the third memory cell adjacent to the first memory cell in the opposite direction to the second memory cell share the anode line AL.

In the first memory cell and the third memory cell, the semiconductor layer (including the cathode region C, the p ⁻ -type semiconductor layer 26, the n ⁻ -type semiconductor layer 27, and the anode region A) included therein includes the insulating layer 31. And the n-type semiconductor region 32 are electrically insulated.

The element region AA is grounded via the source line SL. That is, the plurality of memory cells MC formed in the same element region AA are grounded with their substrate gate terminals SG commonly connected to the source line SL. An interlayer insulating layer 25 is embedded between the semiconductor substrate 20 and the bit line BL. Thus, the semiconductor memory device 10 according to the second embodiment is configured. In addition, about the conductivity type of a semiconductor, it is not restricted to the designation | designated of the above conductivity type, You may reverse the above conductivity type.

As described above in detail, in the second embodiment, the access transistor 11 and the thyristor 12 constitute a memory cell, and the first memory cell and the second memory cell adjacent to one of the memory cell are The source region S and the bit line contact BC provided on the source region S are shared. The first memory cell and the third memory cell adjacent to the other one share the anode line AL. Furthermore, the substrate gates of the access transistors 11 are commonly connected to the plurality of memory cells formed in the same element region AA.

Therefore, according to the second embodiment, the number of anode lines AL and bit line contacts BC can be reduced. As a result, the wiring area can be reduced, so that the area of the memory cell array can be reduced. In addition, since the thyristor 12 is configured vertically, the area of the memory cell array can be further reduced.

Also, it is not necessary to provide an element isolation region between memory cells sharing the source region S of the access transistor 11. As a result, the area of the memory cell array can be further reduced because there is no element isolation region.

Since the thyristor 12 is a vertical type, the thyristor 12 is electrically insulated from the semiconductor substrate 20 except that the cathode region C is connected to the drain region D. As a result, the adjacent thyristors can be controlled independently, and the connection relationship shown in FIG. 2 can be realized.

[Third embodiment]
The third embodiment shows another configuration example of the thyristor 12, and the volatile semiconductor memory device 10 is configured using a thyristor having a MOS structure.

FIG. 20 is a cross-sectional view showing the configuration of the volatile semiconductor memory device 10 according to the third embodiment of the present invention. The circuit configuration of the volatile semiconductor memory device 10 and the device structure of the access transistor 11 are the same as those in the first embodiment.

The thyristor 12 is provided on the cathode region C made of an n ⁺ type semiconductor layer provided in the semiconductor substrate 20, the p ⁻ type semiconductor layer 26 provided on the cathode region C, and the p ⁻ type semiconductor layer 26. Insulating film (tunnel insulating film) 33 and anode electrode A provided on insulating film 33 are provided. A gate electrode G2 is provided on the side surface of the p ⁻ type semiconductor layer 26 via a gate insulating film. The anode electrode A corresponds to the anode line AL in FIG. That is, the anode electrode A shown in FIG. 20 extends in the Y direction. The gate electrode G2 functions as the word line WL2. The cathode region C of the thyristor 12 is connected to the drain region D of the access transistor 11. In the present embodiment, the cathode region C and the drain region D are configured by the same semiconductor region.

The anode electrode A can be made of various conductive materials such as polysilicon, TaN, Ti, Al, TaC, TiN, TiAlN, Cu, Au, and RrO. As the insulating film 33, silicon oxide or the like is used.

The first memory cell and the second memory cell adjacent to one of the first memory cells are arranged so that the access transistors 11 included in the first memory cell face each other, and the source region S of the access transistor 11 is Sharing.

The first memory cell and the third memory cell adjacent to the first memory cell in the opposite direction to the second memory cell share the anode electrode A. In the first memory cell and the third memory cell, the semiconductor layer (including the cathode region C and the p ⁻ -type semiconductor layer 26) included therein is electrically connected by the insulating layer 31 and the n-type semiconductor region 32. Insulated.

The element region AA is grounded via the source line SL. That is, the plurality of memory cells MC formed in the same element region AA are grounded with their substrate gate terminals SG commonly connected to the source line SL. Thus, the semiconductor memory device 10 according to the third embodiment is configured. In addition, about the conductivity type of a semiconductor, it is not restricted to the designation | designated of the above conductivity type, You may reverse the above conductivity type.

Next, the operation of the thyristor 12 will be described. 21 to 23 are energy band diagrams for explaining the operation of the thyristor 12. FIGS. 21 to 23 show the anode electrode A (electrode), the insulating film 33, the p ⁻ type semiconductor layer 26 (p ⁻ type semiconductor), and the n ⁺ type semiconductor layer C (n ⁺ type semiconductor) constituting the thyristor 12. Shows the energy band. Ef is the Fermi level, Ec is the conduction band energy level, Ev is the valence band energy level, and Efm is the metal Fermi level.

As shown in FIG. 21, when no voltage is applied to the anode electrode A, no voltage is applied to the PN junction, and only a built-in potential at 0 V is generated at the PN junction, and the p ⁻ type semiconductor Minority carriers (electrons) are not generated in the layer 26. Therefore, no current flows through the thyristor 12, and the thyristor 12 is off (high resistance state).

As shown in FIG. 22, when a voltage is applied to the anode electrode A, the p ⁻ type semiconductor layer at the interface of the insulating film 33 is depleted, and the voltage of the anode electrode A is applied to this depleted region. The p ⁻ type semiconductor layer 26 is not inverted and minority carriers are not generated. On the other hand, since an electric field is slightly applied to the insulating film 33, holes start to be injected from the anode electrode A.

When a voltage is further applied to the anode electrode A, hole injection from the anode electrode A becomes remarkable, and the potential of the p ⁻ -type semiconductor layer 26 is lowered. At the same time, electrons are easily injected from the cathode (n ⁺ type semiconductor layer C), and finally the p ⁻ type semiconductor layer 26 is inverted as shown in FIG.

At this time, the voltage of the anode electrode A is all applied to the insulating film 33, and the electron current and the hole current increase (ON state (low resistance state)). Since holes are always injected into the p ⁻ -type semiconductor layer 26, the potential in this region is always lowered and the inverted state is maintained. In addition, the amount of holes passing through the insulating film 33 does not vary, and the on state continues. The voltage applied to the word line WL2 (gate electrode G2) has the effect of promoting the inversion state of the p ⁻ -type semiconductor layer 26.

Once the inversion state of the p ⁻ -type semiconductor layer 26 is formed, the hole current decreases when the voltage of the anode electrode A is lowered, but the on-current is maintained until the inversion state of the p ⁻ -type semiconductor layer 26 continues. (Electron current and hole current) flow. In order to turn off the thyristor 12 in the on state, the voltage of the anode electrode A is set to a predetermined voltage or lower.

As described above, the thyristor 12 shown in FIG. 20 has a high resistance state and a low resistance state in accordance with voltages applied to the anode, the cathode, and the gate, and thus can be used as a memory element.

As described in detail above, according to the third embodiment, the same effects as those of the second embodiment can be obtained. Further, since the number of semiconductor layers constituting the thyristor 12 can be reduced as compared with the thyristor of the second embodiment, the memory cell array can be further miniaturized and the manufacturing cost can be further reduced.

[Fourth Embodiment]
The fourth embodiment is another configuration example of a thyristor having a MOS structure. FIG. 24 is a cross-sectional view showing the configuration of the volatile semiconductor memory device 10 according to the fourth embodiment of the present invention. The circuit configuration of the volatile semiconductor memory device 10 and the device structure of the access transistor 11 are the same as those in the first embodiment.

The semiconductor substrate 20, and the cathode region C made of n ⁺ -type semiconductor layer, and an n ⁺ -type semiconductor layer 35 is provided apart from each other. On the semiconductor substrate 20 between the cathode region C and the n ⁺ type semiconductor layer 35, a gate electrode G2 is provided via a gate insulating film. Side walls 34 are provided on both side surfaces of the gate electrode G1. An insulating film (tunnel insulating film) 33 is provided on the n ⁺ type semiconductor layer 35, and an anode electrode A is provided on the insulating film 33. In this way, the thyristor 12 of the third embodiment is configured.

The anode electrode A corresponds to the anode line AL in FIG. That is, the anode electrode A shown in FIG. 24 extends in the Y direction. The gate electrode G2 functions as the word line WL2. The cathode region C of the thyristor 12 is shared with the drain region D of the access transistor 11.

The first memory cell and the third memory cell adjacent to the first memory cell in the opposite direction to the second memory cell share the anode electrode A. In the first memory cell and the third memory cell, the n ⁺ -type semiconductor layer 35 included therein is electrically insulated by the insulating layer 31 and the n-type semiconductor region 32.

In the thyristor 12 configured as described above, the n ⁺ type semiconductor layer 35 functions as a conductor, and serves to electrically connect the p ⁻ type semiconductor region immediately below the gate electrode G2, the insulating film 33, and the anode electrode A. Fulfill. Therefore, the contact relationship including the anode electrode A, the insulating film 33, the p ⁻ type semiconductor region, and the n ⁺ type semiconductor layer (cathode region) C is the same as that in FIG. That is, the thyristor 12 of the fourth embodiment operates in the same manner as the thyristor of the third embodiment.

The n ⁺ type semiconductor layer 35 can be omitted. FIG. 25 is a cross-sectional view showing another configuration example of the thyristor 12. An insulating film 33 is provided on the semiconductor substrate 20, and an anode electrode A is provided on the insulating film 33. The anode electrode A is disposed adjacent to the gate electrode G2. Even when the thyristor 12 is configured in this manner, the same operation as the thyristor of the third embodiment can be realized.

As described in detail above, according to the fourth embodiment, the same effect as that of the second embodiment can be obtained. Further, the thyristor 12 can be manufactured using a process similar to that of the MOSFET. Thereby, manufacturing cost can be reduced.

The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. For example, regarding the specific configuration of each element constituting the volatile semiconductor memory device, as long as a person skilled in the art can implement the present invention in a similar manner by appropriately selecting from a known range and obtain the same effect, It is included in the scope of the present invention.
In addition, combinations of any two or more elements of each specific example within the technically possible range are also included in the scope of the present invention as long as they include the gist of the present invention.

In addition, all volatile semiconductor memory devices that can be implemented by those skilled in the art based on the volatile semiconductor memory device described above as an embodiment of the present invention are included in the present invention as long as they include the gist of the present invention. Belongs to the range.
In addition, in the category of the idea of the present invention, those skilled in the art can conceive of various changes and modifications, and it is understood that these changes and modifications also belong to the scope of the present invention. .

MC ... memory cell, BL ... bit line, WL ... word line, AL ... anode line, BC ... bit line contact, AC ... anode contact, SL ... source line, AA ... element region, S ... source region, D ... drain region G1, G2 gate electrodes, C ... cathode region, A ... anode region, 10 ... volatile semiconductor memory device, 11 ... access transistor, 12 ... thyristor, 20 ... semiconductor substrate, 21 ... element isolation insulating layer, 22, 24,

Reference numerals

30, 34 ... sidewalls, 23 ... SiGe layer, 25 ... interlayer insulating layer, 26 ... p ^- type semiconductor layer, 27 ... n ^- type semiconductor layer, 28 ... insulating layer, 29 ... dummy insulating layer, 31 ... insulating layer, 32 ... n-type semiconductor region, 33 ... insulating film, 35 ... n ⁺ type semiconductor layer.

Claims

A semiconductor substrate;
An insulating layer partially provided on the semiconductor substrate;
A semiconductor layer provided on the insulating layer;
First to third memory cells,
Each of the first to third memory cells is provided on the semiconductor substrate, has a MOSFET having a source, a drain, and a first gate, and is provided on the semiconductor layer, and has an anode, a cathode, and a second gate. A thyristor, and the drain is electrically connected to the cathode;
In the first and second memory cells, sources are electrically connected to each other,
The volatile semiconductor memory device, wherein anodes of the first and third memory cells are electrically connected to each other.
The semiconductor substrate is of a first conductivity type;
The source and the drain are of a second conductivity type;
The semiconductor layer includes a first semiconductor region of a second conductivity type, a second semiconductor region of a first conductivity type, a third semiconductor region of a second conductivity type, a fourth semiconductor of a first conductivity type. The semiconductor regions are joined in order,
The first semiconductor region corresponds to the cathode;
The fourth semiconductor region corresponds to the anode;
The volatile semiconductor memory device according to claim 1, wherein the second gate is provided on the second semiconductor region.
A first wiring extending in a first direction and electrically connected to a source of the first to third memory cells;
The volatile semiconductor memory device according to claim 1, wherein the first to third memory cells are arranged in the first direction.
The volatile semiconductor according to claim 3, further comprising a contact provided on the source and connected to the first wiring and shared by the first and second memory cells. Storage device.
3. The volatile semiconductor memory device according to claim 2, wherein an insulating layer for electrically separating adjacent memory cells is not formed on the semiconductor substrate.
2. The semiconductor device according to claim 1, further comprising: a second wiring shared by the first and third memory cells and electrically connected to anodes of the first and third memory cells. Volatile semiconductor memory device.
A MOSFET having a source, a drain, a first gate, and a substrate gate, and a thyristor having an anode, a cathode, and a second gate are each configured, and the drain is electrically connected to the cathode. Comprising a third memory cell;
In the first and second memory cells, sources are electrically connected to each other,
The anodes of the first and third memory cells are electrically connected to each other,
In the volatile semiconductor memory device, the first to third memory cells have substrate gates electrically connected to each other.
The MOSFET is provided on a semiconductor substrate of a first conductivity type,
The source and the drain are of a second conductivity type;
The thyristor is
A first semiconductor region provided on the semiconductor substrate and corresponding to the cathode and having a second conductivity type;
A second semiconductor region provided on the first semiconductor region and having a first conductivity type;
A third semiconductor region provided on the second semiconductor region and having a second conductivity type;
A fourth semiconductor region provided on the third semiconductor region and corresponding to the anode and having a first conductivity type;
The volatile semiconductor memory device according to claim 7, wherein the second gate is provided on a side surface of the second semiconductor region.
The MOSFET is provided on a semiconductor substrate of a first conductivity type,
The source and the drain are of a second conductivity type;
The thyristor is
A first semiconductor region provided on the semiconductor substrate and corresponding to the cathode and having a second conductivity type;
A second semiconductor region provided on the first semiconductor region and having a first conductivity type;
An insulating film provided on the second semiconductor region;
An electrode provided on the insulating film and corresponding to the anode;
The volatile semiconductor memory device according to claim 7, wherein the second gate is provided on a side surface of the second semiconductor region.
The MOSFET is provided on a semiconductor substrate of a first conductivity type,
The source and the drain are of a second conductivity type;
The thyristor is
A semiconductor region provided on the semiconductor substrate and corresponding to the cathode and having a second conductivity type;
An insulating film provided on the semiconductor substrate;
An electrode provided on the insulating film and corresponding to the anode;
The volatile semiconductor memory device according to claim 7, wherein the second gate is provided on the semiconductor substrate between the semiconductor region and the electrode.