JP2008103554A - Back irradiation image sensor and semiconductor substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a back irradiation image sensor which can achieve separation of signal charge among different photoelectric conversion regions even when the depletion layer is made thick in the photoelectric conversion region. <P>SOLUTION: The back irradiation image sensor 100 which performs imaging by irradiating a p-substrate 30 from the back side and reading out charges generated in the p-substrate 30 in response to the light from the surface side of the p-substrate 30 comprises an n-type semiconductor layer 4 formed in the p-substrate 30 and storing the charges, and a p-type semiconductor layer 2 formed from the back side to the inside of the p-substrate wherein an n-type or p-type semiconductor layer or an i-type semiconductor layer having impurity concentration of 1.0×10<SP>14</SP>/cm<SP>3</SP>or less is included between the n-type semiconductor layer 4 and the p-type semiconductor layer 2. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a backside illuminating type imaging device that irradiates light from a back surface side of a semiconductor substrate, reads out charges generated in the semiconductor substrate in response to the light from the front surface side of the semiconductor substrate, and performs imaging.

FIG. 15 is a schematic cross-sectional view of the most common structure of an interline type CCD solid-state imaging device.
As shown in FIG. 15, a p-type semiconductor layer 102 made of a p-type impurity is formed in a deep portion of an n-type silicon substrate 101, and n for accumulating electric charges is formed on the surface portion of the n-type silicon substrate 101. An n-type semiconductor layer 104 made of a p-type impurity and a p-type semiconductor layer 105 made of a high-concentration p-type impurity for preventing surface dark current are formed, and a region from the surface of the silicon substrate 101 to the surface of the p-type semiconductor layer 102 ( Charges generated in a photoelectric conversion region that generates charges that contribute to imaging are accumulated in the n-type semiconductor layer 104. In the silicon substrate 101, an element isolation layer 103 for separating adjacent photoelectric conversion regions is formed.

  FIG. 16 shows a potential profile on the AA line in FIG. The thickness of the depletion layer in the photoelectric conversion region is about 2 μm, and the charge generated in the deep part of the silicon substrate 101 does not go to the n-type semiconductor layer 104 and does not contribute to imaging. FIG. 17 shows the relationship between the thickness of the depletion layer in the photoelectric conversion region and the light absorption rate in the photoelectric conversion region. The light absorption coefficient of silicon has a wavelength dependency as shown in FIG. 18, and light having a longer wavelength transmits to the deep part of the silicon substrate 101.

  For example, paying attention to green light having a wavelength of 550 nm, only 75% of light is absorbed at a depletion layer thickness of 2 μm, but 97% of light is absorbed at a depletion layer thickness of 5 μm. From the characteristics shown in FIG. 17, it can be seen that the depletion layer thickness in the photoelectric conversion region is preferably 5 μm or more in order to achieve high sensitivity.

  Conventionally, light is irradiated from the back surface side of the semiconductor substrate, and charges generated in the semiconductor substrate in response to the light are accumulated in a charge accumulation region formed on the front surface side of the semiconductor substrate, and the charges accumulated here are accumulated. A backside-illuminated imaging device that outputs images according to the outside by a CCD, CMOS circuit, or the like for imaging, that is, a solid-state imaging device that is used by irradiating light from the backside of the silicon substrate 101 in FIG. 15 is proposed. ing.

  It has long been known that a high photoelectric conversion efficiency can be realized with this back-illuminated image sensor. For this reason, in this backside illuminating type imaging device, if the depletion layer thickness can be 10 μm or more, a device having very high sensitivity can be realized. However, in a back-illuminated image sensor, in order to reliably realize separation of signal charges between different photoelectric conversion regions, continuous from the back surface of the silicon substrate on which light is incident to the charge storage layer formed on the front side of the silicon substrate. Potential slopes need to be formed. In other words, it is necessary to make it possible for charges generated near the back surface of the silicon substrate in each photoelectric conversion region to move properly to the charge storage layer in the photoelectric conversion region.

  In a normal buried photodiode, the depletion potential is 3 to 4 V, and the potential difference when the potential of the p-type semiconductor layer for reducing dark current provided on the back surface of the silicon substrate of the back-illuminated image sensor is 0 V. Is only 3-4V. It is quite difficult to form a depletion layer having a thickness of 10 μm with such a potential difference so as to have a continuous potential slope.

  Therefore, conventionally, a plurality of n-type semiconductor layers formed by gradually changing the impurity concentration are stacked on the silicon substrate 101 between the p-type semiconductor layer 102 and the n-type semiconductor layer 104 shown in FIG. Thus, a technique that enables formation of a continuous potential slope is disclosed (see Patent Document 1).

JP 2006-134915 A

  FIG. 19 is a diagram illustrating a result of performing a simulation of a backside illumination type image sensor with the density profile shown in the example of Patent Document 1. In FIG. In FIG. 19, the coordinate axis z indicates the depth of the semiconductor substrate, and z = 0 is the surface of the semiconductor substrate. As described above, when the device simulation is performed with the concentration profile shown in the example of Patent Document 1, as shown in FIG. 19, an electron pool is generated in a large part of the photoelectric conversion region. It was found that the concentration profiles of the examples were not realistic. Further, even when the device simulation is performed in the same manner by reducing the concentration digit of the concentration profile shown in the example of Patent Document 1 by two digits, the position of 3 μm from the surface of the semiconductor substrate is shown in FIG. It is difficult to read out the signal charge accumulated at this depth from a CCD or CMOS circuit formed on the surface of the semiconductor substrate because of problems such as afterimages.

  The present invention has been made in view of the above circumstances, and even when the depletion layer of the photoelectric conversion region is thickened, the backside illumination type capable of reliably realizing separation of signal charges between different photoelectric conversion regions. An object is to provide an imaging device.

The backside illumination type imaging device of the present invention irradiates light from the backside of the semiconductor substrate, and reads back the charge generated in the semiconductor substrate in response to the light from the topside of the semiconductor substrate to perform imaging. A first conductivity type first semiconductor layer for accumulating the electric charge formed in the semiconductor substrate, and a first conductivity type formed inside from the back surface of the semiconductor substrate. An impurity concentration of 1.0 × 10 ¹⁴ / cm between the first semiconductor layer and the second semiconductor layer in the semiconductor substrate. ³ or less third semiconductor layers are included.

In the backside illumination type imaging device of the present invention, the third semiconductor layer is n-type or p-type, and the impurity concentration thereof is 2.0 × 10 ¹³ / cm ³ or more, 1.0 × 10 ¹⁴ / cm ^3. It is as follows.

The backside illumination type imaging device of the present invention irradiates light from the backside of the semiconductor substrate, and reads back the charge generated in the semiconductor substrate in response to the light from the topside of the semiconductor substrate to perform imaging. A first conductivity type first semiconductor layer for accumulating the electric charge formed in the semiconductor substrate, and a first conductivity type formed inside from the back surface of the semiconductor substrate. An impurity concentration of 2.0 × 10 ¹⁴ / cm between the first semiconductor layer and the second semiconductor layer in the semiconductor substrate. ^{A third} semiconductor layer having a first conductivity type of ³ or less and a fourth semiconductor layer having a second conductivity type having an impurity concentration of 2.0 × 10 ¹⁴ / cm ³ or less.

The backside-illuminated imaging device of the present invention includes a fifth semiconductor layer having an impurity concentration of 1.0 × 10 ¹⁴ / cm ³ or less between the third semiconductor layer and the fourth semiconductor layer.

A semiconductor substrate of the present invention is a semiconductor substrate used for a semiconductor element, and is formed on a first semiconductor layer of a first conductivity type formed inside from one surface of the semiconductor substrate, and on the first semiconductor layer And a second semiconductor layer having an impurity concentration of 1.0 × 10 ¹⁴ / cm ³ or less.

In the semiconductor substrate of the present invention, the second semiconductor layer is n-type or p-type, and the impurity concentration thereof is 2.0 × 10 ¹³ / cm ³ or more and 1.0 × 10 ¹⁴ / cm ³ or less. .

A semiconductor substrate of the present invention is a semiconductor substrate used for a semiconductor element, and is formed on a first semiconductor layer of a first conductivity type formed inside from one surface of the semiconductor substrate, and on the first semiconductor layer The impurity concentration formed on the second semiconductor layer of the first conductivity type of 2.0 × 10 ¹⁴ / cm ³ or less or the opposite second conductivity type, and the impurity formed on the second semiconductor layer A ^third semiconductor layer having a conductivity type opposite to the second semiconductor layer having a concentration of 2.0 × 10 ¹⁴ / cm ³ or less.

The semiconductor substrate of the present invention includes a fourth semiconductor layer having an impurity concentration of 1.0 × 10 ¹⁴ / cm ³ or less between the second semiconductor layer and the third semiconductor layer.

  In the backside illuminating type imaging device of the present invention, the thickness from the front surface to the back surface of the semiconductor substrate is 5 μm or more, preferably 8 μm or more.

  The semiconductor substrate of the present invention has a thickness from the front surface to the back surface of 5 μm or more, preferably 8 μm or more.

  ADVANTAGE OF THE INVENTION According to this invention, even when the depletion layer of a photoelectric conversion area | region is thickened, the back irradiation type imaging device which can implement | achieve separation of the signal charge between different photoelectric conversion areas can be provided.

  Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a partial cross-sectional schematic view of an interline back-illuminated image sensor for explaining an embodiment of the present invention.
A back-illuminated image sensor 100 shown in FIG. 1 includes a p-type semiconductor layer 1 (hereinafter referred to as p layer 1) 1 and a p-type semiconductor layer 2 (hereinafter referred to as p ++ layer 2) having a higher impurity concentration than p layer 1. A p-type semiconductor substrate 30 (hereinafter referred to as a p-substrate 30) is provided. The back-illuminated image sensor 100 performs imaging by allowing light to enter from the lower side to the upper side in the drawing. In the present specification, of the two surfaces perpendicular to the light incident direction of the p-substrate 30, the surface on the light incident side is referred to as the back surface, and the opposite surface is referred to as the surface. In addition, the direction in which the incident light travels is defined as the upper direction of each component when the components constituting the back-illuminated image sensor 100 are used as a reference, and the direction opposite to the direction in which the incident light travels is defined as the component. It is defined as below. Further, a direction orthogonal to the back surface and the front surface of the p substrate 30 is defined as a vertical direction, and a direction parallel to the back surface and the front surface of the p substrate 30 is defined as a horizontal direction.

  On the same surface extending in the horizontal direction near the surface of the p substrate 30 in the p layer 1, an n-type semiconductor layer 4 (hereinafter referred to as an n layer 4) for accumulating charges generated in the p substrate 30 in response to incident light. Multiple). The n layer 4 includes an n type semiconductor layer 4a (hereinafter referred to as an n layer 4a) formed on the surface side of the p substrate 30, and an n type having a lower impurity concentration than the n layer 4a formed under the n layer 4a. Although it has a two-layer structure with a semiconductor layer 4b (hereinafter referred to as n-layer 4b), it is not limited thereto. The charges generated in the n layer 4 and the charges generated in the p substrate 30 on the path of light incident on the n layer 4 are accumulated in the n layer 4.

  A high-concentration p-type semiconductor layer 5 (hereinafter referred to as p + layer 5) is formed on each n layer 4 to prevent dark charges generated on the surface of the p substrate 30 from accumulating in each n layer 4. Yes. In each p + layer 5, an n-type semiconductor layer 6 (hereinafter referred to as n + layer 6) having an impurity concentration higher than that of n layer 4 is formed from the surface of p substrate 30 toward the inside thereof. The n + layer 6 functions as an overflow drain for discharging unnecessary charges accumulated in the n layer 4, and the p + layer 5 also functions as an overflow barrier for the overflow drain. As illustrated, the n + layer 6 has an exposed surface exposed on the surface of the p substrate 30.

  A charge transfer channel 12 made of an n-type semiconductor having an impurity concentration higher than that of the n layer 4 is formed on the right side of the p + layer 5 and the n layer 4, and the p + layer 5 is formed around the charge transfer channel 12. A p-type semiconductor layer 11 (hereinafter referred to as a p-layer 11) having a lower impurity concentration is formed.

  In the p layer 11 and the p layer 1 between the p + layer 5 and the n layer 4 and the charge transfer channel 12, a charge reading region (not shown) for reading out the charges accumulated in the n layer 4 to the charge transfer channel 12. ) Is formed. Charge transfer for controlling the charge transfer operation by supplying a voltage to the charge transfer channel 12 via the gate insulating layer 20 made of a silicon oxide film, an ONO film or the like above the charge transfer channel 12 and the charge readout region. An electrode 13 made of polysilicon or the like serving as an electrode and a charge readout electrode for controlling a charge readout operation by supplying a readout voltage to the charge readout region is formed. An insulating film 14 such as silicon oxide is formed around the electrode 13. The charge transfer channel 12 and the electrode 13 thereabove constitute a CCD.

  An element isolation layer 15 made of a p-type semiconductor is formed below the p layer 11 between the adjacent n layers 4. The element isolation layer 15 is for preventing the charges to be accumulated in the n layer 4 from leaking to the adjacent n layer 4.

  A gate insulating layer 20 is formed on the surface of the p substrate 30, and an insulating layer 9 such as silicon oxide is formed on the gate insulating layer 20, and an electrode 13 and an insulating film 14 are formed in the insulating layer 9. Is buried. Further, in the gate insulating layer 20 and the insulating layer 9, a contact hole having an area equal to or smaller than the exposed surface in plan view is formed on the exposed surface of the n + layer 6 in the contact hole. An electrode 7 is formed.

  The electrode 7 only needs to be a conductive material, and is particularly preferably composed of a metal material such as W (tungsten), Ti (titanium), or Mo (molybdenum), or silicide with these. Between the electrode 7 and the n + layer 6, it is preferable to provide a diffusion preventing layer for preventing diffusion of the conductive material constituting the electrode 7. For example, TiN (titanium nitride) is used as a constituent material of the diffusion prevention layer. By providing the diffusion prevention layer, the PN junction between the n + layer 6 and the p + layer 5 becomes uniform, and the saturation variation between pixels can be reduced.

  An electrode 8 is formed on the insulating layer 9, and the electrode 8 is connected to the electrode 7. A protective layer 10 is formed on the electrode 8. The electrode 8 may be any conductive material. A terminal is connected to the electrode 8, and a predetermined voltage can be applied to the terminal.

  Since the charges transferred to the n + layer 6 move to the electrode 7 connected to the exposed surface of the n + layer 6 and the electrode 8 connected thereto, the n + layer 6 can function as an overflow drain.

A p ++ layer 2 is formed from the back surface of the p substrate 30 to prevent dark charges generated on the back surface of the p substrate 30 from moving to the n layer 4. A terminal is connected to the p ++ layer 2 so that a predetermined voltage can be applied to the terminal. The impurity concentration of the p ++ layer 2 is, for example, 1 × 10 ¹⁷ / cm ³ to 1 × 10 ²⁰ / cm ³ .

  Under the p ++ layer 2, an insulating layer 3 transparent to incident light such as silicon oxide or silicon nitride is formed. Under the insulating layer 3, incident light such as silicon nitride or diamond structure carbon film is used to prevent reflection of light on the back surface of the p substrate 30 due to a difference in refractive index between the insulating layer 3 and the p substrate 30. A transparent high refractive index transparent layer 16 is formed. The high refractive index transparent layer 16 is preferably a layer having a refractive index exceeding n = 1.46, such as amorphous silicon nitride which can be formed at a low temperature of 400 ° C. or lower such as plasma CVD or photo-CVD.

  Under the high refractive index transparent layer 16, a color filter layer formed by arranging a plurality of color filters 18 in the horizontal direction is formed. The plurality of color filters 18 are classified into a plurality of types of color filters that transmit light in different wavelength ranges. For example, the color filter layer includes an R color filter that transmits light in the red wavelength region, a G color filter that transmits light in the green wavelength region, and a B color filter that transmits light in the blue wavelength region. It has become the composition. The color filter 18 is formed below each of the plurality of n layers 4, and one color filter 18 is provided for each n layer 4. Further, since each n layer 4 corresponds to one n + layer 6, it can be said that the color filter 18 corresponds to one of the plurality of n + layers 6.

  A light shielding member 17 for preventing color mixture is formed between adjacent color filters 18. The light shielding member 17 may be any member having a function of not transmitting light, and a metal having a low visible light transmittance such as W, Mo, and Al (aluminum) or a black filter can be used.

  The light shielding member 17 has a cross-sectional shape that is tapered (a triangle whose apex is directed toward the light incident side, or a trapezoid whose upper base is longer than the lower base) that widens toward the back surface of the p substrate 30. Is preferred. By doing in this way, the light perpendicularly incident on the light shielding member 17 can be reflected by the tapered surface and guided into the p substrate 30, and the light utilization efficiency can be increased.

  Under each color filter 18, a microlens 19 is formed. The shape of the microlens 19 is determined so that the refracted light becomes an optical path that avoids the light blocking member 17 between the color filter 18 above and the color filter 18 adjacent to the color filter 18. . Further, the focal point of the microlens 19 is designed to be in the center of the n layer 4. Further, the arrangement pitch of the microlenses 19 may be different from the arrangement pitch of the n layer 4 in order to reduce shading according to the characteristics of the optical system to be used.

  Of the region from the upper surface of the n layer 4 to the back surface of the p substrate 30, the region partitioned by the element isolation layer 15 in plan view is a region that performs photoelectric conversion contributing to imaging, and is hereinafter referred to as a photoelectric conversion region. Since a signal corresponding to the charge generated in one photoelectric conversion region is the basis of one pixel data of image data, this photoelectric conversion region is also referred to as a pixel in this specification. That is, the back-illuminated image sensor 100 includes a plurality of pixels and a CCD-type or CMOS-type signal readout unit that reads out a signal corresponding to the charge generated in each of the plurality of pixels.

  In the back-illuminated imaging device 100 configured as described above, light incident on one microlens 19 enters the color filter 18 above the microlens 19, and light transmitted therethrough enters the color filter 18. The light enters the corresponding n layer 4. At this time, charges are also generated in the portion of the p substrate 30 that serves as a path for incident light. However, the charges move to the n layer 4 through the potential slope formed in the photoelectric conversion region and are accumulated there. The The charges generated here upon entering the n layer 4 are also accumulated here. The charges accumulated in the n layer 4 are read and transferred to the charge transfer channel 12, converted into a signal by an output amplifier, and output to the outside.

FIG. 2 is a diagram showing a potential profile of the BB line shown in FIG.
As shown in FIG. 2, it can be seen that potential wells are formed in the n + layer 6 and the photoelectric conversion region, respectively, and the p + layer 5 functions as a barrier between these potential wells. The charge exceeding the saturation capacity of the potential well formed in the photoelectric conversion region flows into the potential well formed in the n + layer 6, and the flowed-in charge moves to the electrode 7 and is discharged to the outside. Therefore, the saturation capacity of the n layer 4 can be controlled by changing the voltage applied to the electrode 7 connected to the n + layer 6 to adjust the height of the barrier of the p + layer 5. For example, in the moving image shooting mode in which signals are added and read out, overflow in the charge transfer channel 12 can be prevented by performing control to reduce the saturation capacity of the n layer 4.

  Further, as shown by a broken line in FIG. 2, a voltage at a level that can eliminate the barrier formed in the p + layer 5 is applied to the electrode 7 connected to the n + layer 6 to form the photoelectric conversion region. Since the charge in the potential well can be reset, an electronic shutter can be realized by utilizing this fact.

  The electrode 7 connected to the n + layer 6 is connected in common for each type of color filter 18 corresponding to the n + layer 6, and voltage is independently applied to each electrode 7 common to each type of color filter 18. A configuration is also conceivable so that the voltage can be applied. In this case, it is possible to independently apply an electronic shutter for each photoelectric conversion region corresponding to each type of color filter. That is, the charge accumulation time in each photoelectric conversion region can be changed for each color of light incident thereon, and an output with a uniform color balance can be obtained by controlling the charge accumulation time.

  In addition, a plurality of n + layers 6 includes a first group of n + layers 6 corresponding to the n layer 4 that reads charges in a shooting mode that performs thinning readout such as a moving image shooting mode, and n that does not read charges in the shooting mode. It is classified into a second group consisting of n + layers 6 corresponding to the layers 4, and electrodes 7 are connected in common to each n + layer 6 belonging to the same group, and each of the common electrodes 7 is connected. A configuration in which a voltage can be applied independently is also conceivable. In this case, by changing the applied voltage for each group, it is possible to enhance the inter-pixel blooming suppression effect for highlight light.

  The voltage application to the electrodes 7 and 8 may be performed by a driver that drives the backside illumination type image sensor 100 in an imaging apparatus such as a digital camera equipped with the backside illumination type image sensor 100.

  The silicon substrate needs to have a thickness of about 10 μm as shown in FIG. 17 in order to absorb almost all the light in the visible range (about 90% or more) due to the difference in the light absorption coefficient for each wavelength. I know. For this reason, also in the backside illumination type imaging device 100, it is preferable that the length of the p substrate 30 in the vertical direction is about 10 μm. By doing so, visible light can be absorbed without fail, and the sensitivity can be improved.

  Of course, as can be seen from the data in FIG. 17, if the length in the vertical direction of the p-substrate 30 is 5 μm or more, sufficiently high sensitivity can be realized compared to the conventional case.

When the vertical length of the p substrate 30 is about 10 μm, there are the following advantages.
Since light hardly reaches the charge transfer channel 12, no back-shielding layer for shielding the charge transfer channel 12 is provided in the p substrate 30, and the back-illuminated image sensor is made to be a frame interline type. Therefore, an image sensor with sufficiently low smear can be realized even in the interline type.
・ Quantum efficiency increases and sensitivity improves.
・ Long wavelength sensitivity is increased.
・ Near-infrared sensitivity increases dramatically.

  However, when the vertical length of the p-substrate 30 is increased to 10 μm, the depletion voltage of the n layer 4 (about 3 V used in the current image sensor) is affected by the charge separation layer 15 and the like. It becomes difficult to form a depletion layer in the photoelectric conversion region. Therefore, the concentration of the p substrate 30 is optimized so that a depletion layer can be formed in each photoelectric conversion region, and a potential gradient that can move the charge generated in this depletion layer to the n layer 4 is provided. It is necessary to design.

As a result of simulation, the present inventor has found that the above conditions can be satisfied by configuring the p substrate 30 to have the following configurations (1) to (3).
(1) An n-type semiconductor layer, a p-type semiconductor layer, or an i-type semiconductor layer having an impurity concentration of 1 × 10 ¹⁴ / cm ³ or less in an intermediate layer between the n layer 4 and the p ++ layer 2 shown in FIG. the configuration (2) the intermediate layer containing, including the impurity concentration is 2 × ¹⁰ 14 / cm ³ or less of the n-type semiconductor layer, an impurity concentration of 2 × ¹⁰ 14 / cm ³ or less of p-type semiconductor layer structure ( 3) (between the n-type semiconductor layer and the p-type semiconductor layer of 2), 1 × ¹⁰ 14 / cm ³ or less of the n-type semiconductor layer is an impurity concentration, the impurity concentration is 1 × ¹⁰ 14 / cm ³ or less of p-type Configuration including any of semiconductor layer and i-type semiconductor layer

  Hereinafter, the simulation performed by the inventors will be described.

(Simulation 1)
FIG. 3 is a diagram illustrating a model configuration of the semiconductor substrate used in the simulation 1.
The semiconductor substrate shown in FIG. 3 includes a silicon oxide layer 32 (having a thickness of 300 mm) corresponding to the insulating layer 3 in FIG. 1 formed on the support substrate 31 and a p ++ layer in FIG. 1 formed on the silicon oxide layer 32. P-type semiconductor layer 33 corresponding to 2 (impurity concentration = 1 × 10 ¹⁹ / cm ³ , thickness = 0.2 μm) and n corresponding to the n-layer 4 in FIG. 1 formed above the p-type semiconductor layer 33. Type semiconductor layer 35 (impurity concentration = 4.5 × 10 ¹⁶ / cm ³ , thickness = 0.3 μm) and a p-type semiconductor layer corresponding to the p + layer 5 of FIG. 1 formed on the n-type semiconductor layer 35 36 (impurity concentration = 1 × 10 ¹⁹ / cm ³ , thickness = 0.2 μm) and an intermediate layer 34 between the p-type semiconductor layer 33 and the n-type semiconductor layer 35. The thickness from the front surface to the back surface of the semiconductor substrate shown in FIG. 3 was 8 μm. The depletion potential of the n-type semiconductor layer 35 was adjusted to 3 to 4V.

  Since the p-type semiconductor layer 33 is biased to 0 V, a potential difference of about 3 V is generated between the maximum potential point of the photoelectric conversion region (0.5 μm from the surface of the semiconductor substrate in the model of FIG. 3) and the p-type semiconductor layer 33. To do. In order to form a depletion layer having a thickness of nearly 8 μm with a potential difference of 3 V, the intermediate layer 34 needs to be easily depleted, and it was considered that the impurity concentration of this layer must be considerably low.

The inventor first simulated the intermediate layer 34 as an n-type semiconductor layer or a p-type semiconductor layer having an impurity concentration of 2 × 10 ¹⁴ / cm ³ . FIG. 4 shows a simulation result when the intermediate layer 34 is a p-type semiconductor layer, and FIG. 5 shows a simulation result when the intermediate layer 34 is an n-type semiconductor layer.

  When the intermediate layer 34 is a p-type semiconductor layer, the depletion layer does not reach the p-type semiconductor layer 33 as shown in FIG. 4, and when the intermediate layer 34 is an n-type semiconductor layer, as shown in FIG. Electron accumulation occurred in the deep part of the semiconductor substrate. When a layer that is not depleted is formed on the back surface of the semiconductor substrate, electrons generated in the layer diffuse into other photoelectric conversion regions or disappear due to recombination. In addition, if electrons are accumulated in the deep part of the semiconductor substrate, the photoelectric conversion regions are all connected, and independent signals cannot be extracted from the photoelectric conversion regions.

Therefore, by changing the impurity concentration of the n-type semiconductor layer and the p-type semiconductor layer applied to the intermediate layer 34, there is a region where the potential gradient becomes zero between the back surface of the semiconductor substrate and the maximum potential point of the photoelectric conversion region. As a result, the concentration was found to be 1 × 10 ¹⁴ / cm ³ or less in the case of the n-type semiconductor layer and 1.2 × 10 ¹⁴ / cm ³ or less in the case of the p-type semiconductor layer.

A simulation result when the impurity concentration of the n-type semiconductor layer and the p-type semiconductor layer applied to the intermediate layer 34 is further reduced and the impurity concentration is 0, that is, the intermediate layer 34 is an i-type semiconductor layer is shown in FIG. 6 shows, shows the simulation results when the intermediate layer 34 and p-type semiconductor layer having an impurity concentration 2.0 × ¹⁰ 13 / cm ³ in FIG. 7, the impurity concentration of the intermediate layer 34 2.0 × ¹⁰ 13 / cm FIG. 8 shows a simulation result when the n-type semiconductor layer ³ is used.

Figure 6 As shown in Figure 8, when the intermediate layer 34 and n-type semiconductor layer having an impurity concentration 2.0 × ¹⁰ 13 / cm ^3, the impurity concentration of the intermediate layer 34 2.0 × ¹⁰ 13 / cm ³ It was found that substantially the same potential distribution can be obtained in both cases where the p-type semiconductor layer is an i-type semiconductor layer having an impurity concentration of 0. That is, when the intermediate layer 34 is n-type or p-type, the potential distribution does not change much even if the impurity concentration is lower than 2.0 × 10 ¹³ / cm ³ . Therefore, the intermediate layer 34 is an n-type semiconductor layer or a p-type semiconductor layer of 2.0 × 10 ¹³ / cm ³ or more and 1.0 × 10 ¹⁴ / cm ³ or less, or an i-type semiconductor layer. Thus, it has been found that even when the depletion layer in the photoelectric conversion region is thickened, signal charge separation between different photoelectric conversion regions can be reliably realized.

(Simulation 2)
FIG. 9 is a diagram showing a model configuration of the semiconductor substrate used in the simulation 2. As shown in FIG.
The semiconductor substrate shown in FIG. 9 includes an intermediate layer 34 of the semiconductor substrate shown in FIG. 3 as a p-type semiconductor layer 34b (impurity concentration = 2 × 10 ¹⁴ / cm ³ , thickness = 3.8 μm) and a p-type semiconductor layer. The n-type semiconductor layer 34a (impurity concentration = 2.0 × 10 ¹⁴ / cm ³ , thickness = 3.5 μm) formed on the layer 34b has a two-layer structure.

A simulation result in the configuration shown in FIG. 9 is shown in FIG. As shown in FIG. 10, the intermediate layer 34 is composed of two layers, an n-type semiconductor layer and a p-type semiconductor layer, so that the impurity concentration of each of these two layers is 2.0 × 10 ¹⁴ / cm ³ . Even in this case, it was found that the region where the potential gradient becomes zero up to the maximum potential point of the photoelectric conversion region can be almost eliminated. In the configuration shown in FIG. 9, when the impurity concentration of each of the n-type semiconductor layer 34a and the p-type semiconductor layer 34b is made lower than 2.0 × 10 ¹⁴ / cm ^3, it is shown in FIGS. As shown, the potential gradient became steeper. From this result, even when the depletion layer in the photoelectric conversion region is thickened by configuring the intermediate layer 34 with two layers of an n-type semiconductor layer and a p-type semiconductor layer of 2.0 × 10 ¹⁴ / cm ³ or less, It was found that separation of signal charges between different photoelectric conversion regions can be realized with certainty.

  In the configuration shown in FIG. 9, even if the arrangement of the p-type semiconductor layer 34b and the n-type semiconductor layer 34a is reversed, the same effect is obtained.

(Simulation 3)
FIG. 11 is a diagram showing a model configuration of the semiconductor substrate used in the simulation 3. As shown in FIG.
The semiconductor substrate shown in FIG. 11 has a thickness of the p-type semiconductor layer 34b of the semiconductor substrate shown in FIG. 9 of 1.8 μm, a thickness of the n-type semiconductor layer 34a of 1.5 μm, and the n-type semiconductor layer 34a and the p-type semiconductor. The intermediate layer 34c having a thickness of 4 μm is provided between the layer 34b.

In the case of the configuration shown in FIG. 11, similarly to the simulation 1, when the simulation is performed with the intermediate layer 34c as the n-type semiconductor layer or the p-type semiconductor layer, the impurity concentration of the n-type semiconductor layer or the p-type semiconductor layer is set to 1. It was found that the potential gradient as shown in FIG. 10 can be made steeper by setting it to × 10 ¹⁴ / cm ³ or less.

The simulation result when the impurity concentration of the n-type semiconductor layer and the p-type semiconductor layer applied to the intermediate layer 34c is further reduced and the impurity concentration is 0, that is, the intermediate layer 34c is an i-type semiconductor layer is shown in FIG. 12 shows a simulation result when the intermediate layer 34c is a p-type semiconductor layer having an impurity concentration of 2.0 × 10 ¹³ / cm ³ , and FIG. 13 shows the simulation result when the intermediate layer 34c has an impurity concentration of 2.0 × 10 ¹³ / cm 3. FIG. 14 shows a simulation result when the n-type semiconductor layer ³ is used.

12 to 14 as shown in, when the intermediate layer 34c and an n-type semiconductor layer having an impurity concentration 2.0 × ¹⁰ 13 / cm ^3, the impurity concentration of the intermediate layer 34c 2.0 × ¹⁰ 13 / cm ³ When the p-type semiconductor layer is used, the potential distribution having substantially the same shape can be obtained regardless of whether the intermediate layer 34c is an i-type semiconductor layer having an impurity concentration of 0. That is, when the intermediate layer 34c is n-type or p-type, the potential distribution does not change much even if the impurity concentration is lower than 2.0 × 10 ¹³ / cm ³ . Therefore, the intermediate layer 34c is an n-type semiconductor layer or a p-type semiconductor layer of 2.0 × 10 ¹³ / cm ³ or more and 1.0 × 10 ¹⁴ / cm ³ or less, or an i-type semiconductor layer. Thus, it was found that the potential shown in FIG. 10 can be further improved.

  In the backside illumination type image pickup device 100 shown in FIG. 1, if the configuration of the p substrate 30 is the model configuration as in simulations 1 to 3 described above, even if the depletion layer of the photoelectric conversion region is thickened, It is possible to reliably realize separation of signal charges between them, and it is possible to realize a back-illuminated image sensor 100 with extremely high sensitivity.

  Also, according to the backside illumination type imaging device 100, since the overflow drain is provided on the front surface side of the p substrate 30 where the incident light hardly reaches, compared with the conventional structure in which the overflow drain is provided on the back surface side of the p substrate 30. Blue sensitivity can be improved.

  Also, by controlling the voltage applied to this overflow drain, the saturation capacity and charge accumulation time of each photoelectric conversion region can be controlled uniformly or independently, and various patterns can be easily driven. it can.

  Further, according to the backside illumination type image pickup device 100, the voltage amplitude applied to the n + layer 6 when realizing an electronic shutter can be greatly reduced as compared with the conventional structure in which an overflow drain is provided on the backside of the p substrate 30. Yes (23V → 8V). On the contrary, if the voltage amplitude is the same as the conventional one, the saturation capacity of each photoelectric conversion region can be greatly increased.

  In FIG. 1, the p ++ layer 2 is omitted. Instead, a transparent electrode such as ITO transparent to the incident light is provided under the insulating layer 3 so that a voltage can be applied to the transparent electrode. If a negative voltage is applied to the transparent electrode, dark current generated on the back surface of the p substrate 30 can be suppressed.

  In the above description, the back-illuminated image sensor 100 is of the CCD type, but it may of course be a MOS type. That is, a configuration in which a signal corresponding to the charge accumulated in the n layer 4 is read out by a CMOS circuit or an NMOS circuit may be used.

1 is a partial cross-sectional schematic diagram of an interline back-illuminated image sensor for explaining an embodiment of the present invention. The figure which shows the electric potential profile of the BB line shown in FIG. The figure which shows the model structure of the semiconductor substrate used by the simulation 1 Diagram showing impurity concentration and potential of semiconductor substrate used in simulation 1 Diagram showing impurity concentration and potential of semiconductor substrate used in simulation 1 Diagram showing impurity concentration and potential of semiconductor substrate used in simulation 1 Diagram showing impurity concentration and potential of semiconductor substrate used in simulation 1 Diagram showing impurity concentration and potential of semiconductor substrate used in simulation 1 The figure which shows the model structure of the semiconductor substrate used by the simulation 2 Diagram showing impurity concentration and potential of semiconductor substrate used in simulation 2 The figure which shows the model structure of the semiconductor substrate used by the simulation 3 Diagram showing impurity concentration and potential of semiconductor substrate used in simulation 3 Diagram showing impurity concentration and potential of semiconductor substrate used in simulation 3 Diagram showing impurity concentration and potential of semiconductor substrate used in simulation 3 Cross-sectional schematic diagram of a typical CCD solid-state image sensor The figure which shows the electric potential profile of the AA line of FIG. The figure which shows the relationship between the thickness of the depletion layer in the photoelectric conversion region and the light absorption rate Diagram showing the wavelength dependence of the light absorption coefficient of silicon The figure which shows the result of having implemented the simulation of the backside-illuminated image sensor with the density profile shown in the Example of patent document 1 The figure which shows the result of having implemented the simulation of a backside-illuminated image sensor by reducing the density shown in the Example of Patent Document 1 by two digits

Explanation of symbols

1 p layer 2 p ++ layer 3, 9, 14 Insulating layer 4 n layer 5 p + layer (overflow barrier)
6 n + layer (overflow drain)
7, 8 Electrode 10 Protective layer 11 P layer 12 Charge transfer channel 13 Charge transfer electrode / charge readout electrode 15 Element isolation layer 16 High refractive index transparent layer 17 Light shielding member 18 Color filter 19 Microlens 20 Gate insulating layer

Claims (12)

A backside-illuminated imaging device that irradiates light from the back side of a semiconductor substrate, reads out charges generated in the semiconductor substrate in response to the light from the front side of the semiconductor substrate, and performs imaging,
A first semiconductor layer of a first conductivity type for accumulating the electric charge formed in the semiconductor substrate;
A second semiconductor layer of a second conductivity type opposite to the first conductivity type formed inside from the back surface of the semiconductor substrate;
A backside-illuminated imaging device comprising a third semiconductor layer having an impurity concentration of 1.0 × 10 ¹⁴ / cm ³ or less between the first semiconductor layer and the second semiconductor layer in the semiconductor substrate. The back-illuminated image sensor according to claim 1,
The back-illuminated imaging device, wherein the third semiconductor layer is n-type or p-type, and the impurity concentration thereof is 2.0 × 10 ¹³ / cm ³ or more and 1.0 × 10 ¹⁴ / cm ³ or less. A backside-illuminated imaging device that irradiates light from the back side of a semiconductor substrate, reads out charges generated in the semiconductor substrate in response to the light from the front side of the semiconductor substrate, and performs imaging,
A first semiconductor layer of a first conductivity type for accumulating the electric charge formed in the semiconductor substrate;
A second semiconductor layer of a second conductivity type opposite to the first conductivity type formed inside from the back surface of the semiconductor substrate;
A third semiconductor layer of a first conductivity type having an impurity concentration of 2.0 × 10 ¹⁴ / cm ³ or less between the first semiconductor layer and the second semiconductor layer in the semiconductor substrate; A back-illuminated imaging device including a second conductivity type fourth semiconductor layer having a concentration of 2.0 × 10 ¹⁴ / cm ³ or less. The back-illuminated image sensor according to claim 3,
A back-illuminated imaging device including a fifth semiconductor layer having an impurity concentration of 1.0 × 10 ¹⁴ / cm ³ or less between the third semiconductor layer and the fourth semiconductor layer. A semiconductor substrate used for a semiconductor element,
A first semiconductor layer of a first conductivity type formed inside from one surface of the semiconductor substrate;
A semiconductor substrate comprising: a second semiconductor layer having an impurity concentration of 1.0 × 10 ¹⁴ / cm ³ or less formed on the first semiconductor layer. A semiconductor substrate according to claim 5, wherein
The semiconductor substrate, wherein the second semiconductor layer is n-type or p-type, and an impurity concentration thereof is 2.0 × 10 ¹³ / cm ³ or more and 1.0 × 10 ¹⁴ / cm ³ or less. A semiconductor substrate used for a semiconductor element,
A first semiconductor layer of a first conductivity type formed inside from one surface of the semiconductor substrate;
A second semiconductor layer of the first conductivity type formed on the first semiconductor layer and having an impurity concentration of 2.0 × 10 ¹⁴ / cm ³ or less or the opposite second conductivity type;
A semiconductor substrate comprising: a ^third semiconductor layer having a conductivity type opposite to the second semiconductor layer formed on the second semiconductor layer and having an impurity concentration of 2.0 × 10 ¹⁴ / cm ³ or less. A semiconductor substrate according to claim 7, wherein
A semiconductor substrate including a fourth semiconductor layer having an impurity concentration of 1.0 × 10 ¹⁴ / cm ³ or less between the second semiconductor layer and the third semiconductor layer. The back-illuminated image sensor according to any one of claims 1 to 4,
A backside illuminating type imaging device having a thickness from the front surface to the back surface of the semiconductor substrate of 5 μm or more. The back-illuminated image sensor according to claim 9,
A backside illuminating type imaging device having a thickness from the front surface to the back surface of the semiconductor substrate of 8 μm or more. A semiconductor substrate according to any one of claims 5 to 8,
A semiconductor substrate having a thickness from the front surface to the back surface of 5 μm or more. A semiconductor substrate according to claim 11, wherein
A semiconductor substrate having a thickness from the front surface to the back surface of 8 μm or more.

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