JP2008071880A - Manufacturing method of stacked electronic component - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a stacked electronic component capable of further improving electric endurance characteristics. <P>SOLUTION: The manufacturing method of the stacked electronic component laminates a green sheet 14A and a green sheet 14B so that a placement region 30A of an electrode pattern 20 on the green sheet 14A overlaps a non-placement region 40B of the electrode pattern 20 on the green sheet 14B and that a non-placement region 30B of the electrode pattern 20 on the green sheet 14A overlaps a placement region 40A of the pattern 20 on the green sheet 14B. Therefore, a thickness of the green sheet 14 increases between the electrode patterns 20 and 20. In addition, a defect of the green sheet 14 does not expand beyond a sheet interface, thereby reducing possibility of a defect occurring on the same position on the green sheets 14 and 14. The electric endurance characteristics of a ceramic capacitor 1 can thus be improved. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a multilayer electronic component.

Conventionally, in a method for manufacturing a multilayer electronic component in the field of this type of technology, a green sheet laminate in which a plurality of layers are laminated by cutting out a green sheet on which an electrode pattern is printed at a constant pitch is formed. And the dielectric material layer which has an internal electrode is produced by performing the baking process of predetermined temperature to a green sheet laminated body (for example, refer patent document 1).
JP-A-2005-72121

  By the way, it is generally known that a method of increasing the thickness of the dielectric layer is effective as a method of improving the withstand voltage characteristics of the multilayer electronic component. Also in the manufacturing method of the multilayer electronic component described above, the withstand voltage characteristics of the manufactured multilayer electronic component can be improved to some extent by increasing the thickness of the prepared green sheet. On the other hand, the inventors of the present application provide a technique for producing a multilayer electronic component in which the withstand voltage characteristics are further improved as compared with a multilayer electronic component in which the thickness of the dielectric layer is simply increased. Newly found.

  That is, an object of the present invention is to provide a method for manufacturing a multilayer electronic component that can further improve the withstand voltage characteristics.

  In the method for manufacturing a multilayer electronic component according to the present invention, a first sheet in which an arrangement area where an electrode pattern is arranged on a green sheet and a non-arrangement area where no electrode pattern is arranged are formed in a predetermined arrangement pattern, A sheet forming step of forming a second sheet in which an arrangement region and a non-arrangement region are formed in an arrangement pattern different from that of the first sheet on the sheet; and a plurality of layers of the first sheet and the second sheet are laminated. A laminated body forming step for forming the sheet laminated body and a firing step for firing the sheet laminated body. In the laminated body forming step, an arrangement area of the first sheet and a non-arrangement area of the second sheet are provided. The first sheet and the second sheet are stacked such that the first sheet non-arrangement area and the second sheet arrangement area overlap each other in the lamination direction. It is.

  In this method for manufacturing a laminated electronic component, in the laminated body forming step, the first sheet placement area and the second sheet non-placement area overlap each other in the stacking direction, and the first sheet non-placement area. Then, the first sheet and the second sheet are stacked so that the arrangement area of the second sheet overlaps with the stacking direction. Accordingly, when the produced sheet laminate is viewed from the cross-sectional direction, at least two green sheets are interposed between the electrode patterns of the first sheet, and at least between the electrode patterns of the second seed. Two layers of green sheets intervene. For this reason, the thickness of the green sheet between electrode patterns can be increased substantially, and sufficient withstand voltage characteristics can be ensured. Also, by interposing multiple layers of green sheets between the electrode patterns, even if defects such as cracks or chips occur in the green sheets, the defects do not increase beyond the sheet interface, and the upper and lower green sheets The probability that a defect will occur at the same position in is also kept very low. Therefore, in this method for manufacturing a multilayer electronic component, it is possible to further improve the withstand voltage characteristics of the manufactured multilayer electronic component.

  In addition, a sheet condition determining step for determining the interlayer thickness between the electrode patterns in the stacking direction of the sheet laminate and the number of green sheets interposed between the electrode patterns based on desired withstand voltage characteristics is further provided. Is preferred. By selecting the optimum interlayer thickness and the number of sheets based on the desired withstand voltage characteristics in the sheet condition determining step, it is possible to efficiently produce a multilayer electronic component having such desired withstand voltage characteristics.

  Further, in the sheet forming step, the green sheets of the first sheet and the second sheet are respectively formed on the flexible film, and each green sheet is enclosed so as to surround the placement area and the non-placement area. It is preferable to form a dummy electrode pattern thereon. In this case, the thickness and strength of the first sheet and the second sheet around the placement area and the non-placement area can be increased by the dummy electrode pattern. Thereby, when laminating the first sheet and the second sheet in the laminate forming step, it is possible to easily peel the flexible film from the first sheet and the second sheet. Become. Moreover, the generation | occurrence | production of the tear in the sheet | seat peripheral part at the time of peeling a film can also be suppressed.

  According to the method for manufacturing a multilayer electronic component according to the present invention, the withstand voltage characteristics can be further improved.

  Hereinafter, a preferred embodiment of a method for manufacturing a multilayer electronic component according to the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a cross-sectional view showing a configuration of a ceramic capacitor manufactured by using a multilayer electronic component manufacturing method according to an embodiment of the present invention. As shown in FIG. 1, the ceramic capacitor 1 includes an element portion 2 having a substantially rectangular parallelepiped shape, and a pair of terminal electrodes 3 and 3 formed at both ends in the longitudinal direction of the element portion 2.

  The element unit 2 includes dielectric layers 4 and internal electrode layers 5, and the dielectric layers 4 and the internal electrode layers 5 are alternately stacked. In addition, dielectric layers 4 on which the internal electrode layer 5 is not formed are laminated as protective layers at both ends of the element unit 2 in the lamination direction. Although simplified in FIG. 1, the dielectric layer 4 and the internal electrode layer 5 are actually laminated by about 300 layers.

  The internal electrode layers 5 and 5 adjacent to each other in the upper and lower sides face each other with a certain area and are electrically insulated from each other by the dielectric layer 4. One end of each of the internal electrode layers 5 and 5 is separated from one of the different terminal electrodes 3 and 3 with a predetermined gap L. The other ends of the internal electrode layers 5 and 5 extend to the end of the dielectric layer 4 and are electrically connected to the other terminal electrodes 3 and 3 different from each other. Therefore, when a predetermined voltage is applied to the terminal electrodes 3, 3, charges proportional to the facing area are stored between the internal electrode layers 5, 5 facing vertically.

  Then, the manufacturing method of the ceramic capacitor 1 mentioned above is demonstrated. This method for manufacturing a ceramic capacitor mainly includes four steps of a sheet condition determining step, a sheet forming step, a laminate forming step, and a firing step.

[Sheet condition determination process]
In the sheet condition determining step, the condition of the dielectric layer 4 interposed between the internal electrode layers 5 and 5 is determined based on a desired withstand voltage characteristic in the ceramic capacitor 1. More specifically, the interlayer thickness of the electrode patterns 20 and 20 in the stacking direction in the sheet stack 25 described later and the number of green sheets 14 interposed between the electrode patterns 20 and 20 are determined (FIG. 5A). reference). The following formula (1) is used to determine the sheet condition.
T = t ₁ + t ₂ +... + T _n (1)

In the formula (1), T is a layer interval between the electrode patterns 20 and 20 required for obtaining a desired withstand voltage characteristic in the ceramic capacitor 1. Further, n is the number of the green sheets 14 interposed between the electrode patterns 20 and 20 in order to ensure the thickness of the green sheet 14, and t _n is the thickness of each green sheet 14.

Figure 2 illustrates the interlayer thickness T for the withstand voltage characteristics of the ceramic capacitor _1, and an example of setting the number of sheets n. In the example shown in FIG. 2, when the withstand voltage is 6.3V, T = 2.8 μm and n = 2 sheets, and when the withstand voltage is 25V, T = 4.2 μm, n = 3. When the withstand voltage is 50V, T = 5.6 μm and n = 4 sheets, and when the withstand voltage is 100V, T = 7.0 μm and n = 5 sheets. Yes. In the present embodiment, the following description will be made on the case where the withstand voltage is 6.3V.

[Sheet formation process]
In the sheet forming step, first, as shown in FIG. 3, for example, by using a doctor blade device 10, a long carrier film 11 (flexible film) conveyed by a feeding roller and a take-up roller (not shown). A slurry 12 containing ceramic powder is applied to the surface of the film. As a result, an undried ceramic green sheet 13 is formed on the surface of the carrier film 11. Then, the ceramic green sheet 13 on the carrier film 11 is dried by a predetermined drying process to form a green sheet 14 having a thickness of about 1.4 μm.

  After forming the green sheet 14, for example, a conductive paste mainly containing Ag is screen-printed. Thereby, the arrangement | positioning area | region where the electrode pattern 20 is arrange | positioned, and the non-arrangement area | region where an electrode pattern is not arrange | positioned are formed in the surface of the green sheet 14. FIG. As the types of arrangement patterns of the electrode patterns 20 to be formed, n types of patterns are prepared according to the number of sheets n determined in the sheet condition determining step. In the present embodiment, since the number n of sheets is 2, as shown in FIGS. 4A and 4B, two types of green sheets (first sheets) having different arrangement patterns of the arrangement area and the non-arrangement area are provided. Sheet) 14A and green sheet (second sheet) 14B are formed.

  On the surface of the green sheet 14A, as shown in FIG. 4A, rectangular electrode patterns 20 are formed in a matrix of 5 rows × 5 columns. Each column of the electrode pattern 20 is in a state of being separated from the column of adjacent electrode patterns 20 with an interval d1 wider than the width of the electrode pattern 20. Thereby, the area | region along each row | line | column of the electrode pattern 20 becomes the arrangement | positioning area | region 30A, Between the row | line | columns of the adjacent electrode pattern 20 becomes the non-arrangement area | region 40A where the electrode pattern 20 is not arrange | positioned.

  On the other hand, a rectangular electrode pattern 20 is formed on the surface of the green sheet 14B in a matrix of 5 rows × 4 columns as shown in FIG. 4B. In addition, a region where the electrode pattern 20 is not formed is provided between the columns of the adjacent electrode patterns 20 and a region outside the both end columns of the electrode pattern 20 with a distance d1 wider than the width of the electrode pattern 20. It has been. The arrangement pattern of the arrangement area 30B and the non-arrangement area 40B of the electrode pattern 20 in the green sheet 14B is inverted with respect to the arrangement pattern of the arrangement area 30A and the non-arrangement area 40A of the electrode pattern 20 in the green sheet 14A. ing.

  Therefore, when the arrangement relationship between the arrangement region 30A and non-arrangement region 40A of the electrode pattern 20 in the green sheet 14A and the arrangement region 30B and non-arrangement region 40B of the electrode pattern 20 in the green sheet 14B is compared, the arrangement region of the green sheet 14A 30A corresponds to the non-arrangement area 40B of the green sheet 14B, and the arrangement area 30B of the green sheet 14B and the non-arrangement area 40A of the green sheet 14A correspond to each other.

  Also, dummy electrode patterns 21 are formed on the surfaces of the green sheet 14A and the green sheet 14B by screen printing a conductive paste similar to the electrode pattern 20, respectively. The arrangement pattern of the dummy electrode patterns 21 is, for example, a rectangular and annular pattern in which one side is constituted by the four dummy electrode patterns 21. And the dummy electrode pattern 21 is arrange | positioned so that the arrangement | positioning area | regions 30A and 40A and the non-arrangement area | regions 30B and 40B of the electrode pattern 20 may be enclosed, respectively. In addition, an alignment marking (not shown) is formed outside the dummy electrode pattern 21.

  After forming the electrode pattern 20, the dummy electrode pattern 21, and the marking, using the blade cutter or the like, the arrangement regions 30 </ b> A and 40 </ b> A, the non-arrangement regions 30 </ b> B and 40 </ b> B, and the cutting line 23 at the outer edge of the dummy electrode pattern 21 are Then, the green sheet 14 is cut into a rectangle. Thereby, the green sheet 14A and the green sheet 14B are cut out from the green sheet 14.

[Laminated body forming step]
In the laminated body forming step, as shown in FIG. 5A, the carrier film 11 is peeled off from each of the cut green sheet 14A and the green sheet 14B, and the green sheet 14B is placed on the green sheet 14A while performing alignment by marking. Laminate. Accordingly, when the stacked green sheets 14A and 14B are viewed in a cross section orthogonal to the Y direction in FIG. 4, the arrangement area 30A of the electrode pattern 20 in the green sheet 14A and the non-arrangement area of the electrode pattern 20 in the green sheet 14B. 40B overlaps in the stacking direction, and the arrangement region 30B of the electrode pattern 20 in the green sheet 14B and the non-arrangement region 40A of the electrode pattern 20 in the green sheet 14A overlap in the stacking direction.

  After the lamination of the first set of green sheets 14A and 14B is completed, the second set of green sheets 14A and 14B is laminated. At this time, the marking positions of the second set of green sheets 14A and 14B and the marking positions of the first set of green sheets 14A and 14B are equivalent to the gap L (see FIG. 1) in the Y direction in FIG. The second set of green sheets 14A and 14B is stacked on the first set of green sheets 14A and 14B so as to be offset.

  Thereafter, the green sheet 14A and the green sheet 14B are alternately laminated by repeating the same procedure, and finally the green sheet 14 in which the electrode pattern 20 is not formed on both end faces in the lamination direction of the green sheet 14 is used as a protective layer. When two layers are laminated, a sheet laminate 25 is formed as shown in FIG.

[Baking process]
In the firing step, the sheet laminate 25 obtained in the laminate formation step is pressure-bonded by a press or the like, and then chipped into a predetermined size, and degreased and fired at a predetermined temperature. Thereby, the element part 2 is formed. Thereafter, a conductor paste is applied and baked on both ends of the element portion 2 to form the terminal electrodes 3 and 3, thereby completing the ceramic capacitor 1 shown in FIG.

  As described above, in this multilayer electronic component manufacturing method, in the laminated body forming step, the arrangement region 30A of the electrode pattern 20 in the green sheet 14A and the non-arrangement region 40B of the electrode pattern 20 in the green sheet 14B are laminated. The green sheet 14A and the green sheet 14B so that the non-arrangement region 30B of the electrode pattern 20 in the green sheet 14A and the arrangement region 40A of the electrode pattern 20 in the green sheet 14B overlap in the stacking direction. Laminate.

  Therefore, when the produced sheet laminate 25 is viewed from the cross-sectional direction, the two layers of the green sheet 14 are interposed between the electrode patterns 20 and 20, and the green sheet 14 between the electrode patterns 20 and 20 is substantially interposed. Increases in thickness. Moreover, even if a defect such as a crack or a chip occurs in the green sheet 14 by interposing a plurality of layers of the green sheet 14 between the electrode patterns 20 and 20, the defect does not increase beyond the sheet interface. In addition, the probability that a defect occurs at the same position in the upper and lower green sheets 14 and 14 can be suppressed to an extremely low level. Therefore, in this method for manufacturing a multilayer electronic component, the withstand voltage characteristics of the manufactured ceramic capacitor 1 can be further improved.

  Further, in this multilayer electronic component manufacturing method, the green thickness interposed between the sheet thickness of the green sheet 14 and the electrode patterns 20 and 20 located at the same position when viewed from the stacking direction is based on desired withstand voltage characteristics. The number of sheets 14 is determined. Thus, by selecting the optimum sheet thickness and number of sheets based on the desired withstand voltage characteristics, the ceramic capacitor 1 having such desired withstand voltage characteristics can be efficiently manufactured.

  Furthermore, in this multilayer electronic component manufacturing method, the dummy electrode pattern 21 is formed on each green sheet 14 so as to surround the placement areas 30A and 40A and the non-placement areas 30B and 40B in the sheet forming step. . Therefore, the dummy electrode pattern 21 can increase the thickness and strength of the green sheet 14A and the green sheet 14B around the arrangement regions 30A and 40A and the non-arrangement regions 30B and 40B. Thereby, when laminating | stacking the green sheet 14A and the green sheet 14B in a laminated body formation process, it becomes possible to peel the carrier film 11 from the green sheet 14A and the green sheet 14B easily. Further, when the carrier film 11 is easily peeled off, the occurrence of tearing at the peripheral edge of the sheet when the carrier film 11 is peeled is suppressed, and even if tearing occurs, the placement regions 30A and 40A and the non-placement region 30B , 40B is also prevented from reaching the tear. Such a dummy electrode pattern 21 is not limited to the rectangular and annular pattern as shown in FIG. 4, for example, only in a direction parallel to the column direction of the arrangement regions 30A and 40A and the non-arrangement regions 30B and 40B. You may make it form.

  The present invention is not limited to the above embodiment. For example, various modifications can be applied to the arrangement pattern of the electrode patterns 20 formed on the green sheet 14 in the sheet forming process. For example, as shown in FIG. 6A, the electrode pattern 20 is formed in a substantially checkered pattern, and the arrangement region 30C and the non-arrangement region 40C of the electrode pattern 20 are alternately positioned in the row direction and the column direction. As shown in FIG. 6B, a green sheet 14C having an arrangement area 30D and a non-arrangement area 40D obtained by inverting the arrangement pattern with respect to the green sheet 14C may be formed.

  In the above-described embodiment, when the second set of green sheets 14A and 14B is stacked on the first set of green sheets 14A and 14B, the stacking position of the second set of green sheets 14A and 14B is indicated by Y in FIG. The sheet is offset by the gap L, but in the sheet forming process, the green sheet 14A, 14B is formed by offsetting the electrode pattern 20 formation position in the Y direction in advance in the Y direction with respect to the electrode pattern 20 of the green sheet 14A, 14B. (Not shown) may be formed, and the green sheets may be stacked without offsetting the stacking position in the stack forming step.

It is sectional drawing which shows the structure of the ceramic capacitor manufactured using the manufacturing method of the multilayer electronic component which concerns on one Embodiment of this invention. It is a figure which shows the example of a setting of sheet | seat conditions. It is a figure which shows the manufacturing process of a ceramic green sheet. It is the figure which showed the arrangement pattern of the arrangement | positioning area | region and non-arrangement area | region of the electrode pattern in a green sheet. It is a figure which shows the manufacturing process of a sheet laminated body. It is the figure which showed the modification of the arrangement pattern of the arrangement | positioning area | region of the electrode pattern in a green sheet, and a non-arrangement | positioning area | region.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Ceramic capacitor (laminated type electronic component), 11 ... Carrier film (flexible film), 14 ... Green sheet, 14A, 14C ... Green sheet (first sheet), 14B, 14D ... Green sheet (first 2), 20 ... electrode pattern, 21 ... dummy electrode pattern, 25 ... sheet laminate, 30A-30D ... arrangement region, 40A-40D ... non-arrangement region.

Claims (3)

A first sheet in which an arrangement area in which an electrode pattern is arranged on a green sheet and a non-arrangement area in which the electrode pattern is not arranged is formed in a predetermined arrangement pattern, and an arrangement pattern different from the first sheet on a green sheet A sheet forming step of forming a second sheet in which the placement area and the non-placement area are formed;
A laminate forming step of forming a sheet laminate by laminating a plurality of layers of the first sheet and the second sheet;
A firing step of firing the sheet laminate,
In the laminated body forming step, the arrangement region of the first sheet and the non-arrangement region of the second sheet overlap in the lamination direction, and the non-arrangement region of the first sheet, A method of manufacturing a multilayer electronic component, comprising: stacking the first sheet and the second sheet so that the arrangement region of the second sheet overlaps in the stacking direction.   A sheet condition determining step of determining an interlayer thickness between the electrode patterns in the stacking direction of the sheet laminate and a number of sheets of the green sheet interposed between the electrode patterns based on desired withstand voltage characteristics; The method for manufacturing a multilayer electronic component according to claim 1, wherein:   In the sheet forming step, the green sheets of the first sheet and the second sheet are respectively formed on a flexible film, and each of the green sheets is surrounded by the placement area and the non-placement area. 3. The method of manufacturing a multilayer electronic component according to claim 1, wherein the dummy electrode pattern is formed on a green sheet.

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