JPH11204369A - Multiply-connected stacked ceramic capacitor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce stray capacitance between adjacent stacked ceramic capacitors, in a case where a plurality of stacked ceramic capacitors are formed in the same element assembly. SOLUTION: In a multiply-connected sacked ceramic capacitor, having a plurality of stacked ceramic capacitors 10a, 10b, 10c and 10d formed at a predetermined spacing in the lateral direction inside a single element assembly, the stacked ceramic capacitors 10a, 10b, 10c and 10d are formed on the upper and lower sides via an intermediate reactive layer 4. At the same time, inner electrodes 3 which constitute the stacked ceramic capacitors 10a and 10c on the lower side and inner electrodes 3 for constituting the stacked ceramic capacitors 10b and 10d on the upper side are laterally shifted from each other, so that the stacked ceramic capacitors do not vertically overlap each other.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer ceramic capacitor (hereinafter, referred to as a capacitor array) in which a plurality of multilayer ceramic capacitors (hereinafter, referred to as multilayer capacitors) are formed in a single element.

[0002]

2. Description of the Related Art A conventional method for manufacturing a capacitor array will be described with reference to the drawings.

FIG. 6 is a view showing a conventional green laminate of a capacitor array, FIG. 7 is a development view thereof, FIG. 8 is a view showing a sintered body, and FIG. 9 is a view showing a completed product. 6 to 9, 21 is a green laminate, 22 is a dielectric layer, 23 is an internal electrode, 24 is an ineffective layer, 25a to 25d are multilayer capacitors, 26 is a sintered body, 27 is an external electrode, and 28 is a capacitor. The completed array is shown.

First, a green sheet for the dielectric layer 22 is prepared by using a known method for manufacturing a multilayer capacitor.

Next, a plurality of green sheets are laminated to form an ineffective layer 24. Next, the first-layer internal electrodes 23 shown in FIG. 7 are printed on the green sheet surface, and laminated on the invalid layer 24 surface. Subsequently, a green sheet on which the second-layer internal electrode 23 that forms a pair with the first-layer internal electrode 23 via the dielectric layer 22 is laminated thereon. Further, a green sheet on which the internal electrodes 23 are printed in the same manner as the first layer, and a green sheet on which the internal electrodes 23 are printed in the same manner as the second layer are sequentially laminated thereon, and finally, Invalid layer 2
4 are stacked under pressure to form a laminate green block.

[0006] The green block thus formed is cut into a predetermined shape to form a green laminate 21 of a quadruple capacitor array shown in FIG.

Next, the green laminate 21 is fired at a predetermined temperature to form a sintered body 26. Next, barrel polishing of the sintered body 26 is performed to expose the group of internal electrodes 23 of the multilayer capacitors 25a to 25d formed inside the sintered body 26 to the side surfaces thereof. Thereafter, the external electrodes 27 are formed so as to cover the internal electrodes 23 exposed on the side surfaces, and the capacitor array 28 including the multilayer capacitor elements 25a to 25d as shown in FIG. 9 is manufactured.

[0008]

However, the conventional capacitor array 28 has the disadvantage that the adjacent multilayer capacitor elements 25
There is a problem that stray capacitance is generated between a to 25d.

An object of the present invention is to solve the above-mentioned conventional problems and to provide a method for manufacturing a highly reliable capacitor array having a small stray capacitance between adjacent multilayer capacitors.

[0010]

SUMMARY OF THE INVENTION In order to achieve the above-mentioned object, the present invention provides a method of stacking a plurality of multilayer capacitors at predetermined intervals in a horizontal direction inside a single element body with an intermediate invalid layer interposed therebetween. At the same time, the internal electrodes forming the lower-layer multilayer capacitor and the internal electrodes forming the upper-layer multilayer capacitor were shifted in the horizontal direction so as not to overlap each other in the vertical direction, thereby being formed inside the element body. This is to increase the spacing between the multilayer capacitors and reduce the stray capacitance between adjacent multilayer capacitors.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is directed to a multi-layer type multilayer ceramic capacitor having a plurality of multilayer ceramic capacitors formed at predetermined intervals in a horizontal direction inside a single element body. In addition to being superimposed vertically through the intermediate invalid layer, the internal electrodes forming the lower-layer multilayer ceramic capacitor and the internal electrodes forming the upper-layer multilayer ceramic capacitor are shifted laterally so that they do not overlap each other in the vertical direction. The multi-layered multilayer ceramic capacitor is characterized in that the interval between the horizontally adjacent multilayer capacitors is widened, and the vertically adjacent multilayer capacitors have an internal electrode through an intermediate invalid layer. Since the capacitors are arranged so as not to overlap, the stray capacitance between the multilayer capacitors can be reduced.

The invention according to claim 2 of the present invention is characterized in that the intermediate ineffective layer is formed of a dielectric material having a lower dielectric constant than the dielectric layer constituting the multilayer ceramic capacitor. The multi-layered multilayer ceramic capacitor according to the above, whereby the interval between adjacent multilayer capacitors in the vertical direction is narrower than the interval between adjacent multilayer capacitors in the horizontal direction, but the dielectric constant of the intermediate invalid layer is low. The stray capacitance between matching multilayer capacitors can be reduced.

Hereinafter, a method for manufacturing a capacitor array according to an embodiment of the present invention will be described with reference to the drawings.

FIGS. 1 to 5 show a capacitor array according to the present invention. 1 and 5 are green laminates, FIG. 2 is a development view of the green laminate, FIG. 3 is a sintered body, and FIG. 4 is a view showing a finished product. 1 to 5, 1 is a green laminate,
2 is a dielectric layer, 3 is an internal electrode, 4 is an intermediate invalid layer, 5 is an upper invalid layer, 6 is a lower invalid layer, 7 is a sintered body, 8 is an external electrode, 9 is a finished product, and 10a to 10d are laminated. It is a capacitor.

First, a green sheet for the dielectric layer 2 is prepared by using a known multilayer capacitor manufacturing method.

Next, a plurality of the prepared green sheets are laminated to form an upper invalid layer 5, a lower invalid layer 6, and an intermediate invalid layer 4. A green sheet on which the first-layer internal electrode 3 shown in FIG. 2 is printed is laminated on the lower inactive layer 6 thus prepared. Subsequently, a green sheet on which a second-layer internal electrode 3 to be paired with the first-layer internal electrode 3 is printed via the dielectric layer 2 is laminated thereon. Further, a predetermined number of the green sheets on which the internal electrodes 3 are printed in the same manner as the first layer and the green sheets on which the internal electrodes 3 are printed in the same manner as the second layer are alternately stacked thereon. The intermediate invalid layer 4 is laminated to form lower-layer laminated capacitors 10a and 10c.

Next, the upper-stage multilayer capacitor 10b, 1
For 0d, a green sheet on which the internal electrode 3 is printed on the surface of the intermediate invalid layer 4 in the same manner as the first layer, and a green sheet on which the internal electrode 3 is printed in the same manner as the second layer are sequentially and alternately predetermined. After lamination, the upper ineffective layer 5 was finally laminated to form a green laminate block. At this time, the internal electrodes 3 of the lower multilayer capacitors 10a and 10c are connected to the upper multilayer capacitors 10b and 10
The internal electrodes 3 were stacked in a staggered manner at predetermined intervals so as not to overlap with each other in the vertical direction.

Thereafter, the green laminate block thus produced is cut into the shape of the green laminate 1 shown in FIG. 1 and then fired at a predetermined temperature to produce a sintered body 7.

As shown in FIG. 4, external electrodes 8 are formed at the positions of the internal electrodes 3 constituting the multilayer capacitors 10a to 10d, which are exposed on both side surfaces of the obtained sintered body 7, and the multilayer capacitor elements 10a To 10d were completed.

The capacitance thus created is 22
With respect to the capacitor array 9 including four 0 pF multilayer capacitors 10 a to 10 d and the capacitor array 28 including the multilayer capacitors 25 a to 25 d created by the conventional method, ten stray capacitances between adjacent multilayer capacitors are measured. The results are shown in (Table 1).
The number of stacked dielectric layers 2 of the conventional product was the same as that of the present invention, and the lateral length of the sintered body was the same as that of the present invention.

[0021]

[Table 1]

As apparent from Table 1, the average value of the stray capacitance between the multilayer capacitors 25a and 25b, 25b and 25c, and 25c and 25d constituting the conventional capacitor array 28 is 1.23 to 1.24 pF. Whereas
It can be seen that the stray capacitance between the multilayer capacitors 10a and 10b, 10b and 10c, 10c and 10d constituting the capacitor array 9 of the present invention is extremely small, 0.32 to 0.33 pF.

That is, in the product of the present invention, since the multilayer capacitors 10a to 10d constituting the capacitor array 9 are arranged in a staggered manner on the upper and lower sides via the intermediate invalid layer 4, the adjacent multilayer capacitors 10a and 10b , 10b and 10c,
The distance between 10c and 10d is increased. As a result, the stray capacitance decreases.

In this embodiment, the material of the intermediate invalid layer 4 is made of the same composition as the dielectric layer 2. However, by using a material having a dielectric constant lower than that of the dielectric layer 2, the multilayer capacitor 10a can be formed. And 10b, 10b and 10c, 10c and 10
The stray capacitance between d can be reduced. Fig. 5
A method of forming two intermediate invalid layers 4 as shown in FIG.

[0025]

As described above, according to the present invention, each of the multilayer capacitors constituting the capacitor array is divided into an upper stage and a lower stage via an intermediate invalid layer, and furthermore, the internal components constituting each multilayer capacitor in the vertical direction are formed. By preventing the electrodes from overlapping each other, it becomes possible to reduce the stray capacitance between adjacent multilayer capacitors.

[Brief description of the drawings]

FIG. 1 is a perspective view of a capacitor array according to an embodiment of the present invention.

[Fig. 2]

FIG. 3 is a perspective view of the same.

FIG. 4 is a perspective view of the finished product.

FIG. 5 is a perspective view of another embodiment of the present invention.

FIG. 6 is a perspective view of a conventional capacitor array.

FIG. 7 is an expanded view of the same.

FIG. 8 is a perspective view of the same.

FIG. 9 is a perspective view of the finished product.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Green laminated body 2 Dielectric layer 3 Internal electrode 4 Intermediate invalid layer 5 Upper invalid layer 6 Lower invalid layer 7 Sintered body 8 External electrode 9 Finished product 10a, 10b, 10c, 10d Multilayer capacitor

Claims (2)

[Claims] 1. A multilayer ceramic capacitor having a plurality of multilayer ceramic capacitors formed at predetermined intervals in a horizontal direction inside a single element body and vertically stacked through an intermediate ineffective layer, and a lower-stage multilayer ceramic capacitor is formed. A multi-layer type multilayer ceramic capacitor, wherein an internal electrode forming a multilayer ceramic capacitor and an internal electrode forming an upper stage multilayer ceramic capacitor are shifted laterally so as not to overlap each other in a vertical direction. 2. The multi-layer monolithic ceramic capacitor according to claim 1, wherein the intermediate invalid layer is formed of a dielectric material having a dielectric constant lower than that of the dielectric layer forming the monolithic ceramic capacitor.