JP2008008811A - Method and device for detecting jitter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an improved jitter detection device capable of detecting jitter. <P>SOLUTION: The jitter detection device is equipped with a reception circuit 1 for receiving a signal, a determination circuit 3 for determining a signal portion used for jitter detection in the received signal based on a signal amplitude, and a jitter detection circuit 5 for detecting jitter on the signal based on the determined signal portion. The determination circuit 3 includes the first threshold setting circuit for generating the first threshold, the second threshold setting circuit for generating the second threshold, and a period signal generation circuit for generating a period signal by using the first and second thresholds, and the jitter detection circuit 5 includes a signal portion detection circuit for detecting the signal portion by responding to the received signal following the period signal. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method and apparatus for detecting jitter in a signal.

Conventionally, data recorded on an optical disc such as a CD or DVD is read out by binarizing a reproduction signal from the optical disc and detecting the length of each mark or space in the digital signal obtained by the binarization. (Patent Document 1). For binarization for data reading, for example, for a reproduction signal from the conventional DVD shown in FIG. 1B, an intermediate value of the peak of the reproduction signal is usually used as the slice level. In addition, the detection of jitter in the digital signal from the optical disc detected in this way is also performed using the same slice level as the data detection. That is, for example, a reproduction signal from a DVD is binarized using a slice level that is an intermediate value of the peak peak of the reproduction signal, and the length of each mark / space in the digital signal after binarization is detected. Jitter is measured by examining variations in depth. For example, in the case of DVD, there are marks / spaces having a period from 3T to 11T and 14T. Here, T is equal to one period of the clock used for the DVD. Thus, the quality of the optical disk itself is checked by measuring the jitter in the signal from the optical disk, or the optical axis of the light beam in the optical pickup is adjusted.
JP 2004-295965 A

Recently, a new optical disc standard such as HD (High-Definition) DVD has appeared as an optical disc. Such an optical disc has a higher recording density than a conventional DVD. For example, in HD DVD, ETM code (Eight to Twelve Modulation Code) is used, and the reproduced signal from now on has a waveform as shown in FIG. As can be seen from comparison with the playback signal from the DVD using the conventional EFM code of FIG. 1B, there are some components with smaller signal amplitude, and the component with the smallest amplitude peaks near the slice level. have. This is because if the recording density increases, the signal amplitude decreases due to intersymbol interference, and if the linear density further increases, the signal amplitude decreases. For example, with the shortest 2T mark or space length, the signal amplitude peak p is near the slice level. When data is read from an optical disc that generates such a reproduction signal, the binarization method using the same slice level as in the prior art generates many identification errors near the slice level even with a little noise, so stable data detection is possible. Have difficulty. Therefore, the HD DVD standard stipulates that a PRML (Partial Response and Maximum Likelihood) signal processing method is used as a data reading method. Along with this, the reproduction signal evaluation method is evaluated not by jitter but by SbER (Simulated Bit Error Rate) and PRSNR (Partial Response Signal to Noise) defined in the standard.
However, such a method of evaluating with SbER and PRSNR requires a larger number of samples than jitter measurement, and therefore has a lower real-time property than a method using a conventional slice level. For this reason, at the production site of optical disc-related products, adjustment work such as the optical axis adjustment step of the optical pickup is necessary, but in such adjustment work, there is a certain level of evaluation in SbER or PRSNR for each fine adjustment. Therefore, there is a problem that the adjustment takes time. This also causes a problem that the production efficiency of the entire product is lowered.

Accordingly, it is an object of the present invention to provide an improved jitter detection method and apparatus.
Another object of the present invention is to provide a jitter measurement method using the above-described jitter detection method or an electronic apparatus using the jitter detection device.

  Other objects of the present invention will become apparent from the following detailed description of embodiments of the present invention.

  According to one embodiment of the present invention, a jitter detection method includes a step of receiving a signal, a determination step of determining a signal portion to be used for jitter detection in the received signal based on a signal amplitude, And a jitter detection step of detecting jitter in the signal based on the determined signal portion.

  According to one embodiment of the present invention, a jitter detection apparatus includes a reception circuit that receives a signal, and a determination circuit that determines a signal portion used for jitter detection in the received signal based on a signal amplitude. And a jitter detection circuit that detects jitter related to the signal based on the determined signal portion.

  According to one embodiment of the present invention, jitter detection can be performed at a speed and accuracy sufficient for practical use even from a reproduction signal from a high-density optical disk such as HD DVD. Also, according to one embodiment of the present invention, jitter detection can be performed with a simple configuration. Furthermore, according to an embodiment of the present invention, it is possible to speed up the adjustment work related to jitter, which is necessary at the production site of optical disc related products such as HD DVD.

Next, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 2 is a block diagram showing a configuration of the jitter detection apparatus according to one embodiment of the present invention. As shown in the figure, this jitter detection apparatus includes a reception circuit 1, a signal portion determination circuit 3, and a jitter detection circuit 5. In detail, the receiving circuit 1 receives a signal from an information recording medium such as an optical disc or a communication medium such as a communication line or network at an input terminal, and performs necessary processing (for example, automatic gain control ( AGC) and equalization processing are performed, and then output to the output terminal. The signal portion determination circuit 3 has an input for receiving a reception signal supplied from the output of the reception circuit 1, and determines a signal portion of the reception signal used for jitter detection based on the signal amplitude. The determination result is generated in the output. The jitter detection circuit 5 has an input for receiving a reception signal supplied from the output of the reception circuit 1 and an input for receiving a determination result supplied from the output of the signal portion determination circuit 3. As a result, the jitter detection circuit 5 detects jitter related to the received signal based on the determined signal portion.

  More specifically, the signal portion determination circuit 3 includes an upper threshold value setting circuit that generates an upper threshold value THU that is a first threshold value, and a lower threshold value THL that is a second threshold value. And a period signal generation circuit that generates a period signal using the upper and lower thresholds. At this time, the jitter detection circuit 5 can be configured to include a signal portion detection circuit that detects a signal portion by responding to the received signal in accordance with the period signal.

  Here, with reference to FIG. 3, the upper threshold value THU and the lower threshold value THL will be described. For example, assuming that the received signal is a playback signal from HD DVD, the playback signal has a waveform as shown in FIG. 3, for example. At this time, if the intermediate value of the peak peaks of the reproduction signal is set to zero level, the reproduction signal includes signal components c1 to c13 having positive or negative peaks. Here, in the illustrated waveform example, the component having the largest positive or negative peak is c1, c2, c5, c13, and the component having the next lowest peak is c8, and the component having the lower peak. Are c4, c11, and the components having the smallest peak are c3, c6, c7, c9, c10, c12.

  In such a case, assuming that the illustrated zero level is binarized as a slice level, the component having the minimum peak has a very high probability that an identification error will occur at c3, c6, c7, c9, c10, and c12. Furthermore, the probability of discriminating errors between components adjacent to these minimum peak components also increases. For example, considering the component c3, the mark / space length identification error that occurs in the component c3 directly affects the data length in the adjacent components C2 and C4, and therefore the probability of the identification error increases. Therefore, in the jitter detection apparatus according to the embodiment of the present invention, signal jitter detection is performed based only on a signal portion where the probability of occurrence of mark / space length identification errors is not high. For this reason, a part with a high probability of occurrence of an identification error and a part with no probability are identified based on the signal amplitude. As an example, the upper threshold value THU and the lower threshold value THL are determined with respect to the zero level to determine a signal portion where the probability of occurrence of an identification error is not high, and zero as in the conventional jitter detection method. A technique of detecting jitter by binarizing the level as a slice level is adopted. As a result, the same high speed as the conventional jitter detection method can be realized.

  Here, how to set the upper threshold value THU and the lower threshold value THL will be described in more detail. For example, if these threshold values are set at the positions of the dotted lines in the figure, in this case, the components c3, c6, c7, c9, c10, and c12 of the minimum peak can be distinguished from the other components. If the upper threshold value THU is set to positions THU ′ and THL ′ shown by the alternate long and short dash line, a signal portion including the minimum peak component and components c4 and c11 having the next lowest peak, and other portions, Can be identified. In the example of a playback signal from an HD DVD, when only the 2T shortest mark / space length component is excluded from the determination target, those threshold values are larger than the peak of the 2T component but the next long 3T component. A level smaller than the peak, for example, a level such as THU and THL is set. Also, when it is desired to exclude not only 2T but also 3T or longer period components such as 5T, the threshold value is higher than the 5T peak but smaller than the 6T component peak, such as THU 'and THL'. Set to level. As described above, the magnitudes of the upper threshold value and the lower threshold value can be set to a predetermined value or can be continuously variable according to the periodic component to be excluded from the determination target.

  Next, with reference to FIG. 4 and FIG. 5, the principle of the method for determining the signal portion used for jitter detection will be described using an HD DVD playback signal as an example. In this example, a threshold is set for the purpose of excluding the 2T shortest signal component. In these figures, the encoded signal (data recorded on the optical disc) is displayed at the top, the waveform of the reproduction signal from the optical disc below it, and the waveform of the signal related to the threshold used for the determination. Show. First, (a) of FIG. 4 shows an example of “clear crossing” in which the reproduction signal clearly crosses the slice level from the positive side, and (b-1) and (c-1) indicate the slice level. An example of “non-clear crossing” that crosses non-clear from the positive side is shown. Further, examples of crossing slice levels from the negative side are shown in (b-2) and (c-2) of FIG. “Clear intersection” or “clear intersection” means that the above-mentioned identification error occurrence probability is not high, and “non-clear intersection” or “non-clear intersection” means an identification error. This is used to indicate an intersection when the probability of occurrence is high.

  First, referring to FIG. 4A, when components having a period longer than 2T continue, for example, the slice level is clearly crossed from the positive side to the negative side at time t2, and a clear crossing point cr1 is generated. In this case, the probability of occurrence of identification errors at positions that cross the slice level is low. Here, the “upper threshold crossing” signal rises when the reproduction signal crosses the upper threshold THU when the reproduction signal changes from the zero level to the positive side, and changes from the positive side to the zero level side. Suppose that it falls when it crosses the threshold. On the other hand, the “lower threshold crossing” signal rises when the reproduction signal crosses the lower threshold THL when the reproduction signal changes from zero level to a more negative side, and changes from the negative side to the zero level side. Suppose that it falls when it crosses the threshold. The “upper mask” signal is a signal for excluding a signal portion having a high identification error occurrence probability, and is generated mainly based on the upper threshold value, while the “lower mask” signal is Similarly, a signal for excluding a signal portion having a high identification error occurrence probability, and a signal generated mainly based on the lower threshold value. In the case of the clear crossing in FIG. 4A, the lower threshold value on the opposite side is crossed at a certain time from the time point t1 when the reproduction signal crosses the upper threshold value, for example, at the time point t3 within 2T. . In this case, since the probability of occurrence of an identification error is not high, it is not necessary to generate both the upper and lower masks, so that it remains low.

  On the other hand, as shown in FIG. 4 (b-1), when one 2T component follows a periodic component longer than 2T, the reproduction signal passes the upper threshold from the positive side, but crosses the slice level. Later, a non-clear crossing occurs that turns back in the vicinity and returns to the positive side without reaching the lower threshold value. That is, the non-clear intersections cr2 and cr3 are continuous. In this case, since it enters the slice level from the positive side and exits to the positive side, it is called a “return type” non-clear intersection. At this time, the lower threshold crossing signal does not become high within 2T from the time when the upper threshold crossing signal becomes low. In this case, a portion with a high identification error occurrence probability has occurred, and the upper mask signal rises high to start the mask signal because it enters from the upper side with respect to the slice level. In this manner, the clear threshold crossing of (a) and the non-clear crossing of (b-1) can be distinguished depending on whether the lower threshold crossing signal becomes high within the 2T time. FIG. 4B-1 shows the case of one 2T component, but the same applies to other cases where an odd number of 2T components are continued.

  On the other hand, as shown in (c-1) of FIG. 4, when two 2T components follow a periodic component longer than 2T, the reproduction signal passes the upper threshold value from the positive side, and the slice level A non-clear intersection occurs in which the lower threshold value is passed after repeating the slice level intersection by changing in the vicinity. That is, non-clear intersections cr4, cr5, cr6, cr7 are continuous. In this case, since the slice level is entered from the positive side and exits to the negative side, it is called a “non-return type” non-clear intersection. At this time, the lower threshold crossing signal does not go high within 2T from the time when the upper threshold crossing signal goes low, and goes high after the elapse of 2T. In this case as well, there is a portion where the probability of occurrence of discrimination error is high, and the upper mask signal rises high to start the mask signal because it enters from the upper side with respect to the slice level. Thus, the clear threshold crossing of (a) and the non-clear crossing of (c-1) can be distinguished depending on whether the lower threshold crossing signal becomes high within the 2T time.

  In the case of FIGS. 4B-1 and 4C-1, the mask signal once started is continued until the next clear crossing as shown in FIG. 4A occurs, and crosses the slice level. The process is terminated immediately before, for example, at the time of crossing the upper threshold (t1 in FIG. 4A). As a result, all the periodic components that are affected by the identification error occurring in the shortest periodic component can be excluded from the jitter determination target. More specifically, in the case of FIG. 4 (c-1), since two 2T periodic components are followed by a periodic component cx longer than 2T, a clear intersection cr8 occurs at t5 in this periodic component cx. However, the clear crossing here is from the negative side to the positive side and has a polarity opposite to the polarity of the reproduction signal immediately before the start of mask generation, so when the upper mask is terminated at t4 immediately before t5, Since the reproduction signal as a result of masking causes a state change immediately after time t4, a slice level crossing due to the mask occurs. Slice level crossings due to such masks should not occur for jitter detection. Therefore, in FIG. 4C-1, the mask is terminated at the same polarity side, that is, at the threshold crossing point on the positive side, for example, at t6 or t7. However, it is a condition that a clear intersection as shown in FIG. 4A occurs immediately after t7. Although FIG. 4C-1 shows a case where two 2T components continue, the same applies to the case where an even number other than two continues.

  Next, FIG. 5D shows a case where non-return type non-clear crossing continues, that is, two 2T components continue, one component longer than 2T follows, and then two 2T components continue again. Shows when to do. In this case, unlike the case of FIG. 4 (c-1), a clear intersection does not occur between the four consecutive non-clear intersections cr10-cr13 and the next four non-clear intersections cr14-cr17. Instead, the clear intersection cr18 occurs at t10 after the latter clear intersection. Also in this case, after the upper mask signal becomes high at time t8, a clear crossing similar to that in FIG. 4A occurs at time t10, so that it remains high until time t9 immediately before that.

Although not shown in the figure, when a return-type non-clear intersection continues, it can be dealt with by processing in the same manner as in FIG.
Next, a jitter detection apparatus according to an embodiment that embodies the determination principle described in FIGS. 4 and 5 will be described with reference to FIG. As shown in the figure, this jitter detection apparatus includes an automatic gain control circuit (AGC) 10 and an equalizer (EQ) 12 corresponding to the reception circuit 1 of FIG. As a binary signal circuit 50, a latch 52 and a jitter determination circuit 54, and a mask signal generator 30 corresponding to the signal partial determination circuit 3. The difference from the conventional jitter detection apparatus will be briefly described. In the jitter detection apparatus of this embodiment, the circuit portion including the AGC 10, the binarization circuit 50, and the jitter determination circuit 54 has a slice level similar to that of the conventional DVD. It is a circuit that uses it to detect jitter. On the other hand, the equalizer 12 is a circuit for performing equalization processing peculiar to the playback signal from the HD DVD, the latch 52 is a circuit for extracting a signal portion, and the mask signal generator 30 is This is a circuit for generating a signal for determining the signal portion, and is different from the conventional jitter detection device in that these circuits 12, 52 and 30 are provided.

  More specifically, the AGC 10 controls the peak / peak value of the reproduction signal to be constant by performing automatic gain control on the reproduction signal from the HD DVD. The equalizer 12 that receives the signal from the AGC 10 is a circuit that performs processing for matching this reproduction signal from the HD DVD with PR (partial response) characteristics used in the PRML signal processing technology, that is, characteristics determined by the standard. There is a circuit well known in the art. Next, the equalized reproduction signal output from the equalizer 12 is binarized by the binarization circuit 50 using the zero level as the slice level. The latch 52 receives the resulting binarized signal SB and latches the binarized signal in response to the mask signal MST from the mask signal generator 30. That is, the latch 52 ignores the binarized signal portion while the mask signal is present, thereby extracting the signal portion while the mask signal is not present. The next jitter determination circuit 54 performs jitter determination from the latch output SL which is the extracted signal portion by a conventionally known method. The jitter judgment method is a pulse width measurement method that measures the length of each mark / space in the binarized signal and determines its change, and measures the phase difference between the mark / space edge and the synchronization clock edge. The data-to-clock method for determining the above is known.

  Next, the mask signal generator 30 will be described in detail with reference to FIG. 7. The generator 30 includes an upper threshold crossing detector 300, a lower threshold crossing detector 302, and an upper mask generator. Unit 304, lower mask generation unit 306, and mask generation unit 308. Specifically, the upper threshold crossing detection unit 300 includes a binarization circuit 3000 that receives an HD DVD playback signal (see FIG. 7B) that is an output of the AGC 10, and an upper threshold setting circuit 3002. On the other hand, the lower threshold value crossing detection unit 302 includes a binarization circuit 3020 and a lower threshold value setting circuit 3022 that similarly receive an output from the AGC 10. 4 and 5, binarization circuit 3000 performs binarization processing on the AGC output using upper threshold value THU received from upper threshold setting circuit 3002, and The result is output as the upper threshold crossing signal CTHU (FIG. 7C) as described in FIG. The crossing signal CTHU becomes high when the upper threshold value is positively crossed from the zero level side, and becomes low when crossing in the opposite direction. On the other hand, the binarization circuit 3020 performs binarization processing on the AGC output using the lower threshold value THL received from the lower threshold setting circuit 3022 and outputs the result to the lower threshold crossing. The signal CTHL (FIG. 7 (d)) is output. The cross signal CTHL becomes high when the lower threshold value is negatively crossed from the zero level side, and becomes low when crossing in the opposite direction. In the present embodiment, the upper threshold value and the lower threshold value are set so as to exclude at least the shortest 2T component. However, as described above, it is possible to set so as to exclude at least a period component longer than that, or to change the threshold during operation.

  Next, the upper mask generation unit 304 includes a delay circuit 3040, a flip-flop (F / F) 3042, and an OR gate 3044. Similarly, the lower mask generation unit 306 includes the delay circuit 3060, A flip-flop (F / F) 3062 and an OR gate 3064 are provided. Specifically, delay circuits 3040 and 3060 respectively receive the upper or lower threshold crossing signals CTHU and CTHL and delay them by a fixed time, and delay them by a delayed upper threshold crossing signal CTHUD (FIG. 7). (E)) or a delayed lower threshold crossing signal CTHLD (FIG. 7 (f)). In this embodiment, since at least the periodic component to be removed is the shortest 2T component, the delay amount in these delay circuits is 2T. This amount of delay is used to distinguish between clear and non-clear intersections as described in FIGS. When removing components longer than 2T, a delay having a length equal to the period of the maximum removed component may be set.

  Next, the OR gate 3044 receives the lower threshold crossing signal CTHL at one input, the lower mask signal MSL from the F / F 3062 at the other input, and the upper mask inhibition signal INHU ( FIG. 7 (g)) is generated. As can be seen from FIG. 4, the upper mask inhibition signal INHU indicates that the lower threshold crossing signal CTHL is in a high state (this means that the reproduction signal is on the negative side of the lower threshold THL). Or when the lower mask signal MSL is high (which indicates that the opposite lower mask is being generated), the generation of the upper mask signal is inhibited. Therefore, the generation of the upper mask signal is permitted when the lower threshold crossing signal CTHL is in the low state and the lower mask signal MSL is not generated. Similarly, the OR gate 3064 receives the upper threshold crossing signal CTHU at one input, receives the upper mask signal MSU from the F / F 3062 at the other input, and outputs the lower mask inhibition signal INHL (FIG. 7 (h)). Similar to the description of the upper mask prohibition signal INHU, the lower mask prohibition signal INHL requires that the upper threshold crossing signal CTHU is in a high state (this means that the reproduction signal is on the positive side of the upper threshold THH). ) Or when the upper mask signal MSU is high (which indicates that the opposite upper mask is being generated), the generation of the lower mask signal is inhibited. Therefore, the generation of the lower mask signal is permitted when the upper threshold crossing signal CTHU is in the low state and the upper mask signal MSU is not generated.

  Next, the F / F 3042 receives the upper mask inhibition signal INHU at the data input terminal, the delayed upper threshold crossing signal CTHUD at the inverted clock terminal, and the signal at the inverted clock terminal rises high. An inverted version of the signal present at the data input is generated at the Q * ("*" indicates inversion) terminal, which becomes the upper mask signal MSU (FIG. 7 (i)). That is, the upper mask signal generates the upper mask signal MSU when the delayed upper threshold crossing signal CTHUD falls to low and the upper mask inhibit signal INHU is low. Similarly, the F / F 3062 receives the lower mask inhibition signal INHL at the data input terminal, the delayed lower threshold crossing signal CTHLD at the inverted clock terminal, and Q * (“*” is inverted). The lower mask signal MSL (FIG. 7 (j)) is generated at the terminal shown. This lower mask signal generates the lower mask signal MSL when the delayed lower threshold crossing signal CTHLD falls to low and the lower mask inhibit signal INHU is low.

  The next mask generation unit 308 includes an OR gate 3080 and a timing adjustment circuit 3082. The OR gate 3080 receives two inputs of the upper mask signal MSU and the lower mask signal MSL, and generates a mask signal MS (FIG. 7 (k)) as an OR of them at the output. This mask signal is delayed by a time of 2T with respect to the reproduction signal to be masked (delay by delay circuits 3040 and 3060), but the reproduction signal is also delayed by the equalization circuit. In order to synchronize the timing of the signal SB and the mask signal MS, the timing adjustment circuit 3082 generates a mask signal MST after time adjustment by delaying the mask signal MS when it is ahead of the binarized signal SB. This is supplied to the latch 52. When the mask signal MS is delayed from the binarized signal SB, the delay circuit may be changed between the binarizing circuit 50 and the latch circuit 52.

  Next, the operation of the mask signal generator 30 shown in FIG. 6 will be described in detail with reference to FIG. 7 in detail. The HD DVD playback signal shown in the timing diagram of FIG. 7 includes a clear intersection including a clear intersection 1 and a clear intersection 2, a return-type non-clear intersection 1, a non-return-type non-clear intersection, and a return-type non-clear intersection 2. These will be described. First, in the case of the clear crossing 1 from the negative side to the positive side, in this case, it is not necessary to generate the lower mask. At this time, the delayed lower threshold crossing signal CTHLD falls at time t11. Since the lower mask inhibition signal INHL is high (the upper threshold crossing signal CTHU is high at the time of falling at t11 (however, the upper mask signal MSU is low)), mask generation is prohibited. The side mask remains low. In the case of the clear intersection 2, it is determined whether or not the upper mask is generated, but it is not generated in the same manner. Next, in the case of the return type non-clear intersection 1, since it starts from the negative side at this time, it is necessary to generate the lower mask MSL. At this time, when the delayed lower threshold crossing signal CTHLD falls at time t12, the lower mask inhibition signal INHL is low (the upper threshold crossing signal CTHU is low at the fall at t12). Since mask generation is not prohibited, the lower mask MSL is set high to start the mask signal. Next, when the delayed lower threshold crossing signal CTHLD falls at time t13, the lower mask inhibition signal INHL is high (the upper threshold crossing signal CTHU is high at t13) to inhibit mask generation. Therefore, the lower mask MSL is set low to end the mask signal.

  Next, in the case of a non-return type non-clear intersection, in this case, since it starts from the positive side, it is necessary to generate an upper mask. That is, when the delay upper threshold crossing signal CTHUD falls at t14, mask generation is prohibited when the upper mask inhibition signal INHU is low (the lower threshold crossing signal CTHL is low at the fall at t14). Since this is not done, the upper mask MSU is set high to start. Thereafter, the next falling of the delayed upper threshold crossing signal CTHUD occurs at time t16. At this time, the mask is generated when the upper mask inhibition signal INHU is high (the lower threshold crossing signal CTHL is high at t16). Since the upper mask MSU is set low, the upper mask is terminated. The last return-type non-clear intersection 2 is opposite in polarity to the return-type non-clear intersection 1 described above, but generates an upper mask in the same operation. At time t15, the delayed lower threshold crossing signal CTHLD falls. At this time, the lower mask inhibition signal INHL becomes high. This is because the upper threshold crossing signal CTHU is high at time t15.

  Next, with reference to FIG. 8, an operation in the case where non-return type non-clear crossing occurs continuously will be described. In this case, the same operation as at time t14 of the non-return type non-clearing crossing in FIG. 7 occurs at time 20 and the upper mask MSU goes high. Also in the example of FIG. 8, the delayed lower threshold crossing signal CTHLD falls at time t21 corresponding to time t15 in FIG. At this time, the lower mask inhibition signal INHL becomes high. The reason is that at time t21, the upper threshold crossing signal CTHU is low, but the upper mask signal MSU is high unlike the example of FIG. For this reason, the generation of the lower mask is prohibited, and the lower mask MSL remains low. The subsequent operation is the same as in the case of FIG. As described above, while one of the upper mask and the lower mask is generated, the other mask is unnecessary, and thus the generation thereof is prevented.

  The mask signal generated as described above generates a mask signal MST in which the timing adjustment circuit 3082 matches the timing of the binarized signal SB. The latch 52 that receives the mask signal MST latches the state of the binary signal SB when the mask signal rises high, and outputs the latched state as long as the mask signal remains high. When the signal falls to low, the latch operation is stopped and the signal received at the input is generated as it is at the output. This is the latch output SL. As a result, the signal portion that is a part of the reproduction signal can be extracted while ignoring the reproduction signal while the mask is present.

  Next, a method for realizing the mask signal generator 30 of FIG. 6 by software will be described with reference to the flowchart of FIG. In this flowchart, the same symbols as the names of the signals are used for the variables corresponding to the signals appearing in the circuit of FIG. 6 for convenience of explanation. First, in step 900, one sample of the HD DVD playback signal is acquired and set to A. This flow is executed every time one sample of the HD DVD playback signal is acquired.

  Next, in steps 902 to 908, an upper threshold value crossing variable CTHU is generated from the upper threshold value variable THU, which corresponds to the function of the upper threshold value crossing detection unit 300 in FIG. That is, in step 902, a certain value as the upper threshold value is set in the variable THU. In step 904, it is determined whether the reproduction signal sample A is equal to or greater than the upper threshold variable THU. If YES, in step 906, the upper threshold crossing variable CTHU is set to high, that is, "1". If NO, step 908 sets low, ie, “0”.

  Next, in steps 910 to 916, the lower threshold value crossing variable CTHL is generated from the lower threshold value variable THL. This corresponds to the function of the lower threshold value crossing detecting unit 302 in FIG. ing. Specifically, in step 910, a value as a lower threshold value is set in the variable THL, and in step 912, it is determined whether or not the sample A is equal to or lower than THL. Variable CTHL is set to “1”. On the other hand, if NO, variable CTHL is set to “0” in step 916.

  Next, in steps 918 to 926, the delayed upper threshold crossing variable CTHUD is set from the upper threshold crossing variable CTHU, which corresponds to the function of the delay circuit 3040 in FIG. That is, it is determined whether or not the upper threshold value THU is less than the amplitude of the 3T periodic component. If YES, the upper threshold value crossing variable is delayed for 2T in step 920 (for example, using a clock synchronized with the reproduction signal). When NO, it is determined in step 922 whether THU is less than the amplitude of the periodic component of (n−1) T, where n is an integer greater than 5. In step 922, YES, in step 924, the upper threshold crossing variable is delayed by an amount of (n-1) T, and if NO, the variable is delayed in step 926 by an amount of nT, and the result Is set as the delay upper threshold crossing variable CTHUD, and in steps 928 to 936, the lower threshold crossing variable CTH is processed in the same manner as in steps 918 to 926. The delay upper threshold value crossing variable CTHLD is set from L (corresponding to the function of the delay circuit 3060 in FIG. 6), and can be performed in the same manner as in Steps 918 to 926, so the description is omitted. In the case of a signal, the signal component has a period of 2T to 11T, 13T, and the minimum amplitude is 2T, the amplitude is increased to 3T, 4T, and the maximum amplitude is reached at 5T, and after 6T, the maximum is 13T. However, although 5T, 6T, and 7T are signal components having the same maximum amplitude, they can be distinguished by changing the delay amount, so that they can be distinguished from 2T to 5T, from 2T to 6T, from 2T It is possible to distinguish and detect up to 7 T. This also applies to the delay amount set in the delay circuits 3040 and 3060 in FIG. In the above flow, similar steps are duplicated on the upper and lower sides not only when the upper and lower threshold values have the same absolute value, but also when they have different absolute values. For example, when it is desired to detect jitter of a reproduction signal in which the symmetry is shifted, that is, the intermediate value between the positive peak and the negative peak does not reach the zero level.

  Next, in steps 938 to 942, the upper mask is set, which corresponds to the functions of the OR gate 3044 and the F / F 3042 in FIG. That is, in step 938, it is determined whether the lower threshold crossing variable CTHL is “0” and the lower mask variable MSL is “0” when the delayed upper threshold crossing variable CTHUD transitions from high to low. , And if YES, the upper mask variable MSU is set high in step 940 to start the upper mask if no upper mask has yet occurred at this time, and if it has already started the upper mask Maintain the upper mask. On the other hand, when NO in step 938, the upper mask variable MSU is set to low in step 942, and the upper mask is terminated when the upper mask has already occurred.

  Similarly, in steps 944 to 948, the lower mask is set, which corresponds to the functions of the OR gate 3064 and the F / F 3062 in FIG. Note that the processing is basically the same as in steps 938 to 942, and the difference is that in step 944, the delay upper threshold crossing variable CTHUD is not at the transition from high to low, but is delayed. Whether the side threshold crossing variable CTHLD is transitioning from high to low, and whether the upper threshold crossing variable CTHU is “0” and the upper mask variable MSU is “0” is determined. Is a point. In this way, the start or end of the lower mask MSL is realized. Finally, in step 950, the mask variable MS is generated by taking the logical sum of the upper mask variable MSU and the lower mask variable MSL. This processing corresponds to the OR gate 3080 in FIG.

By repeating the operation described above for each sample of the HD DVD playback signal, the operation described in FIGS. 6, 7, and 8 can be realized.
Next, another embodiment of the jitter detection circuit shown in FIG. 2 will be described with reference to FIG. In FIG. 6, the latch circuit 52 is disposed after the binarization circuit 50. However, in the embodiment of FIG. 10, the hold circuit 56 is placed in front of the binarization circuit 50a, and the jitter determination circuit 54a is binarized. The output from the circuit 50a is received. At this time, instead of the latch circuit 52 of FIG. 6, in FIG. 10, the hold circuit 56 is configured to receive the output of the equalizer 12 of FIG. 6 and the mask signal MST from the mask signal generator 30. At this time, the hold circuit 56 holds the equalizer output when the mask signal MST becomes high and generates it at the output. When the mask signal MST becomes low, the hold circuit 56 outputs the equalizer output as it is. appear. Also with this configuration, a portion of the HD DVD playback signal can be extracted. The binarization circuit 50a and the jitter determination circuit 54a may have the same configuration as that of FIG.

  Next, still another embodiment of the jitter detection circuit shown in FIG. 2 will be described with reference to FIG. This embodiment differs from the jitter detection circuit of the embodiment of FIG. 6 in that it is the jitter determination circuit 54b that receives the mask signal instead of the latch. By receiving this mask signal, the jitter judgment circuit 54b does not extract a part of the HD DVD playback signal, but controls the jitter judgment operation to substantially detect jitter based only on a part of the playback signal. . Furthermore, the embodiment of FIG. 11 can be applied to the jitter detection circuit shown in FIG. 10 in a similar manner so that the jitter determination circuit 54a receives the mask signal instead of the hold circuit 56.

  Next, with reference to FIG. 12, a jitter measuring apparatus including the above-described jitter detecting apparatus according to the embodiment of the present invention will be described. The jitter measuring apparatus includes a display / output unit that receives a jitter determination output from the jitter detecting apparatus. The output from the jitter detection apparatus can take a form corresponding to a display form or an output form in the display / output unit. For example, the jitter determination output may be in a form in which the width of each mark / space length is statistically processed, or in a form in which the difference between the mark / space edge and the clock edge is statistically processed as described above. The display / output unit outputs the received jitter determination output to an output device such as a display or a printer according to the user's selection.

  Finally, with reference to FIG. 13, an electronic apparatus provided with the above-described jitter detection apparatus according to the embodiment of the present invention will be described. Examples of the electronic apparatus include optical disk-related apparatuses such as an optical pickup, an optical disk driver, and an optical disk player. In addition, other devices such as a communication device are included as long as the device uses the PRML signal processing technology. By providing the above-described jitter detection device according to the embodiment of the present invention in such an electronic device, the jitter processing for removing the influence of jitter in the electronic device can be performed at a higher speed or with a simple circuit configuration. Can be realized.

  In the above, several embodiments of the present invention have been described in detail. However, the jitter detection apparatus of the above embodiment is not limited to a recording medium such as HD DVD, but is also applicable to jitter detection of a signal from another information recording medium using a signal form similar to HD DVD, for example, a magnetic disk. Can be applied to. Further, as described above, the jitter detection apparatus of the above embodiment can also be applied to signals from other fields where the PRML method is used, for example, communication media such as communication lines and networks.

(a) shows the example of a waveform of the reproduction signal from HD DVD, (b) is a figure which shows the example of the waveform of the reproduction signal from DVD. FIG. 2 is a block diagram showing a configuration of a jitter detection apparatus according to one embodiment of the present invention. FIG. 3 is a diagram showing the relationship between various signal components included in an HD DVD playback signal and the corresponding slice level, upper threshold value, and lower threshold value. FIG. 4 is a diagram for explaining in principle the technique for determining the signal portion used for jitter detection in the HD DVD playback signal, where (a) is a clear intersection, (b-1) and (B-2) shows the case of a return type non-clear intersection, and (c-1) and (c-2) show the case of a non-return type non-clear intersection. FIG. 5 is a view similar to FIG. 4, and FIG. 5D shows a case where non-return type non-clear intersections continue. FIG. 6 is a block diagram showing a jitter detection apparatus according to an embodiment that embodies the determination principle described in FIGS. 4 and 5; FIG. 7 is a timing diagram showing signal waveforms at various parts in the apparatus of FIG. FIG. 8 is a timing chart showing signal waveforms at various parts in the apparatus of FIG. 6 when the non-return type non-clear crossing shown in FIG. 5 occurs continuously. FIG. 9 is a flowchart of a program that realizes the same function as that realized by the mask signal generator 30 of FIG. FIG. 10 is a block diagram showing another embodiment of a jitter detection circuit in the jitter detection apparatus shown in FIG. 11 is a block diagram showing still another embodiment of the jitter detection circuit in the jitter detection apparatus shown in FIG. FIG. 12 is a diagram showing a jitter measuring apparatus including the jitter detecting apparatus according to the embodiment of the present invention. FIG. 13 is a diagram showing an electronic apparatus including the jitter detection apparatus according to the embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Reception circuit 3 Signal partial determination circuit 5 Jitter detection circuit 30 Mask signal generator 300 Upper threshold crossing detection part 302 Lower threshold crossing detection part 304 Upper mask generation part 306 Lower mask generation part 308 Mask generation part c1 ~ C13 Signal component cr1, cr8 Clear intersection cr2-cr7 Non-clear intersection cr10-cr17 Non-clear intersection cr18 Clear intersection

Claims (18)

Receiving a signal; and
A determination step of determining a signal portion of the received signal used for jitter detection based on the signal amplitude;
A jitter detection step of detecting jitter in the signal based on the determined signal portion;
Jitter detection method including: The method of claim 1, wherein
The determination step includes
Defining first and second threshold values;
Generating a period signal using the first and second thresholds;
Including
The jitter detection step includes
Detecting the signal portion by responding to the received signal according to the period signal;
A jitter detection method. The method of claim 2, wherein
Generating the period signal comprises:
Binarizing the received signal with the first threshold to generate a first binarized signal;
Binarizing the received signal with the second threshold to generate a second binarized signal;
A step of generating a mask signal from the first binarized signal and the second binarized signal, the mask signal being a first signal portion other than the first signal portion which is the signal portion of the received signal; Said processing step representing a period during which there are two signal parts;
Including
Detecting the signal portion comprises:
Extracting the first signal portion from the received signal using the mask signal;
A jitter detection method. The method of claim 3, wherein
The received signal includes a signal component having positive and negative maximum amplitude values and having an amplitude equal to or smaller than a first amplitude value smaller than the maximum amplitude value;
The first threshold has a value between the positive maximum amplitude value and the positive first amplitude value;
The second threshold value has a value between the negative maximum amplitude value and the negative first amplitude value.
Jitter detection method. The method of claim 4, wherein
The processing step includes
Whether or not the first state in which the received signal crosses one of the first and second thresholds in the first polarity direction has occurred is determined in the first and second. Determining based on one of the associated binarized signals of:
When the first state occurs, a second state in which the received signal crosses the other threshold value in the first polarity direction within a predetermined time from the first time point when the first state occurs is Determining whether it has occurred based on the other binarized signal;
Starting the mask signal when the second state has not occurred within the predetermined time; and
It is determined whether or not a third state has occurred in which another first state has occurred and another second state has occurred within a predetermined time from a third time point at which the first state has occurred. Steps,
Ending the mask signal at the third time point when the third state occurs;
A jitter detection method. The method of claim 5, wherein
The processing step includes
Once the mask signal is started, the generation of another mask signal is prevented until the mask signal is ended.
A jitter detection method.   A jitter measurement method for measuring jitter using the jitter detection method according to claim 1. A receiving circuit for receiving a signal;
A determination circuit for determining a signal portion used for jitter detection in the received signal based on a signal amplitude;
A jitter detection circuit for detecting jitter related to the signal based on the determined signal portion;
A jitter detection apparatus. The apparatus of claim 8.
The determination circuit includes:
A first threshold value setting circuit for generating a first threshold value;
A second threshold setting circuit for generating a second threshold;
A period signal generating circuit for generating a period signal using the first and second threshold values;
Including
The jitter detection circuit includes:
A signal part detection circuit for detecting the signal part by responding to the received signal according to the period signal;
Including a jitter detection apparatus. The apparatus of claim 9.
The period signal generation circuit includes:
A first binarization circuit for binarizing the received signal with the first threshold value to generate a first binarized signal;
A second binarization circuit that binarizes the received signal with the second threshold value to generate a second binarized signal;
A processing circuit for generating a mask signal from the first binarized signal and the second binarized signal, wherein the mask signal is a signal other than the first signal portion which is the signal portion of the received signal. Said processing circuit representing a period in which there are two signal parts;
Including
The signal part detection circuit includes:
An extraction circuit for extracting the first signal portion from the received signal using the mask signal;
including,
Jitter detector. The apparatus of claim 10.
The received signal includes a signal component having positive and negative maximum amplitude values and having an amplitude equal to or smaller than a first amplitude value smaller than the maximum amplitude value;
The first threshold has a value between the positive maximum amplitude value and the positive first amplitude value;
The second threshold value has a value between the negative maximum amplitude value and the negative first amplitude value.
Jitter detector. The apparatus of claim 11.
The processing circuit includes:
A first delay circuit for generating a first delayed binarized signal obtained by delaying the first binarized signal by a predetermined time;
A second delay circuit for generating a second delayed binary signal obtained by delaying the second binary signal by the predetermined time;
A first logic circuit connected to receive the first and second binarized signals and the first and second delayed binarized signals and generating first and second mask signals Because
a. Whether or not the first state in which the received signal crosses one of the first and second thresholds in the first polarity direction has occurred is determined in the first and second. Based on one of the related binarized signals of
b. When the first state occurs, a second state in which the received signal crosses the other threshold value in the first polarity direction within the predetermined time from the first time point when the first state occurs is Determining whether or not it occurred based on the other binarized signal and one of the first and second delayed binarized signals,
c. When the second state does not occur within the predetermined time, start one of the related mask signals of the first and second mask signals;
d. It is determined whether or not a third state has occurred in which another first state has occurred and another second state has occurred within a predetermined time from a third time point at which the first state has occurred. ,
e. The first logic circuit that operates to terminate the one mask signal at the third time point when the third state occurs;
A second logic circuit for generating the mask signal from the first and second mask signals;
Including a jitter detection apparatus. The apparatus of claim 12.
The first logic circuit includes:
A first mask signal generation logic circuit that receives the first delayed binary signal, the second binary signal, and the second mask signal, and generates the first mask signal;
A second mask signal generation logic circuit that receives the second delayed binary signal, the first binary signal, and the first mask signal, and generates the second mask signal;
Including
The first logic circuit once prevents the generation of the other mask signal until the one mask signal is terminated after the one mask signal is started.
Jitter detector. The apparatus of claim 10.
The jitter detection circuit further includes:
A third binarization circuit for generating a third binarized signal by binarizing the received signal with a third threshold value, wherein the extraction circuit includes the third binary signal The third binarization circuit for extracting the first signal portion from the digitized signal;
A jitter determination circuit that determines the jitter of the received signal using the first signal portion extracted from the third binarized signal by the extraction circuit;
Jitter detection circuit including The apparatus of claim 14.
The extraction circuit includes:
A circuit for generating the first signal portion by changing the magnitude of the third binarized signal during a period in which the mask signal exists;
Jitter detector. The apparatus of claim 10.
The jitter detection apparatus, wherein the second signal portion includes at least a shortest periodic component in the reception signal. The apparatus of claim 8.
The jitter detection apparatus, wherein the signal is a signal from an information recording medium.   An electronic device comprising the jitter detection device according to claim 8.

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