JP2007310975A - Address information detecting circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an address information detecting circuit reducing influence of noise of a wobble signal thereby accurately detecting an address signal of an ADIP (Address in Pre-groove) in an optical disk of a DVD+RW system. <P>SOLUTION: A gate signal is formed from a position of a previous detected ADIP signal for a signal obtained by multiplication and integration of the wobble signal and a carrier wave of the wobble signal, accumulation is performed on the basis of the position of the gate signal, and thus information identifying the ADIP signals as SYNC, ZERO and ONE signals is added. More accurate address information can be consequently detected. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an address information detection circuit called ADIP of an optical disc drive apparatus for recording data on a DVD + RW optical disc.

  Data is recorded in a spiral on an optical disc. Therefore, guide grooves are recorded in advance on the recordable optical disc so that the optical head can correctly follow the spiral during recording. Further, the groove is wobbled and recorded at a constant period, and at the time of reproduction, the scanning speed is detected by measuring the wobble period, and a clock signal synchronized with the rotational speed can be obtained.

  By the way, a recordable optical disc needs to have address data recorded in advance on the optical disc. The optical disk drive device reproduces the address data before recording the data, identifies the position on the optical disk from the reproduced address data, and records the data. As address data recording methods, there are a pre-pit method in which pits are formed in advance on a track and a wobble modulation method in which a groove is modulated according to an address. The pre-pit method is adopted in DVD-R / RW and DVD-RAM, and the wobble modulation method is adopted in CD-R / RW and DVD + R / RW. In the pre-pit method, since the recording signal has information at the edge portion, it tends to lack reliability, and it is preferable to record the address data by the wobble modulation method.

  In particular, in a DVD + RW optical disc, address information called ADIP (Address in Pre-groove) is preformatted on a recording medium in advance by a wobble modulation method. When data is recorded on this optical disk, ADIP is reproduced to detect address information, and the position on the optical disk is specified from the detected address information and data is recorded.

  As a circuit for reproducing an ADIP signal from a phase-modulated wobble signal, a circuit as disclosed in Patent Document 1 is disclosed. The conventional address information detection circuit shown in Patent Document 1 latches and outputs the detected ADIP signal as it is.

In ADIP, it is defined as a standard to represent “ADIP pit” by a total of 93 wobbles of 8 wobble ADIP units and 85 wobble monotone wobbles. In FIG. 10, FIG. 10 (a) shows a monotone wobble. In the 8-wobble ADIP unit, as shown in FIGS. 10B to 10D, there are three patterns of ADIP pits. That is, the sync pattern indicating the break of the ADIP word shown in FIG. 10B, the zero pattern showing ADIP = 0 shown in FIG. 10C, and ADIP = 1 shown in FIG. 10D. One pattern.
JP 2003-85749 A

  As described above, in the DVD + RW optical disc, address information called ADIP is formed by the phase modulation of the wobble obtained by inverting the phase of 32T wobble (sine wave) by 180 degrees and normal wobble, and the signal is put on the signal. In addition, there is a concern about deterioration of the wobble signal due to the increase in speed and the distribution of various quality media to the market.

  Further, in the conventional address information detection circuit, when detecting the wobble ADIP modulation unit, the detection is performed by multiplying the carrier signal synchronized with the wobble signal and latching the integral value every 32T. In the case of the influence of the binarization of the simple slice method, the ADIP signal is erroneously detected, so that the sync pattern, the zero pattern, and the one pattern of the ADIP signal are erroneously determined. Furthermore, when the wobble jitter is large, the ADIP signal is erroneously detected due to factors such as the case where the ADIP signal of the adjacent track crosstalks.

  The present invention has been made to solve the above problems, and provides an address information detection circuit capable of accurately reproducing address information without being affected by defects or crosstalk of the information recording medium. For the purpose.

  In order to solve the above-mentioned problem, an address information detection circuit according to claim 1 of the present invention wobbles address information and a pattern for synchronization on a data recording track with a frequency component phase-modulated according to a predetermined rule. In an address information detection circuit of an optical disc apparatus that records and reproduces data on an optical disc, an A / D converter that converts the wobble signal of the data recording track into a digital signal, and a first waveform shaping of the digitized wobble signal Digital filter, a generation circuit that generates a single carrier having the same frequency as the wobble signal, and a phase adjustment circuit that adjusts the phase of the single carrier generated by the generation circuit so as to be synchronized with the phase of the wobble signal A wobble signal output from the first digital filter, and A multiplier that multiplies the single carrier wave output from the phase adjustment circuit and outputs it as a phase modulation signal, a second digital filter that removes a high frequency component of the phase modulation signal, and phase modulation of the phase modulation signal And a discriminator for discriminating a phase modulation pattern from the output of the second digital filter, and the discriminator comprises the second digital signal according to the gate signal. An adder for adding output signals of the filter, and a selector for resetting the adder in accordance with the gate signal.

  An address information detection circuit according to a second aspect of the present invention is the address information detection circuit according to the first aspect, wherein the optical disc is a DVD + RW or DVD + R optical disc, and the discriminator is the phase modulation signal. On the basis of the phase modulation unit, the phase modulation signal identifies whether the phase modulation signal is a sync pattern, a zero pattern, or a one pattern.

  An address information detection circuit according to claim 3 of the present invention is the address information detection circuit according to claim 2, wherein the gate signal generation circuit receives a gate signal and a reset signal for identifying the phase modulation pattern. The generated discriminator includes a register that changes the number of bits to be added based on the gate signal, and resets the number of bits to be added when the reset signal is input.

  According to a fourth aspect of the present invention, there is provided an address information detection circuit for recording data on an optical disc wobbled with a frequency component obtained by phase-modulating address information and a pattern for synchronization on a data recording track according to a predetermined rule. In an address information detection circuit of an optical disc apparatus that performs reproduction, an A / D converter that converts the wobble signal of the data recording track into a digital signal, a first digital filter that performs waveform shaping of the digitized wobble signal, A generation circuit that generates a single carrier wave having the same frequency as the wobble signal, a phase adjustment circuit that adjusts the phase of the single carrier wave generated by the generation circuit so as to be synchronized with the phase of the wobble signal, and the first Output from the digital filter and the phase adjustment circuit. And a second digital filter for removing a high frequency component of the phase modulation signal, and a phase modulation unit of the phase modulation signal. A gate signal generation circuit for generating a gate signal, a discriminator for discriminating a phase modulation pattern from the output of the second digital filter, and a coefficient of the first digital filter set to at least two or more arbitrary values And switching means for switching the coefficient of the first digital filter based on the gate signal.

  According to a fifth aspect of the present invention, there is provided an address information detection circuit for recording data on an optical disk wobbled with a frequency component obtained by phase-modulating address information and a pattern for synchronization with a data recording track according to a predetermined rule. In an address information detection circuit of an optical disc apparatus that performs reproduction, an A / D converter that converts a wobble signal of the data recording track into a digital signal, a first digital filter that performs waveform shaping of the digitized wobble signal, and An amplitude adjustment circuit that adjusts the amplitude of the output of the first digital filter to at least two kinds of amplitude adjustment values, a generation circuit that generates a single carrier wave having the same frequency as the wobble signal, and the generation circuit Adjust the phase of the generated single carrier to be synchronized with the phase of the wobble signal. A multiplier that multiplies the phase adjustment circuit, the wobble signal output from the amplitude adjustment circuit, and the single carrier wave output from the phase adjustment circuit, and outputs the result as a phase modulation signal; and the high frequency of the phase modulation signal A second digital filter for removing components, a gate signal generation circuit for generating a gate signal synchronized with the phase modulation unit of the phase modulation signal, and a discriminator for determining a phase modulation pattern from the output of the second digital filter And switching means for switching the amplitude adjustment value adjusted by the amplitude adjustment circuit based on the gate signal.

  According to a sixth aspect of the present invention, there is provided an address information detection circuit for recording data on an optical disk wobbled with a frequency component obtained by phase-modulating address information and a pattern for synchronization on a data recording track according to a predetermined rule. In an address information detection circuit of an optical disc apparatus that performs reproduction, an A / D converter that converts a wobble signal of the data recording track into a digital signal, a first digital filter that performs waveform shaping of the digitized wobble signal, and A generation circuit that generates a single carrier wave having the same frequency as the wobble signal, a phase adjustment circuit that adjusts the phase of the single carrier wave generated by the generation circuit so as to be synchronized with the phase of the wobble signal, and the first circuit Output from the wobble signal output from the digital filter and the above phase adjustment circuit A multiplier that multiplies a single carrier wave to be output and outputs a phase modulated signal, a second digital filter that removes a high frequency component of the phase modulated signal, and a gate signal that is synchronized with the phase modulating unit of the phase modulated signal A gate signal generation circuit for generating a signal, a discriminator for discriminating a phase modulation pattern from the output of the second digital filter, and a minimum for binarizing the output of the second digital filter and outputting it as an ADIP modulation signal And an ADIP detection circuit for setting two slice levels, and switching means for switching the slice level based on the gate signal.

  According to a seventh aspect of the present invention, there is provided an address information detection circuit for recording data on an optical disc wobbled with a frequency component obtained by phase-modulating a pattern for obtaining address information and synchronization on a data recording track according to a predetermined rule. In an address information detection circuit of an optical disc apparatus that performs reproduction, an A / D converter that converts the wobble signal of the data recording track into a digital signal, a digital filter that shapes the waveform of the digitized wobble signal, and the wobble signal A generation circuit that generates a single carrier wave having the same frequency, a phase adjustment circuit that adjusts the phase of the single carrier wave generated by the generation circuit so as to be synchronized with the phase of the wobble signal, and the first digital filter. Output wobble signal and output from the phase adjustment circuit A multiplier that multiplies one carrier wave, a second digital filter that integrates the output of the multiplier, a gate signal generation circuit that generates a gate signal synchronized with a phase modulation unit from the phase modulation signal of the wobble signal, The phase adjustment circuit includes switching means for setting at least two gains and switching based on the gate signal.

  According to the address information detection circuit of the present invention, more accurate address information can be reproduced by adding the identified ADIP signal to the sync pattern, zero pattern, and one pattern signal. Therefore, conventionally, when detecting the wobble ADIP modulation unit, the detection is performed by multiplying the carrier signal synchronized with the wobble signal and latching the integral value every 32T. In the binarization of the simple slice method, there is an increased probability of erroneously determining the sync pattern, zero pattern, and one pattern of the ADIP signal by erroneously detecting the ADIP signal. By using this circuit, an ADIP signal can be detected correctly even when noise is superimposed on the signal.

Embodiments of the present invention will be described below with reference to the drawings.
(Embodiment 1)
FIG. 1 is a diagram showing a configuration of an address information detection circuit according to the first exemplary embodiment of the present invention.
The address information detection circuit according to the first embodiment includes an A / D converter (ADC) 1, a first digital filter 2, an offset removal circuit 3, a carrier signal generation circuit 4, a phase adjustment circuit 5, and multiplication. And a second digital filter 8, a gate signal generation circuit 9, and an ADIP signal detection circuit 10.

  The A / D converter 1 converts the wobble analog signal 1s of the data recording track of the optical disc into a digital signal 2s.

  The first digital filter 2 performs waveform shaping of the wobble signal 2s digitized by the A / D converter 1.

  The offset removal circuit 3 removes the offset of the wobble signal 3s output from the first digital filter 2.

  The carrier signal generation circuit 4 generates a single carrier wave (carrier signal) 5s having the same frequency as the wobble signal.

  The phase adjustment circuit 5 adjusts the phase of the carrier signal 5s so as to be synchronized with the phase of the wobble signal 4s.

  The multiplier 7 multiplies the carrier signal 6 s output from the phase adjustment circuit 5 and the wobble signal 4 s output from the offset removal circuit 3.

  The second digital filter 8 integrates the multiplication result 7s of the multiplier 7 and removes the high frequency component.

  The ADIP signal detection circuit 10 detects a phase modulation signal (ADIP signal) from the output 8s of the digital filter 8, discriminates the phase modulation pattern of the phase modulation signal, and outputs an ADIP modulation signal discrimination signal 12s. The ADIP signal detection circuit 10 binarizes the ADIP signal using the slice level and outputs an ADIP binarized signal 11s. There are three types of phase modulation patterns: sync pattern, zero pattern, and one pattern. The phase modulation unit is a High section of the second digital filter output 8s.

  The gate signal generation circuit 9 generates a gate signal 10s synchronized with the phase modulation unit from the ADIP binarized signal 11s.

FIG. 2 is a diagram showing a detailed configuration of the ADIP detection circuit 10.
In the figure, gate signals 104s, 105s, 106s and a reset signal 110s are generated by a gate signal generation circuit 9 in order to identify a phase modulation pattern.

The ADIP detection circuit 10 includes an inverting unit 101, a first selector 102, a second selector 103, and an adder 104.
The inversion unit 101 inverts the polarity of the signal 8s.

  The first selector 102 selects the signal 8s or the output of the inverting unit 101 in response to the input of the gate signal 105s.

  The second selector 103 selects the output of the first selector 102 or 0 based on the input of the gate signal 104s.

  The adder 104 changes the number of bits to be added based on the phase modulation pattern. When the gate signal 106s is HIGH, the number of bits is added, and when the reset signal 110 is input, the added value is reset.

The operation of the ADIP detection circuit 10 will be described below with reference to FIG.
In FIG. 3, signals 101 s, 102 s and 103 s indicate three types of phase modulation patterns of the second digital filter output 8 s input to the ADIP detection circuit 10. Signals 107s, 108s, and 109s indicate three types of phase modulation patterns of the ADIP binarized signal 11s.

  In the period from the time T1 to the time T2, the second digital filter output 8s is at a high level in all patterns of the sync pattern 101s, the zero pattern 102s, and the one pattern 103s. On the other hand, in the period from time T2 to time T3, the sync pattern 101s is at a high level, but the zero pattern 102s and the one pattern 103s are at a low level.

  Therefore, when the high level of the second digital filter output 8s continues in the period from time T2 to T3, that is, in the case of the sync pattern 101s, a value is added to the + side. When the low level of the second digital filter output 8s is continuous, that is, in the case of the zero pattern 102s and the one pattern 103s, the value is added to the minus side.

  Thus, at time T3, the sync pattern takes a positive value and the zero pattern or the one pattern takes a negative value like the signals 111s, 112s, and 113s, and therefore the phase modulation pattern of the signal 8s is a sync pattern. It can be determined whether or not. During this time, even if noise is superimposed on the signal 8s instantaneously, it is averaged, so the probability of erroneous determination due to noise can be reduced.

  Next, in the period from time T3 to T4, the zero pattern 102s is at the low level, and the one pattern 103s is at the high level. In the period from time T4 to T5, the zero pattern 102s is at the high level, and the one pattern 103s is at the low level.

  Therefore, the polarity to be added is switched between the period from time T3 to T4 and the period from time T4 to T5. Then, at time T5, since the zero pattern takes a positive value and the one pattern 109 takes a negative value, it can be determined whether the phase modulation pattern of the signal 8s is a zero pattern or a one pattern. it can.

  Further, a register for setting the number of bits to be added by the adder 104 is provided, and when the ADIP modulation signal is identified as the gate signal, the setting value of the register is changed to change the number of bits to be added. Even if the signals 107 s, 108 s, and 109 s do not exceed the zero crossing point and the polarity does not change, the effect of discriminating the ADIP signal pattern at the time T3 or T5 can be enhanced by adding the values.

(Embodiment 2)
FIG. 4 is a diagram showing a configuration of the address information detection circuit according to the second exemplary embodiment of the present invention. In the figure, the same components as those in FIG.
The address information detection circuit according to the second embodiment includes switching means 303 in addition to the configuration of the address information detection circuit shown in FIG.
The switching signal 303 sets the coefficient of the first digital filter 2 to at least two or more arbitrary values and switches based on the phase inverting part gate signal 114s. Here, it is assumed that either the first coefficient 301 or the second coefficient 302 is selected and output to the first digital filter 2.

Next, the operation and effect of the second embodiment will be described.
Usually, when the first digital filter 2 is constituted by a low-pass filter or a band-pass filter, the frequency of the phase inversion unit is lowered if the characteristics are matched so that the frequency characteristics of the filter are optimized for a single wobble waveform. As a result, the signal amplitude of the phase inverting unit decreases. Further, when noise is superimposed on the signal 8s, the S / N ratio (signal noise ratio) is lowered, and as a result, the detection rate of the ADIP signal is lowered.

  Therefore, in the present embodiment, based on the phase inversion unit gate signal 114s generated by the gate signal generation circuit 9, the wobble single waveform unit and the phase inversion unit are switched to the optimum settings by the switching unit 303, respectively. did. Thereby, it is possible to adjust the signal amplitude to be optimum for each of the wobble single waveform and the phase inversion unit.

  In the case of adopting a circuit configuration in which the second digital filter 8 for integrating the output 7s of the multiplier 7 switches the filter coefficient by the phase inversion unit gate signal 114s, the frequency of the wobble single waveform unit is used. By reducing the bandwidth, the probability of erroneous detection of noise as an ADIP signal can be reduced.

(Embodiment 3)
FIG. 5 is a diagram showing a configuration of an address information detection circuit according to the third exemplary embodiment of the present invention. In the figure, the same components as those in FIG.
The address information detection circuit according to the third embodiment includes a switching unit 403 and an amplitude adjustment circuit 404 in addition to the configuration of the address information detection circuit shown in FIG.

  The amplitude adjustment circuit 404 is located between the offset removal circuit 3 and the multiplier 7 and adjusts the amplitude of the wobble signal 4 from which the offset is removed.

  The switching means 403 sets at least two kinds of amplitude adjustment values of the wobble signal 4s from which the offset has been removed, and performs switching based on the phase inverter gate signal 114s. Here, it is assumed that either the first amplitude adjustment value 401 or the second amplitude adjustment value 402 is selected and output to the amplitude adjustment circuit 404.

Next, the operation and effect of the third embodiment will be described.
As shown in FIG. 6, the wobble signal 31s after the offset removal has different frequency characteristics between the single waveform portion and the wobble phase inversion portion. That is, an amplitude difference such as L1 and L2 occurs. This difference is generated by passing through the digital filter 2.

  In this embodiment, in order to improve the amplitude drop in the phase inversion unit, optimum amplitude adjustment values are set in the wobble single waveform unit and the wobble phase inversion unit, respectively. Specifically, when the phase inverting part gate signal is Low, that is, in the wobble single waveform part, control is performed by the first amplitude adjustment value 401, and when the phase inverting part gate signal 114s is High, that is, wobble. In the phase inversion unit, the control by the second amplitude adjustment value 402 is performed. Thereby, it is possible to adjust the signal amplitude to be optimum for each of the wobble single waveform portion and the wobble phase inversion portion.

(Embodiment 4)
FIG. 7 is a diagram showing a configuration of an address information detection circuit according to the fourth exemplary embodiment of the present invention. In the figure, the same components as those in FIG.
The address information detection circuit according to the fourth embodiment includes switching means 503 in addition to the configuration of the address information detection circuit shown in FIG.
The switching unit 503 sets at least two slice levels of the second digital filter output 8s and switches based on the phase inverter gate signal 114s. Here, it is assumed that either the first slice level 501 or the second slice level 502 is selected and output to the ADIP signal detection circuit 10.

Next, functions and effects of the fourth embodiment will be described.
Normally, as shown in FIG. 8A, the second digital filter output 8s is binarized using a predetermined slice level to obtain an ADIP binarized signal 11s. However, if noise is superimposed on the signal 8s, the ADIP signal may be erroneously detected.

  Therefore, in the present embodiment, as shown in FIG. 8B, when the phase inversion unit gate signal 114s is High, that is, in the wobble phase inversion unit, binarization is performed using slice level 1, and the phase inversion unit When the gate signal 114s is Low, that is, in the wobble single waveform portion, binarization is performed using slice level 2. Accordingly, since the slice level can be switched between the wobble single waveform portion and the wobble phase reverse portion by the phase inversion portion gate signal 114s, noise superimposed on the wobble single waveform portion is erroneously detected as an ADIP signal. It is possible to prevent the ADIP signal from being erroneously detected due to crosstalk from the adjacent clock.

(Embodiment 5)
FIG. 9 is a diagram showing a configuration of an address information detection circuit according to the fifth embodiment of the present invention. In the figure, the same components as those in FIG.
The address information detection circuit according to the fifth embodiment includes switching means 603 in addition to the configuration of the address information detection circuit in FIG.
The switching means 603 sets at least two gain values of the phase adjustment circuit 5 and switches based on the phase inverter gate signal 114s. Here, it is assumed that either the first gain 601 or the second gain 602 is selected and output to the phase adjustment circuit 5.

Next, functions and effects of the fifth embodiment will be described.
Based on the phase inverter gate signal 114s, the gain of the phase adjustment circuit 5 is switched so that the gain of the wobble phase inverter is set lower than that of the wobble single waveform section. As a result, it is possible to prevent the phase adjustment circuit 5 from responding to the opposite phase by inverting the phase at the wobble phase inverting unit.

  Further, the operation of the phase adjustment circuit 5 is not held by the wobble phase inverting unit. Thereby, even if the phase inverter gate signal 114s is deviated from the actual wobble phase inverter, the phase adjustment circuit 5 can be operated accurately.

  The DVD + RW type ADIP address information detection circuit according to the present invention has an ADIP signal discriminating means and is useful as a DVD + RW type recordable optical disk device for PC. It can also be used for DVD recorders.

It is a block diagram which shows the structural example of the address information detection circuit by Embodiment 1 of this invention. It is a figure which shows the detailed structure of the ADIP signal detection circuit which comprises the address information detection circuit of the said Embodiment 1. FIG. It is a figure which shows the signal waveform diagram in the address information detection circuit of the said Embodiment 1. FIG. It is a block diagram which shows the structural example of the address information detection circuit by Embodiment 2 of this invention. It is a block diagram which shows the structural example of the address information detection circuit by Embodiment 3 of this invention. It is a figure which shows the signal waveform figure in the said Embodiment 3. FIG. It is a block diagram which shows the structural example of the address information detection circuit by Embodiment 4 of this invention. It is a figure which shows the signal waveform figure in the said Embodiment 4. FIG. It is a block diagram which shows the structural example of the address information detection circuit by Embodiment 5 of this invention. It is explanatory drawing of an ADIP signal.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 AD converter 2 1st digital filter 3 Offset removal circuit 4 Carrier signal generation 5 Phase adjustment circuit 6 Latch signal generation circuit 7 Multiplier 8 Second digital filter 9 Gate signal generation circuit 10 ADIP signal detection circuit 101 Inversion of signal polarity Unit 102 First selector 103 Second selector 104 Adder 301 Digital filter first coefficient 302 Digital filter second coefficient 303 Switching means 404 Amplitude adjustment circuit 401 First amplitude adjustment value 402 Second amplitude adjustment Value 403 Switching means 501 First slice level 502 Second slice level 503 Switching means 601 First gain 602 Second gain 603 Switching means

Claims (7)

In an address information detection circuit of an optical disc apparatus for recording and reproducing data on an optical disc wobbled with a frequency component obtained by phase-modulating a pattern for synchronizing address information with a data recording track according to a predetermined rule,
An A / D converter for converting the wobble signal of the data recording track into a digital signal;
A first digital filter for shaping the waveform of the digitized wobble signal;
A generation circuit for generating a single carrier wave having the same frequency as the wobble signal;
A phase adjustment circuit that adjusts the phase of the single carrier wave generated by the generation circuit so as to be synchronized with the phase of the wobble signal;
A multiplier that multiplies the wobble signal output from the first digital filter by the single carrier wave output from the phase adjustment circuit and outputs the product as a phase modulation signal;
A second digital filter for removing a high frequency component of the phase modulation signal;
A gate signal generation circuit that generates a gate signal synchronized with the phase modulation unit of the phase modulation signal;
A discriminator for discriminating a phase modulation pattern from the output of the second digital filter;
The discriminator is
An adder for adding the output signal of the second digital filter according to the gate signal;
A selector for resetting the adder according to the gate signal;
An address information detection circuit characterized by the above. The address information detection circuit according to claim 1,
The optical disc is a DVD + RW or DVD + R optical disc,
The discriminator identifies whether the phase modulation signal is a sync pattern, a zero pattern, or a one pattern based on a phase modulation unit of the phase modulation signal;
An address information detection circuit characterized by the above. The address information detection circuit according to claim 2,
The gate signal generation circuit generates a gate signal and a reset signal for identifying the phase modulation pattern,
The discriminator includes a register that changes the number of bits to be added based on the gate signal, and resets the number of bits to be added when the reset signal is input.
An address information detection circuit characterized by the above. In an address information detection circuit of an optical disc apparatus for recording and reproducing data on an optical disc wobbled with a frequency component obtained by phase-modulating a pattern for synchronizing address information with a data recording track according to a predetermined rule,
An A / D converter that converts the wobble signal of the data recording track into a digital signal;
A first digital filter for shaping the waveform of the digitized wobble signal;
A generation circuit for generating a single carrier wave having the same frequency as the wobble signal;
A phase adjustment circuit that adjusts the phase of the single carrier wave generated by the generation circuit so as to be synchronized with the phase of the wobble signal;
A multiplier that multiplies the wobble signal output from the first digital filter by the single carrier wave output from the phase adjustment circuit and outputs the product as a phase modulation signal;
A second digital filter for removing the high frequency component of the phase modulation signal;
A gate signal generation circuit that generates a gate signal synchronized with the phase modulation unit of the phase modulation signal;
A discriminator for discriminating a phase modulation pattern from the output of the second digital filter;
Switching means for setting the coefficient of the first digital filter to at least two or more arbitrary values and switching the coefficient of the first digital filter based on the gate signal;
An address information detection circuit characterized by the above. In an address information detection circuit of an optical disc apparatus for recording and reproducing data on an optical disc wobbled with a frequency component obtained by phase-modulating a pattern for synchronizing address information with a data recording track according to a predetermined rule,
An A / D converter for converting the wobble signal of the data recording track into a digital signal;
A first digital filter for shaping the waveform of the digitized wobble signal;
An amplitude adjustment circuit for adjusting the amplitude of the output of the first digital filter to at least two kinds of amplitude adjustment values;
A generation circuit for generating a single carrier wave having the same frequency as the wobble signal;
A phase adjustment circuit that adjusts the phase of the single carrier wave generated by the generation circuit so as to be synchronized with the phase of the wobble signal;
A multiplier that multiplies the wobble signal output from the amplitude adjustment circuit by a single carrier wave output from the phase adjustment circuit and outputs it as a phase modulation signal;
A second digital filter for removing a high frequency component of the phase modulation signal;
A gate signal generation circuit that generates a gate signal synchronized with the phase modulation unit of the phase modulation signal;
A discriminator for discriminating a phase modulation pattern from the output of the second digital filter;
Switching means for switching an amplitude adjustment value to be adjusted by the amplitude adjustment circuit based on the gate signal;
An address information detection circuit characterized by the above. In an address information detection circuit of an optical disc apparatus for recording and reproducing data on an optical disc wobbled with a frequency component obtained by phase-modulating a pattern for synchronizing address information with a data recording track according to a predetermined rule,
An A / D converter for converting the wobble signal of the data recording track into a digital signal;
A first digital filter for shaping the waveform of the digitized wobble signal;
A generation circuit for generating a single carrier wave having the same frequency as the wobble signal;
A phase adjustment circuit that adjusts the phase of the single carrier wave generated by the generation circuit so as to be synchronized with the phase of the wobble signal;
A multiplier that multiplies the wobble signal output from the first digital filter by the single carrier wave output from the phase adjustment circuit and outputs the product as a phase modulation signal;
A second digital filter for removing a high frequency component of the phase modulation signal;
A gate signal generation circuit that generates a gate signal synchronized with the phase modulation unit of the phase modulation signal;
A discriminator for discriminating a phase modulation pattern from the output of the second digital filter;
An ADIP detection circuit for setting at least two slice levels for binarizing the output of the second digital filter and outputting it as an ADIP modulated signal;
Switching means for switching the slice level based on the gate signal;
An address information detection circuit characterized by the above. In an address information detection circuit of an optical disc apparatus for recording and reproducing data on an optical disc wobbled with a frequency component obtained by phase-modulating a pattern for synchronizing address information with a data recording track according to a predetermined rule,
An A / D converter for converting the wobble signal of the data recording track into a digital signal;
A digital filter for shaping the waveform of the digitized wobble signal;
A generation circuit for generating a single carrier wave having the same frequency as the wobble signal;
A phase adjustment circuit that adjusts the phase of the single carrier wave generated by the generation circuit so as to be synchronized with the phase of the wobble signal;
A multiplier that multiplies the wobble signal output from the first digital filter by the single carrier wave output from the phase adjustment circuit;
A second digital filter for integrating the output of the multiplier;
A gate signal generation circuit that generates a gate signal synchronized with the phase modulation unit from the phase modulation signal of the wobble signal;
Switching means for setting at least two gains in the phase adjustment circuit and switching based on the gate signal;
An address information detection circuit characterized by the above.

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