JP2008077706A - Optical disk apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an optical disk apparatus which reduces the circuit scale of an address decoder circuit. <P>SOLUTION: The apparatus is equipped with a detection circuit which detects a bit synchronization signal showing the timing synchronization of address bits and a word synchronization signal showing the timing synchronization of address words from a wobble signal read from an optical disk 1, and a timing signal generation circuit which generates a timing signal for decoding the address information of the optical disk based on the bit synchronization signal and the word synchronization signal and which is in common with two or more kinds of optical disks. Then, by setting a timing signal corresponding to the address format of the optical disk according to the discrimination result of the optical disk, the address information for the two or more kinds of optical disks is decoded. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an optical disc apparatus for recording or reproducing information on a plurality of types of optical discs, and more particularly to a technique for decoding address information of a plurality of different types of optical discs.

  In recent years, optical disk media have become widespread. Under such circumstances, there are also optical disk media having different address information recording formats. For example, DVD + R (Digital Versatile Disc + Recordable), DVD + RW (Digital Versatile Disc + Rewritable), DVD-R (Digital Versatile Disc-Recordable), etc. have different address information recording formats. Furthermore, DVD-RW (Digital Versatile Disc-Rewritable), BD (Blu-ray Disc), etc. also have different address information recording formats.

  In this specification, DVD + R and DVD + RW are collectively referred to as DVD + R / RW in the following description. DVD-R and DVD-RW are collectively referred to as DVD-R / RW.

  These DVD + R / RW, DVD-R / RW, and BD are provided with tracks formed by grooves called grooves formed on the flat surface (land) of the disc. This groove is formed to slightly meander (wobble), and wobble signals having different predetermined periods can be extracted from DVD + R / RW, DVD-R / RW, and BD.

  As shown in FIG. 9, the DVD + R / RW wobble signal is subjected to phase modulation corresponding to address information called PSK (Phase Shift Keying) for the predetermined period. Specifically, the sync signal is indicated by periodically inverting the wobble phase, and the address bits are expressed by changing the inverting position.

  As shown in FIG. 10, in the DVD-R / RW disc medium, areas including address information called land prepits (LPP) in addition to wobble are formed on the track at predetermined intervals. Specifically, a sync signal is indicated by periodically forming an LPP in an adjacent land of a wobble, and an address bit is indicated by changing the position where the LPP is formed.

  Further, as shown in FIG. 11, the BD wobble signal is subjected to phase modulation corresponding to address information called MSK (Minimum Shift Keying) for the predetermined period. Specifically, the sync signal is indicated by periodically inverting the wobble phase, and the address bits are expressed by changing the inverting position.

  Further, before and after the phase-inverted wobble, wobbles having a period of 1.5 times are arranged so that the joints are smoothed, and the high-frequency component is reduced in the entire wobble signal.

Patent Document 1 discloses a configuration having a plurality of independent address recorders (numbers 11, 13, and 15) for each format.
Japanese Patent Laid-Open No. 2002-50109

  As described above, the recording format of address information differs between DVD + R / RW, DVD-R / RW, and BD as disk media. Therefore, when decoding address information for these disk media, it is necessary to provide separate circuits for DVD + R / RW, DVD-R / RW, and BD, and the increase in circuit scale cannot be ignored.

  An object of the present invention is to provide an optical disc apparatus capable of reducing the circuit scale of an address decoder circuit.

  The present invention relates to a detection circuit that detects a bit sync signal indicating timing synchronization of address bits and a word sync signal indicating timing synchronization of address words from a wobble signal read from an optical disc, and based on the bit sync signal and the word sync signal. A timing signal generation circuit that generates a timing signal for decoding the address information of the optical disc and is common to the plurality of types of optical discs. Then, by switching the setting of the timing signal generating circuit according to the discriminating result of the optical disc, and setting the timing signal corresponding to the discriminated address format of the optical disc, a common timing signal generating circuit for a plurality of types of optical discs Is used to decode the address information.

  According to the present invention, since address information can be decoded by a common timing signal generation circuit for a plurality of types of optical discs, an increase in circuit scale can be suppressed without requiring a dedicated decoding circuit for the plurality of types of optical discs. . Further, not only the circuit scale can be suppressed, but also the chip area when the address decoding circuit and the like are integrated can be reduced. Therefore, the cost of the chip can be reduced, and the power consumption can be reduced by reducing the circuit scale.

  Next, the best mode for carrying out the invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a configuration of an embodiment of an optical disc apparatus according to the present invention.

  Although FIG. 1 mainly shows a circuit related to address decoding of an optical disc, other recording circuits and reproducing circuits necessary for recording and reproducing information, or servo control circuits such as tracking control and focus control are omitted. ing. In addition, circuits and mechanisms such as a controller that controls the entire apparatus and a spindle motor that rotates the optical disk are also omitted.

  In the present invention, the circuit portion surrounded by the thick line in FIG. 1, that is, the circuit portion including the wobble counter 12, the bit counter 13, the word counter 14, the timing generation circuit 16, and the address decoding result output circuit 15 is replaced with the address decoder circuit. It is called. A circuit portion including the wobble counter 12, the bit counter 13, the word counter 14, and the timing generation circuit 16 is called a timing signal generation circuit.

  In the figure, reference numeral 1 denotes an optical disk as an information recording medium. As the optical disc, for example, any of DVD + R / RW, DVD-R / RW, and BD can be used. Address information and the like are recorded on these optical disks by wobbling the tracks as described above.

  The optical head 2 irradiates the optical disc 1 with laser light, and records or reproduces information on the optical disc 1. The optical head 2 receives reflected light from the optical disc 1 by an internal optical sensor. Based on this light reception signal, a wobble signal indicating address data recorded on the optical disc 1 and a reproduction signal indicating recording data are generated.

  When the DVD + R / RW is used as the optical disc 1, the PSK demodulator circuit 3 takes in the wobble signal read from the optical disc 1 by the optical head 2 and generates binary data that is PSK demodulated. Specifically, by multiplying a wobble signal by a SIN wave having the same frequency as that of a wobble signal called a carrier and having the same phase, a modulation component can be detected only at a PSK modulated portion. This modulation component is converted into a binary signal.

  The PSK_SYNC detection circuit 6 detects a bit sync signal and a word sync signal from the binarized data output from the PSK demodulation circuit 3. The detected bit sync signal is output to the subsequent bit sync selector 9, and the word sync signal is output to the word sync selector 10. The bit sync signal is a signal indicating timing synchronization of address bits, and the word sync signal is a signal indicating timing synchronization of address words.

  When the DVD-R / RW is used as the optical disk 1, the LPP detection circuit 4 takes in the wobble signal read from the optical disk 1 by the optical head 2 and generates binary data of the LPP signal. That is, the LPP signal attached to the position of −90 ° of the wobble signal is converted into a binary signal with a predetermined threshold.

  The LPP_SYNC detection circuit 7 detects a bit sync signal and a word sync signal from the binarized data output from the LPP detection circuit 4. The detected bit sync signal is output to the bit sync selector 9, and the word sync signal is output to the word sync selector 10.

  When the BD is used as the optical disc 1, the MSK demodulation circuit 5 takes in the wobble signal read from the optical disc 1 by the optical head 2 and generates binary data that is MSK demodulated. Specifically, when a COS wave having the same frequency as the wobble signal called a carrier and having the same phase is multiplied by the wobble signal, the modulation component can be detected only at the MSK modulated portion. This modulation component is converted into a binary signal.

  The MSK_SYNC detection circuit 8 detects a bit sync signal and a word sync signal from the binarized data output from the MSK demodulation circuit 5. The detected bit sync signal is output to the bit sync selector 9, and the word sync signal is output to the word sync selector 10.

  The disc discriminating circuit 11 discriminates the type of the optical disc 1 based on the wobble frequency difference from the wobble PLL 17. The discriminating result of the disc discriminating circuit 11 is output to the bit sync selector 9, the word sync selector 10, the wobble counter 12, the bit counter 13, the word counter 14, the address decode result output circuit 15, and the timing generation circuit 16.

  The wobble counter 12 counts the number of wobbles included in the bit sync signal (one wobble cycle). A clock synchronized with the wobble signal is supplied from the wobble PLL 17 to the wobble counter 12.

  The bit counter 13 is a counter that counts a bit sync signal included between word sync signals, and the word counter 14 is a counter that counts a word sync signal, nibbie, and the like included between address information. In these counters 12, 13, and 14, the maximum count value is set according to the determination result of the disk determination circuit 11. Note that the maximum count value in each counter is set by a count value setting circuit (not shown) in the disc discrimination circuit 11. Of course, you may set from the controller which is not illustrated.

  The timing generation circuit 16 outputs a timing signal for address decoding to the address decoding result output circuit 15 in accordance with the outputs of the disk discrimination circuit 11, the wobble counter 12, the bit counter 13, and the word counter 14. Since the timing signal of the timing generation circuit 16 may change depending on the type of the optical disc, the type of the optical disc is notified.

  The address decoding result output circuit 15 selects an output signal corresponding to the type of the optical disc from the PSK demodulating circuit 3, the LPP detecting circuit 4 and the MSK demodulating circuit 6 in accordance with the disc discriminating result of the disc discriminating circuit 11. Then, the address information of DVD + R / RW, DVD-R / RW, and BD is decoded according to the timing signal from the timing generation circuit 16.

  FIG. 2 is a timing chart for explaining the address decoding operation when the discrimination result of the disc discrimination circuit 11 is DVD + R / RW. 2A is a bit sync signal, FIG. 2B is a count value of the wobble counter 12, FIG. 2C is a word sync signal, FIG. 2D is a count value of the bit counter 13, and FIG. ) Indicates the count value of the word counter 14.

  If the discriminating result of the disc discriminating circuit 11 is DVD + R / RW, the bit sync selector 9 outputs the bit sync signal from the PSK_SYNC detecting circuit 6 to the wobble counter 12. The wobble counter 12 resets the count value to 0 with a bit sync signal.

  The word sync selector 10 outputs the word sync signal from the PSK_SYNC detection circuit 6 to the bit counter 13 and the word counter 14. The bit counter 13 and the word counter 14 reset the count value to 0 with a word sync signal. Further, the bit counter 13 increments the count value with the carry of the wobble counter 12. The word counter 14 increments the count value with the carry of the bit counter 13.

  FIG. 3 is a timing chart for explaining the address decoding operation when the discrimination result of the disc discrimination circuit 11 is DVD-R / RW. 3A is a bit sync signal, FIG. 3B is a count value of the wobble counter 12, FIG. 3C is a word sync signal, FIG. 3D is a count value of the bit counter 13, and FIG. ) Indicates the count value of the word counter 14.

  When the discriminating result of the disc discriminating circuit 11 is DVD-R / RW, the bit sync selector 9 outputs the bit sync signal from the LPP_SYNC detecting circuit 7 to the wobble counter 12. The wobble counter 12 resets the count value to 0 with a bit sync signal.

  The word sync selector 10 outputs the word sync signal from the LPP_SYNC detection circuit 7 to the bit counter 13. The bit counter 13 and the word counter 14 reset the count value to 0 with a word sync signal. Further, the bit counter 13 increments the count value with the carry of the wobble counter 12. The word counter 14 increments the count value with the carry of the bit counter 13.

  FIG. 4 is a timing chart for explaining the address decoding operation when the discriminating result of the disc discriminating circuit 11 is BD. 4A is a bit sync signal, FIG. 4B is a count value of the wobble counter 12, FIG. 4C is a word sync signal, FIG. 4D is a count value of the bit counter 13, and FIG. ) Indicates the count value of the word counter 14.

  If the discriminating result of the disc discriminating circuit 11 is BD, the bit sync selector 9 outputs the bit sync signal from the MSK_SYNC detection circuit 8 to the wobble counter 12. The wobble counter 12 resets the count value to 0 with a bit sync signal.

  The word sync selector 10 outputs the word sync signal from the MSK_SYNC detection circuit 8 to the bit counter 13 and the word counter 14. The bit counter 13 and the word counter 14 reset the count value to 0 with a word sync signal. Further, the bit counter 13 increments the count value with the carry of the wobble counter 12. The word counter 14 increments the count value with the carry of the bit counter 13.

  Next, the address decoding operation when the optical disc 1 is DVD + R / RW will be described in detail. FIG. 5 shows an address format when the optical disc 1 is DVD + R / RW.

  When disc discriminating circuit 11 discriminates that optical disc 1 is DVD + R / RW, it sets the maximum count value in each counter as shown in FIG. FIG. 6 shows the maximum count values set in the wobble counter 12, the bit counter 13, and the word counter 14 in DVD + R / RW, DVD1-R / RW, and BD optical discs.

  Further, the disc discrimination circuit 11 notifies the discriminating result of the optical disc to each selector, each counter, the timing generation circuit 16 and the address decoding result output circuit 15 as described above.

  When the optical disk is DVD + R / RW, as shown in FIG. 6, since 93 wobbles between bit sync signals are counted in the wobble counter 12, a maximum count value 92 is set. The bit counter 13 counts the bit sync signal in nibble units, so the maximum count value 3 is set. Since the word counter 14 counts 13 nibbies between the address information, the maximum count value 12 is set.

  The timing generation circuit 16 outputs a timing signal to the address decode result output circuit 15 according to the count value of the wobble counter 12, the count value of the bit counter 13, and the count value of the word counter 14 shown in FIG. The address decode result output circuit 15 decodes the address information from the PSK_demodulation circuit 3 according to the timing signal from the timing generation circuit 16.

  Specifically, the timing generation circuit 16 outputs an address decoding start signal at the timing “0” of the wobble counter 12, the bit counter 13, and the word counter 14.

  The address decoding result output circuit 15 starts decoding the address information from the PSK demodulating circuit 3 during the period when the count value of the word counter 14 is “0” as shown in FIG. At this time, as shown in FIG. 2D, the address information from the PSK demodulator circuit 3 is sequentially decoded according to the count values ‘0’, ‘1’, ‘2’ and ‘3’ of the bit counter 13.

  Here, the address decoding result output circuit 15 detects an address bit according to the count value of the wobble counter 12 shown in FIG. In this case, as shown in FIG. 2B, when the count value of the wobble counter 12 is “4-7”, when the output of the PSK demodulator circuit 3 is “1100” as shown in FIG. Set to '1'.

  Similarly, when the output of the PSK demodulating circuit 3 is “0011”, the address bit is set to “0”. The address decode result output circuit 15 collects the data of the address bits “0” and “1” in nibble units and outputs them as address data.

  When the address information is decoded until the count value of the bit counter 13 is “3” during the period when the count value of the word counter 14 is “0”, the count of the bit counter 13 is similarly performed during the period when the count value of the word counter 14 is “1”. Address bits having values from “0” to “3” are detected. Similarly, the address bits are detected according to the count value of the bit counter 13 until the count value of the word counter 14 becomes “12”.

  Next, address decoding when the optical disc 1 is a DVD-R / RW will be described in detail. FIG. 7 shows an address format when the optical disc 1 is a DVD-R / RW.

  When disc discriminating circuit 11 discriminates that the optical disc is DVD-R / RW, it sets the maximum count value in each counter as shown in FIG. That is, since the wobble counter 12 counts eight wobbles between the bit sync signals, the maximum count value 7 is set.

  Since the bit counter 13 counts 13 bit sync signals between the word sync signals, the maximum count value 12 is set. Since the word counter 14 counts 16 word sync signals between the address information, a maximum count value 15 is set.

  Similarly, the disc discrimination circuit 11 notifies each selector, each counter, the timing generation circuit 16 and the address decode result output circuit 15 of the disc discrimination result.

  Similarly, the timing generation circuit 16 outputs a timing signal to the address decode result output circuit 15 according to the count value of the wobble counter 12, the count value of the bit counter 13, and the count value of the word counter 14 shown in FIG. The address decode result output circuit 15 decodes the address information from the LPP detection circuit 4 according to the timing signal from the timing generation circuit 16.

  Specifically, the timing generation circuit 16 outputs an address decoding start signal at the timing “0” of the wobble counter 12, the bit counter 13, and the word counter 14.

  As shown in FIG. 3 (e), the address decode result output circuit 15 has a count value “0”, “1” of the bit counter 13 as shown in FIG. 3 (d) during a period when the count value of the word counter 14 is “0”. Address information from the LPP detection circuit 4 is decoded in accordance with “...,“ 12 ”.

  Here, the address decoding result output circuit 15 decodes the address information from the LPP detection circuit 4 in accordance with the count value of the wobble counter 12 shown in FIG. At this time, as shown in FIG. 10, when the count value of the wobble counter 12 is “0 to 2” and the output of the LPP detection circuit 4 is “101”, the address bit is set to “1”.

  Similarly, when the output of the LPP detection circuit 4 is “100”, the address bit is set to “0”. The address decode result output circuit 15 collects the data of the address bits “0” and “1” in units of bytes and outputs them as address data (address bits shown in FIG. 7).

  When address bits are detected until the count value of the bit counter 13 reaches “12” while the count value of the word counter 14 is “0”, the count of the bit counter 13 is similarly detected during the period when the count value of the word counter 14 is “1”. Address bits having values from “0” to “12” are detected. Similarly, the address bits are detected according to the count value of the bit counter 13 until the count value of the word counter 14 becomes ‘15’.

  Next, an address decoding operation when the optical disc 1 is a BD will be described in detail. FIG. 8 shows an address format when the optical disc is a BD.

  If the disc discriminating circuit 11 discriminates that the disc is a BD, the maximum count value is set in each counter as shown in FIG. That is, as shown in FIG. 6, since 56 wobbles between the bit sync signals are counted in the wobble counter 12, a maximum count value 55 is set.

  The bit counter 13 counts 8 (= (Monotone (1) + Sync (1)) × 4) when the word counter 14 is 0. When the word counter 14 is other than 0, 5 (= (Reference (1) + Data (4))) is counted. Therefore, the maximum count value 7 is set in the bit counter 13 when counting 8 and the maximum count value 4 is set when counting 5.

  The word counter 14 counts the word sync signal (1) and nibbie (15) between the address information, so the maximum count value 15 is set. Accordingly, as shown in FIG. 4, when the count value of the word counter 14 is “0”, the count value of the bit counter 13 is “0” to “7”. When the count value of the word counter 14 is other than “0”, the count value of the bit counter 13 is “0” to “4”.

  Similarly, the disc discrimination circuit 11 notifies each selector, each counter, the timing generation circuit 16 and the address decode result output circuit 15 of the disc discrimination result.

  The timing generation circuit 16 outputs a timing signal to the address decode result output circuit 15 according to the count value of the wobble counter 12, the count value of the bit counter 13, and the count value of the word counter 14 shown in FIG. The address decode result output circuit 15 decodes the address information from the MSK demodulation circuit 5 according to the timing signal from the timing generation circuit 15.

  Specifically, the timing generation circuit 16 similarly outputs an address decoding start signal at the timing “0” of the wobble counter 12, the bit counter 13, and the word counter 14.

  The address decoding result output circuit 15 decodes the address information from the MSK demodulating circuit 5 in accordance with the count values “0” to “7” of the bit counter 13 while the count value of the word counter 14 is “0”. Incidentally, the period when the count value of the bit counter 13 is “0” corresponds to (Monotone (1) + Sync (1) × 4) as described above (see FIG. 8).

  The address bit is detected after the count value of the word counter 14 is "1" or later. At this time, the address information from the MSK demodulating circuit 5 is decoded according to the count values “0” to “4” of the bit counter 13.

  In that case, the address decoding result output circuit 15 decodes the address information from the MSK demodulation circuit 5 according to the count value of the wobble counter 12 shown in FIG. At this time, as shown in FIG. 11, when the count value of the wobble counter 12 is ‘13’ and the output of the MSK demodulation circuit 5 is ‘1’, the address bit is set to ‘1’.

  Similarly, when the count value of the wobble counter 12 is “16” and the output of the MSK demodulation circuit 5 is “1”, the address bit is set to “0”. The address decode result output circuit 15 collects the data of the address bits “0” and “1” in nibble units and outputs them as address data. Similarly, the address bits are detected according to the count value of the bit counter 13 until the count value of the word counter 14 becomes ‘15’.

  In this embodiment, the maximum count values of the wobble counter 12, the bit counter 13, and the word counter 14 are switched according to the type of the optical disc as described above. By switching the timing signal for decoding the address information in accordance with the address format of the optical disk, it becomes possible to perform address decoding of a plurality of types of optical disks using an address decoding circuit with a reduced circuit scale.

1 is a block diagram showing an embodiment of an optical disc apparatus according to the present invention. 10 is a timing chart for explaining an address decoding operation when the optical disc is DVD + R / RW. 6 is a timing chart for explaining an address decoding operation when the optical disc is a DVD-R / RW. 10 is a timing chart for explaining an address decoding operation when the optical disc is a BD. It is a figure which shows the address format of DVD + R / RW. It is a figure which shows the count maximum value of a wobble counter, a bit counter, and a word counter corresponding to the kind of optical disk. It is a figure which shows the address format of DVD-R / RW. It is a figure which shows the address format of BD. It is a figure which shows the wobble format of DVD + R / RW. It is a figure which shows the wobble format of DVD-R / RW. It is a figure which shows the wobble format of BD.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Optical disk 2 Optical head 3 PSK demodulation circuit 4 LPP detection circuit 5 MSK demodulation circuit 6 PSK_SYNC detection circuit 7 LPP_SYNC detection circuit 8 MSK_SYNC detection circuit 9 Bit sync selector 10 Word sync selector 11 Disk discrimination circuit 12 Wobble counter 13 Bit counter 14 Word counter 14 15 Address decode result output circuit 16 Timing generation circuit 17 Wobble PLL

Claims (3)

In an optical disc apparatus for recording or reproducing information on a plurality of types of optical discs having different address formats,
Discriminating means for discriminating the type of the optical disc;
A detection circuit for detecting a bit sync signal indicating timing synchronization of address bits and a word sync signal indicating timing synchronization of address words from a wobble signal read from the optical disc;
A timing signal generation circuit common to the plurality of types of optical discs, which generates a timing signal for decoding address information of the optical disc based on the bit sync signal and the word sync signal;
Means for switching the setting of the timing signal generation circuit according to the determination result of the determination means, and setting the timing signal corresponding to the address format of the optical disc determined by the determination means;
And a circuit for outputting address data of the optical disc in accordance with a timing signal from the timing signal generation circuit. The timing signal generation circuit includes a wobble counter that counts wobble signals between the bit sync signals, a bit counter that counts bit sync signals between the word sync signals, and a word counter that counts the word sync signals or nibbies. 2. The optical disc according to claim 1, wherein a timing signal corresponding to an address format of the optical disc is set by switching a maximum count value set in each counter according to a discrimination result of the discrimination means. apparatus. The optical disc apparatus according to claim 1 or 2, wherein the discriminating unit discriminates the type of the optical disc based on a difference in wobble frequency of a wobble signal of the optical disc.