KR20090031660A - Jitter detecting method and apparatus - Google Patents

Abstract

The present invention provides an improved jitter detection device capable of performing jitter detection.

The jitter detecting device for this purpose includes a receiving circuit 1 for receiving a signal, a determining circuit 3 for determining a signal portion used for jitter detection in the received signal based on the signal amplitude, and the determined signal portion. And jitter detection circuit 5 for detecting jitter related to the signal. The determination circuit 3 uses a first threshold setting circuit for generating a first threshold value, a second threshold setting circuit for generating a second threshold value, and the first and second threshold values for a period of time. A period signal generation circuit for generating a signal may be included, and the jitter detection circuit 5 may include a signal portion detection circuit for detecting a signal portion by responding to a received signal according to the period signal.

Description

JITTER DETECTING METHOD AND APPARATUS

This application claims the priority based on Japanese Patent Application No. 2006-180702 of a "method and apparatus for detecting jitter" of the application on June 30, 2006, The specification, drawings, claims The entire beginning disclosure is incorporated into the text.

The disclosed embodiment relates to a method and apparatus for detecting jitter in a signal.

Conventionally, reading of data recorded on an optical disc such as a CD or a DVD is performed by digitalizing a reproduction signal from the optical disc and binarizing the reproduction signal from the optical disc, for example, as disclosed in Japanese Patent Laid-Open No. 2004-295965. This is done by detecting the length of each mark or space. In the binarization for data reading, for example, the median value of the peak peak of the reproduction signal is usually used as the slice level for the reproduction signal from the conventional DVD shown in Fig. 1 (b). The detection of jitter in the digital signal from the optical disk thus detected is also performed using the same slice level as the data detection. That is, using the slice level which is the intermediate value of the peak peak of the reproduction signal, the reproduction signal from the DVD is binarized, for example, the length of each mark / space in the digital signal after binarization is detected, and the variation in this length is varied. Jitter is measured by examining. For example, in the case of a DVD, there is a mark / space having a period of 3T to 11T and 14T. Here, T is equal to one period of the clock used for the DVD. In this way, by measuring the jitter in the signal from the optical disk, the quality of the optical disk itself was checked or the optical axis of the optical beam in the optical pickup was adjusted.

Recently, as an optical disc, a new optical disc standard such as HD (High-Definition) DVD has emerged. In such an optical disc, the recording density is further increased as compared with the conventional DVD. For example, in HD DVD, an ETM code (Eight to Twelve Modulation Code) is used, and the reproduction signal therefrom is a waveform as shown in Fig. 1A. As can be seen when comparing with the reproduction signal from the DVD using the conventional EFM code of Fig. 1 (b), there are some smaller components of the signal amplitude, and the components with the smallest amplitude peak near the slice level. Have This is because the higher the recording density, the lower the signal amplitude due to inter-signal interference, and the higher the linear density, the lower the signal amplitude. For example, at the shortest 2T mark or the length of the space, the peak p of the signal amplitude is near the slice level. In the case of reading data from an optical disc causing such a reproduction signal, in the binarization method using a slice level as in the prior art, many identification errors occur even in the vicinity of the slice level, so that stable data detection is difficult. Therefore, in the HD DVD standard, it is decided to use a PRML (Partial Response and Maximum Likelihood) signal processing method as a data reading method. Accordingly, the reproduction signal evaluation method is also evaluated not by jitter but by SbER (Simulated Bit Error Rate) and PRSNR (Partial Response Signal to Noise).

However, in the method of evaluating such SbER and PRSNR, since a large number of samples is required in comparison with the jitter measurement, the real time is low as compared with the method using a conventional slice level. For this reason, in the production site of the optical disc related products, an adjustment operation such as an optical axis adjustment step of the optical pickup is required, but in such an adjustment operation, a constant number of samples preset for evaluation by SbER or PRSNR is required for each fine adjustment. There is a problem that the adjustment takes time. This also causes a problem that the production efficiency as a whole product is lowered.

Various aspects and embodiments described below will be described and described with respect to devices, circuits, and methods, but these are merely illustrative and are not meant to limit the scope. In various embodiments, one or more of the above problems are alleviated or eliminated, but there are other embodiments for use for other improvements.

In one embodiment, the jitter detection method includes a step of receiving a signal, a determination step of determining a signal portion used for jitter detection in the received signal based on a signal amplitude, and based on the determined signal portion And detecting jitter in the signal.

In another embodiment, the jitter detection device includes a reception circuit for receiving a signal, a decision circuit for determining a signal portion used for jitter detection in the received signal based on a signal amplitude, and the above determination. And a jitter detection circuit for detecting jitter related to the signal based on the signal portion.

In addition to the exemplary embodiments and aspects described above, other embodiments and aspects will become apparent to those skilled in the art upon reviewing the following description with reference to the drawings.

1 (a) is a diagram showing a waveform example of a reproduction signal from an HD DVD;

1B is a diagram showing an example waveform of a reproduction signal from a DVD;

2 is a block diagram showing the configuration of a jitter detection device according to one embodiment;

FIG. 3 is a diagram showing a relationship between various signal components included in an HD DVD playback signal, and slice levels, upper threshold values, and lower threshold values thereof.

FIG. 4 is a diagram for explaining, in principle, a method of determining a signal portion used for jitter detection in an HD DVD playback signal, in which (a) shows the case of clear crossing; FIGS. 4 (b-1) and (b). -2) is a figure showing a case of a return type non-clear crossing, 4 (c-1) and (c-2) is a figure showing a case of a non-return type non-clear crossing,

FIG. 5 is the same view as FIG. 4, wherein (d) shows a case where non-return non-clear crossing is continuous.

6 is a block diagram showing a jitter detection device of one embodiment incorporating the determination principle described in FIGS. 4 and 5;

7 is a timing diagram showing signal waveforms of respective units in the apparatus of FIG. 6;

FIG. 8 is a timing diagram showing signal waveforms of respective parts in the apparatus of FIG. 6 in the case where the non-return type non-clear crossing shown in FIG. 5 occurs continuously; FIG.

9 is a flowchart of a program for realizing the same function as that performed by the mask signal generator 30 of FIG.

FIG. 10 is a block diagram showing another embodiment of the jitter detection circuit in the jitter detection device shown in FIG. 2;

FIG. 11 is a block diagram showing another embodiment of the jitter detection circuit in the jitter detection device shown in FIG. 2;

12 is a diagram showing a jitter measuring device having a jitter detecting device of one embodiment;

FIG. 13 is a diagram illustrating an electronic device including the jitter detection device of one embodiment. FIG.

Next, various embodiments will be described in detail with reference to the drawings.

2 is a block diagram showing the configuration of a jitter detection device according to one embodiment. As shown in the drawing, the jitter detecting device includes a receiving circuit 1, a signal portion determining circuit 3, and a jitter detecting circuit 5. As shown in FIG. Specifically, the reception circuit 1 receives signals from an information recording medium such as an optical disc or from a communication medium such as a communication line or a network at an input terminal, and processes necessary for the received signal (for example, automatic gain control). (AGC), equalization process, or the like] is output to the output terminal. The signal portion determination circuit 3 has an input for receiving a received signal supplied from the output of the receiver circuit 1, and determines the signal portion used for jitter detection in the received signal based on the signal amplitude, The judgment result is output to the output. The jitter detection circuit 5 has an input for receiving a reception signal supplied from the output of the reception circuit 1 and an input for receiving a determination result supplied from the output of the signal portion determination circuit 3. As a result, the jitter detection circuit 5 detects jitter related to the received signal based on the determined signal portion.

More specifically, the signal portion determination circuit 3 includes an upper threshold setting circuit for generating an upper threshold THU, which is a first threshold, and a lower side for generating a lower threshold THL, which is a second threshold. The threshold value setting circuit and the period signal generation circuit which generate a period signal using these upper and lower threshold values can be comprised. At this time, the jitter detecting circuit 5 can be configured to include a signal portion detecting circuit for detecting the signal portion by responding to the received signal in accordance with the period signal. According to this embodiment, jitter detection can be performed at a speed and accuracy practically sufficient even for reproduction signals from a high density optical disc such as HD DVD. Moreover, according to this embodiment, jitter detection can be performed with a simple structure.

Here, with reference to FIG. 3, those upper threshold value THU and lower threshold value THL are demonstrated. For example, assuming that the received signal is a reproduction signal from an HD DVD, the reproduction signal becomes a waveform as shown in FIG. 3, for example. At this time, when the intermediate value of the peak peak of the reproduction signal is set to zero level, the reproduction signal includes signal components c1 to c13 having positive (+) or negative (-) peaks. Here, in the waveform example shown, the component having the largest positive or negative peak is c1, c2, c5, c13, and the component having the next lowest peak is c8, and the component having the lower peak is c4, c11, and the minimum peak components are c3, c6, c7, c9, c10, c12.

In this case, assuming that the illustrated zero level is binarized as the slice level, the component having the smallest peak has a very high probability of generating an identification error in c3, c6, c7, c9, c10, and c12. Moreover, the probability of the identification error of the component adjacent to these minimum peak components also increases. For example, considering the component c3, the identification error of the mark / space length occurring in the component c3 directly affects the data length in the adjacent components C2 and C4, so that the probability of the identification error is also reduced. Increases. Therefore, in the jitter detection device of one embodiment, the jitter detection of the signal is performed based on the signal portion where the occurrence probability of the identification error of the mark / space length is not high. For this reason, identification of the part with a high probability of occurrence of an identification error and the part which is not, based on signal amplitude is performed. As an example, the upper threshold value THU and the lower threshold value THL are determined for the zero level to determine a signal portion where the probability of identification error is not high, and the slice level is zero level as in the conventional jitter detection method. As a result, a method of binarizing and detecting jitter is employed. Thereby, high speed similar to the conventional jitter detection method can be realized.

Here, the setting method of the upper threshold value THU and the lower threshold value THL will be described in more detail. For example, if these thresholds are set at the positions of the dotted lines, the components (c3, c6, c7, c9, cl0, c12) of the minimum peak and components other than this can be identified in this case. Further, for example, if the upper threshold value THU is set at the positions THU 'and THL' indicated by a dashed-dotted line, the signal portion including the minimum peak component and the components having the next lowest peak (c4, c1l) and the same Other parts can be identified. In the example of the reproduction signal from the HD DVD, when the component of the shortest mark / space length of 2T is excluded from the determination object, those thresholds are larger than the peak of the 2T component but smaller than the peak of the next long 3T component. Level, for example, THU and THL. When not only 2T but also 3T or longer periods, for example, 5T components are to be excluded, the threshold is larger than the peak of 5T, but smaller than the peak of the 6T component, for example, THU 'and THL'. You can set it at the same level. Thus, the magnitude | size of an upper threshold value and a lower threshold value can be set to predetermined value, or it can continuously change according to the periodic component to be excluded from a determination object.

Next, referring to Figs. 4 and 5, the principle of the determination method of the signal portion used for jitter detection will be described using an HD DVD playback signal as an example. In this example, the threshold value is set for the purpose of eliminating the shortest signal component of 2T. In these figures, the waveform of a signal related to a coded signal (data recorded on an optical disc), a waveform of a reproduction signal from the optical disc below it, and a threshold used for determination is shown at the top. First, Fig. 4 (a) shows an example of "clear crossing" in which the reproduction signal crosses the slice level to clear on both sides, and (b-1) and (c-1) show the slice level on both sides. An example of "non-clear cross" intersecting with non-clear is shown. The example of crossing the slice level on the negative side is shown in Figs. 4B-2 and 4-2 for the case of non-clear crossing. Incidentally, "cross to clear" or "clear cross" means that the occurrence of the identification error is not high, and "cross to non-clear" or "non-clear cross" is the probability of occurrence of identification error. It is used as showing the intersection in this high state.

Referring first to Fig. 4A, when components of a period longer than 2T are continuous, for example, the slice level crosses the clear at the time t2 from both sides to the negative side, and a clear crossing point cr1 occurs. In this case, the probability of occurrence of identification error at the position crossing the slice level is low. Here, the "upper threshold crossing" signal rises when the reproduction signal crosses the upper threshold THU when the reproduction signal changes from zero level to both sides, and changes from both sides to the zero level side to cross the threshold value. It is said to descend. On the other hand, the "lower threshold crossing" signal rises when the reproduction signal crosses the lower threshold THL when the reproduction signal changes from the zero level to the more negative side, and changes from the negative side to the zero level side to cross the threshold value. It is said to descend. The "upper mask" signal is a signal for excluding a signal portion having a high probability of identifying error, and is mainly a signal generated based on an upper threshold value, while the "lower mask" signal has a similar probability of identifying error. As a signal for excluding this high signal portion, the signal is mainly generated based on the lower threshold. In the case of the clear crossing of Fig. 4A, the reproduction signal crosses the lower threshold on the opposite side at a predetermined time, for example, at time t3 within a time of 2T, at the time t1 when the upper threshold crosses the upper threshold. In this case, since the probability of identification error occurrence is not high, it stops low because neither the upper nor the lower mask needs to be generated.

On the other hand, as shown in Fig. 4B-1, when one 2T component continues after a periodic component longer than 2T, the reproduction signal passes the upper threshold on both sides, but crosses the slice level, A non-clear crossover occurs, returning from the vicinity and returning to both sides without reaching the lower threshold. That is, the non-clear crossing points cr2 and cr3 are continuous. In this case, it is called a "return type" non-clear crossing because it enters both sides and exits the slice level. At this time, when the upper threshold crossing signal becomes low, the lower threshold crossing signal does not become high within the time of 2T. In this case, since a portion having a high probability of identifying error occurs and enters from the upper side with respect to the slice level, the upper mask signal rises high to start the mask signal. In this way, it is possible to distinguish between the clear crossing of (a) and the non-clear crossing of (b-1) by whether the lower threshold crossing signal becomes high within the time of 2T. In addition, although FIG.4 (b-1) showed about the case of one 2T component, it is suitable also in the other cases where an odd number of 2T components are continued.

On the other hand, as shown in Fig. 4 (c-1), when two 2T components are continued after a periodic component longer than 2T, the reproduction signal passes the upper threshold on both sides and near the slice level. A non-clear crossing occurs that changes and passes through the lower threshold after repeating the slice level crossing. That is, the non-clear crossing points cr4, cr5, cr6 and cr7 are continuous. In this case, since it enters into the slice level from both sides and goes out to the negative side, it is called "non-returning" non-clear crossing. At this time, the lower threshold crossing signal does not become a high level within the time of 2T from the time when the upper threshold crossing signal becomes low, but becomes high after the passage of the 2T time. Also in this case, since a portion having a high probability of identifying error occurs and enters from the upper side with respect to the slice level, the upper mask signal rises high to start the mask signal. In this way, it is possible to distinguish between the clear crossing of (a) and the non-clear crossing of (c-1) by whether the lower threshold crossing signal becomes high within the time of 2T.

In the case of Fig. 4 (b-1) and (c-1), the mask signal once started is continued until a clear crossover as shown in Fig. 4 (a) occurs, and immediately before the slice level is crossed. For example, it terminates at the time which crosses an upper threshold (t1 of FIG. 4 (a)). Thereby, all the periodic components affected by the identification error which arise in the shortest periodic component can be excluded from a jitter determination object. Specifically, in the case of Fig. 4 (c-1), since two 2T periodic components are followed by a periodic component cx longer than 2T, the clear intersection point cr8 at t5 in this periodic component cx is continued. This is happening. However, the clear crossover here is from the negative side to the both side, which is opposite to the polarity of the regeneration signal immediately before the mask is started. Therefore, when the upper mask is terminated at the time t4 immediately before t5, the regeneration signal of the masked result is obtained. Since? Causes a state change immediately after the time t4, the slice level crossing due to the mask occurs. The slice level crossing due to such a mask does not have to occur in jitter detection. Therefore, in Fig. 4C-1, the mask is terminated at the same polarity side, that is, at the threshold crossing time of both sides, for example, at t6 or t7. However, the condition is that clear crossover as shown in Fig. 4A occurs immediately after t7. In addition, in FIG.4 (c-1), although the case where two 2T components are continued is shown, the case where even number other than two is continued is similarly suitable.

Next, Fig. 5 (d) shows that when a non-return type non-clear crossing is continuous, that is, two components having a length longer than 2T are continued after two consecutive 2T components, and then two 2T components are continued again. The case is shown. In this case, unlike in the case of Fig. 4 (c-1), the clear intersection is between the four consecutive non-clear crossing points cr10 to cr13 and the next four non-clear crossing points cr14 to cr17. It does not occur and the clear crossing point cr18 occurs at t10 following the latter clear crossing point. Also in this case, after the upper mask signal becomes high at t8, the same clear crossover as in FIG. 4 (a) occurs at t10, and therefore remains high until immediately before t9.

In addition, although not shown in the figure, in the case where the return-type non-clear crossing is continuous, it can be dealt with by processing in the same manner as in FIG. 4 (b-1).

Next, with reference to FIG. 6, the jitter detection apparatus of one Embodiment which actualized the determination principle demonstrated in FIG. 4 and FIG. 5 is demonstrated. As shown, this jitter detecting apparatus corresponds to the receiving circuit 1 of FIG. 2 and includes an automatic gain control circuit (AGC) 10 and an equalizer (EQ) 12, and the jitter detecting circuit ( A counter signal 5) is provided with a binarization circuit 50, a latch 52 and a jitter determination circuit 54, and a mask signal generator 30 as a counterpart of the signal portion determination circuit 3 is provided. Differences from the conventional jitter detection device will be described briefly. In the jitter detection device of the present embodiment, the circuit portion including the AGC 10, the binarization circuit 50, and the jitter determination circuit 54 is conventional. Similar to the DVD, the jitter detection is performed using the slice level. On the other hand, the equalizer 12 is a circuit for performing an equalization process peculiar to the reproduction signal from the HD DVD, the latch 52 is a circuit for extracting the signal portion, and the mask signal generator 30 is It is a circuit that generates a signal for determining the signal portion, and the point provided with these circuits 12, 52, and 30 differs from the conventional jitter detection device.

In detail, the AGC 10 controls the peak peak value of the playback signal to be constant by automatically controlling the playback signal from the HD DVD. The equalizer 12, which receives the signal from the AGC 10, performs processing for matching this reproduced signal from the HD DVD to the PR (partial response) characteristics used in the PRML signal processing technique, that is, the characteristics specified in the standard. It is a circuit which is performed, and is a circuit well known in the said field | area. Next, the equalized reproduction signal output from the equalizer 12 is binarized by the binarization circuit 50 using the zero level as the slice level. The latch 52 receives the resulting binarization signal SB and latches the binarization signal in response to the mask signal MST from the mask signal generator 30. That is, the latch 52 extracts the signal portion while the mask signal is not present by ignoring the binarization signal portion while the mask signal is present. The next jitter determination circuit 54 performs jitter determination from a latch output SL which is the extracted signal portion by a conventionally known method. As a method of jitter determination, the pulse width measurement method which measures the length of each mark / space in a binarization signal, and determines the change, and the data-to-measure which measures the phase difference between the edge of a mark / space and the edge of a synchronous clock. The clock method and the like are known.

Next, the details of the mask signal generator 30 will be described with reference to FIG. 7. The generator 30 includes an upper threshold crossing detection unit 300, a lower threshold crossing detection unit 302, and an upper mask. The generator 304, the lower mask generator 306, and the mask generator 308 are provided. In detail, the upper threshold crossing detection unit 300 uses the binarization circuit 3000 and the upper threshold setting circuit 3002 that receive the HD DVD playback signal (see FIG. 7 (b)) which is the output of the AGC 10. On the other hand, the lower threshold crossing detection unit 302 similarly includes a binarization circuit 3020 and a lower threshold setting circuit 3022 that receive the output from the AGC 10. 4 and 5, the binarization circuit 3000 performs binarization on the AGC output using the upper threshold THU received from the upper threshold setting circuit 3002, and as a result, As described with reference to FIG. 4, the signal is output as an upper threshold crossover signal CTHU (FIG. 7C). The crossing signal CTHU goes high when the upper threshold crosses positively on the zero level side and goes low when it crosses in the opposite direction. On the other hand, the binarization circuit 3020 performs binarization processing on the AGC output using the lower threshold value THL received from the lower threshold value setting circuit 3022, and returns the result as the lower threshold crossover signal CTHL [ Fig. 7 (d)]. The crossing signal CTHL becomes high when the lower threshold crosses negatively on the zero level side and becomes low when crossing in the opposite direction. In addition, in this embodiment, the upper threshold value and the lower threshold value are set so that the shortest 2T component may be excluded at least. However, it is as above-mentioned that it can set to exclude at least the periodic component longer than it, or to change a threshold value in operation.

Next, the upper mask generator 304 includes a delay circuit 3040, a flip-flop (F / F) 3042, and an OR gate 3044. Similarly, the lower mask generator 306 also includes: A delay circuit 3060, a flip-flop (F / F) 3062, and an OR gate 3064 are provided. In detail, the delay circuits 3040 and 3060 receive the upper or lower threshold crossing signals CTHU and CTHL, respectively, and delay them for a predetermined time, and delay the delay upper threshold crossing signals CTHUD [Fig. e)] or the delay lower threshold crossing signal CTHLD (Fig. 7 (f)). In this embodiment, since the at least one periodic component to be removed is the shortest 2T component, the delay amount in these delay circuits is 2T. This delay amount is used to identify clear crossings and non-clear crossings as described with reference to FIGS. 4 and 5. In addition, when removing even the component longer than 2T, what is necessary is just to set the delay of the same length as the period of the largest component removed.

The OR gate 3044 then receives the lower threshold crossing signal CTHL on one input, receives the lower mask signal MSL from the F / F 3042 on the other input, and outputs to the output. An upper mask prohibition signal INHU (Fig. 7 (g)) is generated. As can be seen from Fig. 4, the upper mask prohibition signal INHU is in the state where the lower threshold crossing signal CTHL is high (this means that the reproduction signal is in the negative side than the lower threshold THL). Or when the lower mask signal MSL is high (this indicates that the lower mask on the opposite side is occurring), the generation of the upper mask signal is prohibited. Therefore, the generation of the upper mask signal is permitted. The lower threshold crossing signal CTHL is in a low state and the lower mask signal MSL is not generated, and similarly, the OR gate 3064 receives the upper threshold crossing signal CTHU on one side. It receives the input, receives the upper mask signal MSU from the F / F 3062 to the other input, and generates the lower mask prohibition signal INHL (Fig. 7 (h)) at the output. As described in the signal INHU In other words, the lower mask prohibition signal INHL indicates that the upper threshold crossing signal CTHU is in a high state (this indicates that the reproduction signal is on both sides of the upper threshold THU), or the upper mask. When the signal MSU is high (this indicates that the upper mask on the opposite side is being generated), the generation of the lower mask signal is prohibited. Therefore, the generation of the lower mask signal is permitted by the upper threshold crossing signal ( CTHU is in a low state and no upper mask signal MSU is generated.

Next, the F / F 3042 receives the upper mask prohibition signal INHU at the data input terminal, the delay upper threshold cross signal CTHUD at the inverted clock terminal, and then the signal at the inverted clock terminal. Is generated at the Q * ("*" indicates inversion) terminal, which becomes the upper mask signal MSU (Fig. 7 (i)). . That is, the upper mask signal generates the upper mask signal MSU when the upper mask prohibition signal INHU is low when the delay upper threshold crossing signal CTHUD falls low. Similarly, the F / F 3062 receives the lower mask prohibition signal INHL at the data input terminal, the delay lower threshold cross signal CTHLD at the inverted clock terminal, and Q * ("*"). Generates a lower mask signal MSL (Fig. 7 (j)) at the terminal. The lower mask signal generates the lower mask signal MSL when the lower mask prohibition signal INHU is low when the delay lower threshold crossing signal CTHLD falls low.

The next mask generator 308 includes an OR gate 3080 and a timing adjustment circuit 3082. The OR gate 3080 receives two inputs of the upper mask signal MSU and the lower mask signal MSL, and generates a mask signal MS (Fig. 7 (k)) as their logical sum at the output. The mask signal is delayed by 2T for the reproduction signal to be masked (delay by the delay circuits 3040 and 3060), but the reproduction signal is also delayed by the equalization circuit. In order to match the timing of the mask signal MS, the timing adjustment circuit 3082 generates a mask signal MST after time adjustment by delaying when the mask signal MS is advanced than the binarization signal SB. This is supplied to the latch 52. In the case where the mask signal MS is delayed from the binarization signal SB, the mask signal MS may be changed so as to insert a delay circuit between the binarization circuit 50 and the latch circuit 52.

Next, with reference to FIG. 7, the operation | movement of the mask signal generator 30 part of FIG. 6 is demonstrated in detail. The HD DVD playback signal shown in the timing chart of FIG. 7 includes a clear cross including clear cross 1 and clear cross 2, a return non-clear clear 1, a non-return non clear cross, and a return non clear cross 2. These are demonstrated. First, in the case of the clear crossing 1 from the negative side to the both side, in this case, it is not necessary to generate a lower mask, but at this time, when the delay lower threshold crossing signal CTHLD falls at the time t11, the lower mask prohibition signal Since the upper threshold crossing signal CTHU is high when INHL is high (at the time when t11 falls, the upper mask signal MSU is low) and the mask generation is prohibited, the lower mask is kept low. In the case of clear intersection 2, whether or not the upper mask is generated or not is generated similarly, in the case of the return-type non-clear intersection 1, since it starts on the negative side at this time, a lower mask (MSL) is generated. At this time, when the delay lower threshold crossing signal CTHLD falls at the time t12, the lower mask prohibition signal INHL is low (the upper threshold crossing signal at the time of its fall at t12). Since the CTHU does not prohibit the mask generation at low, the mask signal is started by setting the lower mask MSL high.Next, when the delay lower threshold crossing signal CTHLD falls at time t13, Since the lower mask prohibition signal INHL is high (the upper threshold crossing signal CTHU is high at t13) and the mask generation is inhibited, the lower mask MSL is set to low to terminate the mask signal.

Next, in the case of the non-return type non-clear crossing, since this case starts from both sides, it is necessary to generate an upper mask. That is, when the delay upper threshold crossing signal CTHUD falls at t14, the upper mask prohibition signal INHU is low (the lower threshold crossing signal CTHL is low at its fall at t14) and the mask is masked. Since the generation is not prohibited, the upper mask MSU is started high. Thereafter, the next drop of the delay upper threshold crossing signal CTHUD occurs at time t16, but at this time, the upper mask prohibition signal INHU is high [the lower threshold crossing signal CTHL is high at t16] and the mask is Since the generation is prohibited, the upper mask MSU is turned low to terminate the upper mask. The last return non-clear crossing 2 has the same polarity as the return non-clear crossing 1 described earlier, but generates the upper mask in the same operation. At the time t15, the delay lower threshold crossing signal CTHLD falls. At this time, the lower mask prohibition signal INHL becomes high. This is because the upper threshold crossing signal CTHU is high at time t15.

Next, with reference to FIG. 8, the operation | movement in the case where a non-return type non-clear crossing occurs continuously is demonstrated. In this case, the same operation as the time point t14 of the non-return type non-clear crossing in FIG. 7 occurs at the time point t20, and the upper mask MSU becomes high. Also in the case of the example of FIG. 8, at a time point t21 corresponding to the time point t15 of FIG. 7, the delay lower threshold crossing signal CTHLD falls. At this time, the lower mask prohibition signal INHL becomes high. The reason is that at t21, the upper threshold crossing signal CTHU is low, but unlike the example of Fig. 7, the upper mask signal MSU is high. For this reason, generation | occurrence | production of the lower mask is prohibited, and the lower mask MSL is as it is. Subsequent operations are the same as those in FIG. As described above, while one of the upper mask and the lower mask is generated, the other mask is unnecessary, and thus the occurrence of the mask is prevented.

The mask signal generated as described above generates the mask signal MST in timing with the binarization signal SB by the timing adjustment circuit 3082. The latch 52 receiving the mask signal MST latches the state of the binarization signal SB when the mask signal rises high and outputs the latched state as long as the mask signal stays high. Then, when it descends low, the latch operation is stopped and the signal received at the input is generated as is in the output. This is the latch output SL. As a result, it is possible to disregard the reproduction signal while the mask is present and extract a signal portion which is a part of the reproduction signal.

Next, with reference to the flowchart of FIG. 9, the method of realizing the mask signal generator 30 of FIG. 6 by software is demonstrated. In addition, in this flowchart, the variable corresponding to the signal shown in the circuit of FIG. 6 uses the code | symbol same as the name of these signals for convenience of description. First, in step 900, one sample of the HD DVD playback signal is acquired and referred to as A. FIG. This flow is executed each time one sample of the HD DVD playback signal is acquired.

Next, in steps 902 to 908, the upper threshold crossing variable CTHU is generated from the upper threshold variable THU, but this corresponds to the function of the upper threshold crossing detection unit 300 in FIG. That is, in step 902, a value preset as the upper threshold value is set in the variable THU. In step 904, it is determined whether the reproduction signal sample A is equal to or greater than this upper threshold variable THU, and when YES, in step 906, the upper threshold cross variable CTHU is set high, that is, "1". . If NO, it is set low in step 908, that is, "0".

Next, the lower threshold crossing variable CTHL is generated from the lower threshold variable THL in steps 910 to 916, but this corresponds to the function of the lower threshold crossing detection unit 302 of FIG. 6. Specifically, in step 910, a value set as the lower threshold is set in the variable THL, and in step 912, it is determined whether or not sample A is equal to or less than THL, and if YES, in step 914, the lower threshold is set. The cross variable CTHL is set to "1", while when NO, the variable CTHL is set to "0" in step 916.

Next, in steps 918 to 926, the delay upper threshold crossing variable CTHUD is set from the upper threshold crossing variable CTHU, but this corresponds to the function of the delay circuit 3040 in FIG. That is, it is determined whether the upper threshold THU is less than the amplitude of the 3T periodic component, and in the case of YES, the upper threshold cross variable is delayed by 2T in step 920 (for example, in synchronization with the reproduction signal). The clock is used to delay a period of 2T.). When NO, it is determined in step 922 whether the THU is less than the amplitude of the periodic component of (n-1) T. However, n is an integer larger than five. At this step 922, at YES, at step 924, the upper threshold crossing variable is delayed by the size of (n-1) T; at NO, at step 926, the variable is delayed by the size of nT, resulting in Denotes the delay upper threshold crossing variable (CTHUD). Next, in steps 928 to 936, the delay upper threshold cross variable CTHLD is set from the lower threshold cross variable CTHL in the same manner as the steps 918 to 926 (the function of the delay circuit 3060 in FIG. Corresponding], since the process can be performed in the same manner as in steps 918 to 926, the description is omitted. In the case of the HD DVD playback signal, the signal component has a period of 2T to 11T and 13T, and the minimum amplitude is increased in amplitude from 2T to 3T and 4T, and reaches the maximum amplitude in 5T, and 13T after 6T. The maximum amplitude does not change as it is. However, since 5T, 6T, and 7T are signal components having the same maximum amplitude, but can be distinguished by changing the delay amount, they can be detected by distinguishing from 2T to 5T, 2T to 6T, and 2T to 7T. . This also applies to the delay amounts set by the delay circuits 3040 and 3060 in FIG. In addition, in the flow of FIG. 9, the similar steps are provided in the upper side and the lower side, because the case where the upper threshold value and the lower threshold value have the same absolute value as well as the case where the absolute value is different are considered. to be. For example, this is the case where jitter of a reproduction signal is detected in which the symmetry is off, that is, the intermediate value between the positive peak and the negative peak does not become a zero level.

Next, in step 938 to 942, the upper mask is set, but this corresponds to the functions of the OR gate 3044 and the F / F 3042 in FIG. That is, in step 938, when the delay upper threshold crossing variable CTHUD transitions from high to low, the lower threshold crossing variable CTHL is "0", and the lower mask variable MSL is "0". If it is YES, and if YES, the upper mask variable (MSU) is made high in step 940, if the upper mask has not yet occurred at this point, the upper mask is started, and the upper mask is already started. The upper mask is held when it is made. On the other hand, when NO in step 938, the upper mask variable MSU is set low in step 942, and when the upper mask has already occurred, the upper mask is terminated.

Similarly, the lower mask is set in steps 944 to 948, but this corresponds to the functions of the OR gate 3064 and the F / F 3062 in FIG. The processing is basically the same as in the case of steps 938 to 942, except that the delay lower threshold crossing variable is not at the transition from the high to the low of the delay upper threshold crossing variable CTHUD in step 944. At the transition from high to low of (CTHLD), the upper threshold cross variable CTHU is "0" and the upper mask variable MSU determines whether the condition of "0" is satisfied. . In this way, the start or end of the lower mask MSL is realized. Finally, in step 950, the mask variable MS is generated by taking the logical sum of the upper mask variable MSU and the lower mask variable MSL. This process corresponds to the OR gate 3080 of FIG.

By repeating the operation described above for each sample of the HD DVD playback signal, the operation described in Figs. 6, 7 and 8 can be realized.

Next, another embodiment of the jitter detection circuit shown in FIG. 2 will be described with reference to FIG. 10. In FIG. 6, the latch circuit 52 is disposed after the binarization circuit 50, but in the embodiment of FIG. 10, the hold circuit 56 is placed in front of the binarization circuit 50a and the jitter determination circuit 54a. Is configured to receive the output from the binarization circuit 50a. At this time, instead of the latch circuit 52 of FIG. 6, in FIG. 10, the hold circuit 56 is configured to receive the output of the equalizer 12 of FIG. 6 and the mask signal MST from the mask signal generator 30. . At this time, the hold circuit 56 holds the equalizer output when the mask signal MST becomes high and generates the output. When the mask signal MST becomes low, the hold circuit 56 outputs the equalizer output to the output as it is. Occurs. Even with this configuration, a part of the HD DVD playback signal can be extracted. The binarization circuit 50a and the jitter determination circuit 54a may have the same configuration as that in FIG.

Next, another embodiment of the jitter detection circuit shown in FIG. 2 will be described with reference to FIG. 11. This embodiment differs from the jitter detection circuit in the embodiment of FIG. 6 in that it receives the mask signal, not the latch, but the jitter determination circuit 54b. By receiving this mask signal, the jitter determination circuit 54b does not extract a part of the HD DVD playback signal, but controls the jitter determination operation and actually performs jitter detection based on a part of the playback signal. This embodiment of Fig. 11 can be similarly applied to the jitter detection circuit shown in Fig. 10, so that the jitter determination circuit 54a, not the hold circuit 56, can receive a mask signal.

Next, with reference to FIG. 12, the jitter measuring apparatus provided with the jitter detection apparatus of one Embodiment mentioned above is demonstrated. The jitter measuring device includes a display / output section that receives a jitter determination output from the jitter detecting device. The output from the jitter detection device can take a form in accordance with the display form or output form in the display / output section. For example, the jitter determination output may be in the form of performing statistical processing on the width of each mark / space length, or in the form of performing statistical processing on the difference between the edge of the mark / space and the edge of the clock as described above. . The display / output unit outputs the received jitter determination output to an output device such as a display or a printer according to a user's selection. According to this embodiment, the jitter-related adjustment work required at the production site of the optical disc related products such as HD DVD can be further speeded up.

Finally, referring to FIG. 13, an electronic device including the jitter detection device of the above-described embodiment will be described. As the electronic device, optical disc related devices such as an optical pickup, an optical disc driver, an optical disc player, and the like are included. If the device uses the PRML signal processing technology, other devices such as a communication device are also included. By providing the jitter detection device of the above-described embodiment in such an electronic device, jitter processing for removing the influence of jitter in the electronic device can be realized at a higher speed or with a simpler circuit configuration.

As mentioned above, some embodiment was described in detail. However, the jitter detection device of the above embodiment can be similarly applied not only to recording media such as HD DVD, but also to jitter detection of signals from other information recording media using the same signal format as HD DVD, for example, magnetic disks. . As described above, the jitter detection device of the above embodiment can be applied to signals from other fields in which the PRML method is used, for example, communication media such as communication lines and networks.

While various exemplary aspects and embodiments have been described in detail above, various changes, substitutions, additions, and subcombinations are recognized by those skilled in the art. Accordingly, the interpretation of the claims set forth in the appended claims and the claims that may be included in future claims are intended to cover all such modifications, substitutions, additions, subcombinations, etc., as fall within the true spirit and scope. Intended to be done.

Claims (19)

Receiving a signal, A determination step of determining a signal portion used for jitter detection in the received signal based on the signal amplitude; And a jitter detecting step of detecting jitter in the signal based on the determined signal portion. The method of claim 1, The determining step, Determining first and second thresholds, Generating a period signal using the first and second threshold values, The jitter detection step, And responding to the received signal according to the period signal to detect the signal portion. The method of claim 2, Generating the period signal, Binarizing the received signal to the first threshold to generate a first binarized signal; Binarizing the received signal to the second threshold to generate a second binarized signal; A processing step of generating a mask signal from the first binarization signal and the second binarization signal, wherein the mask signal indicates a period in which a second signal portion other than the first signal portion that is the signal portion of the received signal exists. Including the above processing step, Detecting the signal portion, And extracting the first signal portion from the received signal using the mask signal. The method of claim 3, wherein The received signal includes a signal component having a positive and negative maximum amplitude value and an amplitude less than or equal to a first amplitude value less than the maximum amplitude value, The first threshold has a value between the positive maximum amplitude value and the positive first amplitude value, and the second threshold is the negative maximum amplitude value and the negative first amplitude value. Jitter detection method characterized in that it has a value between and. The method of claim 4, wherein The processing step, One of the first and second binarized signals is related to whether or not a first state occurs in which the received signal crosses one of the first and second thresholds in a first polarity direction. Determining based on the binarization signal of When the first state occurs, within a predetermined time at the first time point when the first state occurs, whether or not a second state occurs in which the received signal crosses the other threshold value in the first polarity direction. Determining whether or not based on the other binarization signal; Initiating the mask signal when the second state does not occur within the preset time; Determining whether a third state occurs that another first state occurs and that another second state occurs within the predetermined time at a third point in time when the first state occurs; And terminating the mask signal at the third time point when the third state occurs. The method of claim 5, The processing step, And once the mask signal is initiated, preventing the generation of another mask signal until the mask signal is terminated. Jitter measurement method characterized by measuring the jitter using the jitter detection method according to any one of claims 1 to 6. A receiving circuit for receiving a signal, A determination circuit for determining a signal portion used for jitter detection in the received signal based on the signal amplitude; And a jitter detection circuit for detecting jitter related to the signal based on the determined signal portion. The method of claim 8, The determination circuit, Generating a period signal using a first threshold setting circuit for generating a first threshold, a second threshold setting circuit for generating a second threshold, and the first and second thresholds; A period signal generating circuit, The jitter detection circuit, And a signal portion detecting circuit for detecting the signal portion by responding to the received signal according to the period signal. The method of claim 9, The period signal generation circuit, A first binarization circuit for binarizing the received signal to the first threshold to generate a first binarization signal; A second binarization circuit for binarizing the received signal to the second threshold to generate a second binarization signal; A processing circuit for generating a mask signal from the first binarization signal and the second binarization signal, wherein the mask signal indicates a period in which a second signal portion other than the first signal portion that is the signal portion in the received signal exists. Including the above processing circuit, The signal portion detection circuit, And an extraction circuit for extracting the first signal portion from the received signal using the mask signal. The method of claim 10, The received signal includes a signal component having a positive and negative maximum amplitude value and an amplitude less than or equal to a first amplitude value less than the maximum amplitude value, The first threshold has a value between the positive maximum amplitude value and the positive first amplitude value, and the second threshold is the negative maximum amplitude value and the negative first amplitude value. And a jitter detection device having a value between and. The method of claim 11, The processing circuit, A first delay circuit for generating a first delay binarization signal that delays the first binarization signal by a predetermined time period; A second delay circuit for generating a second delay binarization signal delaying the second binarization signal by the predetermined time; As a first logic circuit connected to receive said first and second binarization signals and said first and second delay binarization signals, and generating first and second mask signals, a. The binarization of one of the first and second binarization signals related to whether or not a first state occurs in which the received signal crosses one of the first and second thresholds in a first polarity direction. Judging based on the signal, b. When the first state occurs, whether or not a second state occurs in which the received signal crosses the other threshold value in the first polarity direction within the predetermined time at the first time point when the first state occurs. Is determined according to one of the delay binarization signals associated with the other binarization signal and the first and second delay binarization signals, c. When the second state does not occur within the preset time, one of the mask signals associated with the first and second mask signals is started. d. It is determined whether a third state occurs that another first state occurs, and another second state occurs within the predetermined time at a third point in time when the first state occurs, e. The first logic circuit operable to terminate the one mask signal at the third time point when the third state occurs; And a second logic circuit for generating the mask signal from the first and second mask signals. The method of claim 12, The first logic circuit, A first mask signal generation logic circuit receiving the first delay binarization signal, the second binarization signal, the second mask signal, and generating the first mask signal; A second mask signal generation logic circuit receiving the second delay binarization signal, the first binarization signal, the first mask signal, and generating the second mask signal; And the first logic circuit stops generation of the other mask signal until the one mask signal is terminated after the one mask signal is started. The method of claim 10, The jitter detection circuit is also a third binarization circuit for generating a third binarization signal by binarizing the received signal with a third threshold value, wherein the extraction circuit is configured to generate the first signal portion from the third binarization signal. The third binarization circuit for extracting The extraction circuit uses the first signal portion extracted from the third binarization signal, And a jitter determination circuit for determining jitter of the received signal. The method of claim 14, The extraction circuit, And a circuit for generating said first signal portion by varying the magnitude of said third binarization signal during said mask signal period. The method of claim 10, And said second signal portion comprises at least the shortest period component in said received signal. The method of claim 8, And the signal is a signal from an information recording medium. An electronic device comprising the jitter detection device according to any one of claims 8 to 17. Means for receiving a signal, Means for determining, based on the signal amplitude, a signal portion used for jitter detection in the received signal; And a means for detecting jitter related to the signal based on the determined signal portion.

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