JP4106703B2 - Disc signal analyzer - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a disk signal analyzing apparatus, and more particularly, recorded with at least two or more values including a high density optical disk signal equipped with a PRML (Partial Response Maximum Likelihood) signal processing function such as a DVD or a next generation recording medium. The present invention relates to a disk signal analyzing apparatus used for analyzing and evaluating a disk signal.
[0002]
[Prior art]
PRML signal processing is one of the reproduction signal processing methods for increasing the density, and is based on the PR method in which the waveform is adjusted by a method that intentionally provides inter-code interference, and the data sequence recorded with correlation between the data. This is a data channel technology that employs the ML method for detecting the most probable data string.
[0003]
In a magnetic disk or optical disk, it is difficult to determine whether data or noise is detected only by a signal detected by an MR head or an optical pickup. Therefore, PRML signal processing is used to accurately make this determination. That is, the recorded code is always affected by the previously written code. Therefore, in the PRML signal processing, this intersymbol interference is used to obtain the most accurate code when there is a correlation between a waveform equalization method (PR method) that corrects reproduction distortion when reproducing data and the reproduced data. A detection method (ML method) is used in combination. Not only magnetic disk devices but also optical disk devices and video recording VTRs are attracting attention.
[0004]
FIG. 19 is a block diagram showing an example of a conventional disk signal analyzing apparatus. The disc signal analyzing apparatus 100 performs various analyzes on the RF signal and CLOCK signal input from the optical disc, and outputs a decode signal, a display signal, an error signal, and a pattern signal.
[0005]
The input circuit 101 includes an amplifier, an attenuator, and the like, and receives an RF signal and a CLOCK signal of an optical disk (not shown).
The A / D conversion circuit 102 converts the RF signal output from the input circuit 101 into a digital signal at the timing of the CLOCK signal.
[0006]
The PR equalization circuit 103 separates and shapes the digital signal waveform output from the A / D conversion circuit 102 in the voltage amplitude direction, and includes an N-order digital transversal filter as shown in FIG. Here, PR represents an acronym for Partial Response. In FIG. 20, a _k Is the signal of the input series, g ₀ ~ G _n-1 Is the tap coefficient of the filter, c _k Is an output sequence signal, D is a delay element, X is a weight coefficient multiplier, and Σ is an adder.
[0007]
The operation of the Nth-order digital transversal filter shown in FIG. 20 will be described using FIG. 21 and FIG. In order to simplify the description, it is assumed that PR (1, 1) called PR class 1 is used.
[0008]
FIG. 21 is a block diagram of an encoder of PR (1,1), where D is a delay element and + is an adder.
[0009]
FIG. 22 is a state transition diagram of PR (1,1). S0 indicates the case where the state of the delay element D in FIG. 21 is 0, and S1 indicates the case where it is 1. The arrow indicates the transition direction, and a / b beside the arrow means input / output. However, the output level is normalized to a range of −1 to 1.
[0010]
In FIG. 19 again, the Viterbi decoding circuit 104 performs Viterbi decoding from the equalized digital waveform signal output from the PR equalization circuit 103 using a known Viterbi algorithm.
[0011]
The clock generation circuit 105 outputs a clock to the pattern output circuit 106 that outputs a digital pattern.
[0012]
The pattern output circuit 106 outputs a predefined digital pattern at the timing of the input CLOCK signal.
[0013]
The comparison circuit 107 latches the output data of the Viterbi decoding circuit 104 and the output data of the pattern output circuit 106 at the timing of the CLOCK signal, compares the bits, and outputs the result as an error bit.
[0014]
The demodulation circuit 108 performs demodulation and error correction on the output data of the Viterbi decoding circuit 104 in accordance with the modulation method unique to the disk, and outputs the decoded data.
[0015]
The error rate counter 109 calculates an error rate based on the CLOCK signal and the error output of the comparison circuit 106.
[0016]
The operation of FIG. 19 configured as described above will be described with reference to the timing chart of FIG.
[0017]
S1 is an RF signal from the optical disk head input to the input circuit 101, and S2 is a CLOCK signal from the optical disk head input to the input circuit 101. The RF signal S1 and the CLOCK signal S2 are subjected to a desired level process in the voltage axis direction by the input circuit 101, and output to each unit as the RF signal S3 and the CLOCK signal S4.
[0018]
S5 is a digital signal obtained by converting the RF signal S3 output from the input circuit 101 by the A / D conversion circuit 102, and S6 is a digital signal obtained by equalizing the waveform of the digital signal S5 of the A / D conversion circuit 102 by the PR equalization circuit 103. Output signal. The three lines parallel to the X axis correspond to the normalized levels of −1, 0, 1 respectively, and the numerical value next to the sampling point is a level value normalized to the level of −1 to 1. is there.
[0019]
S7 is an output signal obtained by decoding the output signal S6 of the PR equalization circuit 103 by the Viterbi decoding circuit 104, S8 is a pattern output signal output from the pattern output circuit 106 at the timing of the CLOCK signal S7, and S9 is a decoded signal by the comparison circuit 107. As a result of comparing S7 and the pattern output signal S8, this is an error output signal in which a different bit part is output as a high level.
[0020]
FIG. 24 is a trellis diagram of Viterbi decoding. In FIG. 24, the arrow indicates state transition, and the numerical value next to the arrow is the square value of the distance between the input value and the ideal value (hereinafter referred to as branch metric). The circles indicate the bit positions of the data, and the two-stage numerical values above and below the bit positions are the integrated values of the branch metrics of each path. In S0, the upper stage is S0 → S0, the lower stage is S1 → S0, and in S1, the upper stage is S0 → S1, and the lower stage is S1 → S1. A numerical value with a strikethrough indicates a path erased in the Viterbi decoding process, and in the Viterbi algorithm, a surviving path (thick arrow) is adopted as a decoding path. Since the Viterbi algorithm is general, a detailed description is omitted.
[0021]
FIG. 25 is a flowchart showing an operation flow of the apparatus of FIG. Since all the components of the apparatus of FIG. 19 are realized by hardware, processing is executed in real time in synchronization with the CLOCK signal S4. In this flowchart, time series steps (A) to (J) are shown so that the flow from the input circuit 101 located upstream of the circuit configuration to the error rate counter 109 located downstream can be understood. Hereinafter, steps (A) to (J) will be described.
[0022]
(A) An RF signal S1 and a CLOCK signal S2 are input to the input circuit 101 from an optical disk head (not shown).
[0023]
(B) The RF circuit S1 and the CLOCK signal S2 are subjected to signal processing in a desired level direction by an input circuit 101 including an amplifier, an attenuator, a filter, and the like.
[0024]
(C) The RF signal S3 signal-processed in the desired level direction by the input circuit 101 is A / D converted at the timing of the CLOCK signal S4. The signal S5 after A / D conversion becomes a discrete signal as shown in FIG.
[0025]
(D) The digital signal S5 converted and output from the A / D conversion circuit 102 is output as a signal S6 equalized by the PR equalization circuit 103. For example, when a PR (1, 1) equalizer is used, an equalization process is performed to separate the three levels of −1, 0, and 1. In order to realize this equalization processing, the PR equalization circuit 103 is composed of an Nth-order digital transversal filter as shown in FIG. 9 as described above. Since this digital transversal filter is realized by hardware, the number of taps and tap coefficients are usually predetermined values according to the PRML system.
[0026]
(E) The output signal S6 from the PR equalization circuit 103 is input to the Viterbi decoding circuit 104, where decoding processing is performed, and a Viterbi decoding signal S7 is output. At the time of decoding, using the state transition diagram of FIG. 22, metric calculation and path selection processing as shown in the trellis diagram of FIG. 24 are repeatedly performed. In this example, it is decoded into signals of 1,1,1,0,0,0,0,0,0,0,0,1,1,1,1,0 ... In the Viterbi decoding circuit 104 as well, in order to perform high-speed processing by hardware, it is normal that a fixed PR class and a fixed path memory (maximum search path length) are used.
[0027]
(F) The pattern output circuit 106 outputs a digital pattern signal S8 defined in advance at the timing of the CLOCK signal S4 signal-processed by the input circuit 101. Since a specific pattern for measuring the error rate is defined, it is necessary to synchronize the normal input signal with the SYNC signal for bit comparison. In this example, 1,1,1,0,0,0,0,0,0,0,1,1,1,1,0,0 ... are generated. The clock generation circuit 105 is used as a clock source for outputting a write signal to the disk, and is not used in FIG.
[0028]
(G) The Viterbi decoded signal S7 and the pattern output waveform S8 are input to the comparison circuit 107, and the signal is latched and compared at the timing of the CLOCK signal S4 processed by the input circuit 101.
[0029]
(H) The comparison circuit 107 is composed of an XOR circuit or the like, and outputs an error output signal S9 by setting different bits of the two signals to a high level. In this example, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0.
[0030]
(I to J) The error rate counter 109 counts the CLOCK signal S4 and the error output S9 output from the comparison circuit 107, and calculates the error rate (= number of error bits / total number of bits counted). When the number of count bits set by the user or a fixed number of bits is reached, an error rate (for example, 2, 0e-5) is sent to display means such as a liquid crystal panel or LED. Normally, the number of bits from 10 to the 7th power is counted.
The above sequences A to J are repeatedly executed in real time at the timing of the CLOCK signal S4.
[0031]
[Problems to be solved by the invention]
However, such a conventional disk signal analyzing apparatus has the following problems.
[0032]
In order to measure the error rate, the number of bits in the order of 10 6 to the 7th power is usually required. Therefore, it takes time to analyze the error, and productivity is lowered particularly in the inspection process.
[0033]
In addition, since a pattern output circuit for comparing bits is always necessary for error rate measurement, the circuit scale increases and the cost also increases.
[0034]
Further, in order to inspect with a specific pattern, the user must define the pattern each time, and the number of work steps increases.
[0035]
In addition, since most devices are configured by hardware, there are many cases in which there is no degree of freedom for filter settings and corresponding PR classes, and it can be applied only to a fixed system.
[0036]
Also, if a function for analyzing the distribution variation of the PR equalized data (FIG. 10 S6) in the direction of the voltage axis is introduced, the error is large and the skirts of the adjacent histograms for each level overlap. In this case, it is impossible to extract data corresponding to the level, and it becomes difficult to perform jitter analysis on a histogram having a shape close to a normal distribution, and there is a problem that the shape of only the histogram of interest cannot be confirmed. Jitter here does not mean fluctuations in the time direction, but represents the degree of variation in histogram distribution, and has a broad meaning including all of the variance of statistics, PP (Peak-Peak), standard deviation, and the like. . Jitter in the following description is also synonymous.
[0037]
The present invention solves these problems, and its purpose is to evaluate a disk signal recorded with at least two or more values, and it can be used for various PRML systems because of its fast analysis time and small circuit scale. Therefore, it is an object of the present invention to provide a disk signal analyzing apparatus capable of performing histogram analysis appropriately even when the degree of freedom is high and the error is large.
[0038]
[Means for Solving the Problems]
The invention of claim 1 which achieves such an object is a disk signal analyzing apparatus used for analyzing and evaluating a disk signal recorded with at least two values, and at least PR equalization for separating a signal waveform in an amplitude direction. Means, this Viterbi decoding means for performing Viterbi decoding of output data of the PR equalization means and calculating a path metric; this SAM value calculating means for calculating a SAM (difference metric) from the decoding path and path metric calculated by the Viterbi decoding means; Said A SAM window memory for specifying a plurality of SAM ranges is provided.
The SAM value calculation means creates a histogram for each window from the decoding path, path metric, and SAM window memory output, which are outputs of the Viterbi decoding means, and calculates statistical values.
[0039]
The invention of claim 2 is the disk signal analyzing apparatus of claim 1, Said A digital transversal filter is used as the PR equalization means.
[0040]
According to a third aspect of the present invention, in the disc signal analyzing apparatus according to the first or second aspect, Said A memory for storing tap coefficients of the digital transversal filter is provided.
[0041]
According to a fourth aspect of the present invention, in the disk signal analyzing apparatus according to any one of the first to third aspects, Said A PR class memory for storing a PR class for determining an algorithm for Viterbi decoding is provided.
[0043]
A fifth aspect of the present invention provides the disc signal analyzing apparatus according to any one of the first to fourth aspects, Said A path memory length memory for storing a maximum path length during Viterbi decoding is provided.
[0044]
The invention of claim 6 is the disk signal analyzing apparatus according to any one of claims 1 to 5, Said An equalization waveform memory for storing equalization waveform data output from the PR equalization means is provided.
[0045]
The invention of claim 7 is the disc signal analyzing apparatus according to claim 6, Said A normalized level memory for storing a maximum value and a minimum value for defining a range for projecting the equalized waveform data stored in the equalized waveform memory to a normalized level is provided.
[0046]
The invention of claim 8 is the disc signal analyzing apparatus according to claim 1, Said An RF signal and a clock signal are input as disk signals, and means for adjusting the phase of the clock signal is provided.
[0047]
As a result, disk signal analysis can be performed with a much smaller number of sampling points than that required in the conventional error rate measurement method.
Since the evaluation inspection time can be drastically shortened and the filter processing and the arithmetic processing can be realized by software, it can be applied to various PRML systems.
[0048]
The invention of claim 9 is the disc signal analyzing apparatus according to claim 1, Said An RF signal is input as a disk signal, and a means for reproducing a clock signal from the RF signal is provided.
[0049]
Thereby, an input signal system can be simplified.
[0050]
According to a tenth aspect of the present invention, in the disc signal analyzing apparatus according to the first aspect, the level window memory for designating a plurality of level ranges, the range of the level window memory, and the output of the PR equalizing means, Said Level jitter calculation means for creating a histogram for each window and calculating a statistical value.
[0051]
The invention of claim 11 is the disc signal analyzing apparatus according to claim 10, Said The level jitter calculating means updates the tap coefficient memory to an optimum value using an adaptive equalization filter algorithm based on the calculated statistic.
[0053]
As a result, signal quality in the level direction can be evaluated, and margin analysis for disc signal errors can be visually performed.
[0054]
The invention of claim 12 is the disc signal analyzing apparatus according to claim 1 or 11, Said When extracting data of the level window and the SAM window, the decoding state transition and the decoding path pattern table are referred to.
[0055]
As a result, even if the error is so large that the adjacent histogram skirts overlap, the data corresponding to the window can be reliably extracted, and the jitter analysis can be performed with the histogram having a shape closer to the normal distribution.
[0056]
According to a thirteenth aspect of the present invention, in the disc signal analyzing apparatus according to the twelfth aspect, the analysis Want to Level window and analysis Want to Selectable SAM window these Only the histogram of the window to be analyzed is extracted.
[0057]
As a result, only the histogram of the window to be analyzed can be extracted, and the shape analysis of the histogram for each equalized waveform level and the histogram for each SAM value becomes possible.
[0058]
The invention of claim 14 is the invention of claim 1. Or claim 13 In the disc signal analyzing apparatus described in Said A memory is provided for storing the level window and SAM window information for each PR class.
[0059]
This eliminates the need for window definition for the user and improves operability.
[0060]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1, reference numeral 800 denotes a disk signal analyzing apparatus according to the present invention.
[0061]
The delay time memory 801 holds the phase adjustment amount of the input CLOCK signal, and the value is set by the user.
[0062]
The input circuit 802 is configured by an amplifier, an attenuator, a programmable delay line that delays the CLOCK signal by a set delay time, and the like, and an RF signal and a CLOCK signal of an optical disk (not shown) are input thereto.
[0063]
The A / D conversion circuit 803 converts the RF signal output from the input circuit 802 into a digital signal at the timing of the CLOCK signal.
[0064]
The waveform memory 804 holds digital waveform data converted and output from the A / D conversion circuit 803.
[0065]
The tap coefficient memory 805 holds the digital transversal filter tap coefficient set by the user.
[0066]
The PR equalizing means 806 extracts the digital signal waveform output from the A / D conversion circuit 803 from the waveform memory 804 and separates and shapes it in the voltage amplitude direction. The PR equalizing means 806 performs filter processing using the coefficients of the tap coefficient memory 805. . The PR equalization means 806 is realized by software, for example.
[0067]
The equalized waveform memory 807 holds the equalized waveform data filtered by the PR equalizing unit 806.
[0068]
The level window memory 808 stores a level range according to the equalization level and is set by the user. If PR1 (three values) is used, three types of windows are defined.
[0069]
The level jitter calculating unit 809 extracts the equalized waveform data filtered by the PR equalizing unit 806 from the equalized waveform memory 807 and calculates a statistical value for each window from the window range in the level window memory 808. Yes, for example, by software.
[0070]
The PR class memory 810 defines an algorithm for Viterbi decoding, and PR1 is stored in this embodiment.
[0071]
The path memory length memory 811 stores maximum path length data at the time of Viterbi decoding, and 30 is stored in this embodiment.
[0072]
The normalization level memory 812 is for projecting the equalized waveform data in the equalized waveform memory 807 into a normalization space of −1 to 1. In this embodiment, the maximum value = 2V (normalized to = 1) and the minimum value = −2V (normalized to −1) are stored.
[0073]
The Viterbi decoding unit 813 performs Viterbi decoding of the data in the equalized waveform memory 807 that has been waveform-equalized by the PR equalizing unit 806. Specifically, Viterbi decoding processing is performed based on the PR class stored in the PR class memory 810, the path memory length stored in the path memory length memory 811, and the normalization level stored in the normalization level memory 812. The Viterbi decoding means 813 is also realized by software, for example.
[0074]
The path metric memory 814 stores the path metric result calculated by the Viterbi decoding unit 813.
[0075]
SAM window memory In 815, a range set by the user in accordance with the SAM value level is stored.
[0076]
The SAM value calculation means 816 extracts the path metric calculated by the Viterbi decoding means 813 from the path metric memory 814, and calculates the statistical value for each window from the window range in the SAM window memory 815. This SAM value calculation means 816 is also realized by software, for example.
[0077]
FIG. 2 is a timing chart for explaining the operation of FIG.
S10 is an RF signal from the optical disk head input to the input circuit 802, and S11 is a CLOCK signal from the optical disk head input to the input circuit 802. The RF signal S10 and the CLOCK signal S11 are subjected to level processing in a desired voltage axis direction by the input circuit 802, and are output to the A / D conversion circuit 803 as the RF signal S12 and the CLOCK signal S13.
[0078]
S14 is a digital signal obtained by converting the RF signal S12 output from the input circuit 802 by the A / D conversion circuit 803.
[0079]
FIG. 3 is a flowchart showing an operation flow of the apparatus of FIG. In the apparatus of FIG. 1, since the input circuit 802 and the A / D conversion circuit 803 are implemented by hardware, steps (d) to (f) are executed in real time in synchronization with the CLOCK signals S11 and S13. The Hereinafter, steps (a) to (k) will be described.
[0080]
(A) Prior to signal input, the delay time (for example, 17 ns) of the CLOCK signal 13 with respect to the input RF signal S12 is set in the delay time memory 801 in the internal memory state diagram shown in FIG. The tap coefficients (for example, α, β, γ...) Of the digital transversal filter to be set are set in the tap coefficient memory 805.
[0081]
Here, the memory state diagram of FIG. 4 will be described.
The delay time memory 801 stores a delay time for holding the phase adjustment amount of the CLOCK signal set by the user.
[0082]
The waveform memory 804 stores digital waveform data converted and output from the A / D conversion circuit 803.
[0083]
The tap coefficient of the digital transversal filter set by the user is stored in the tap coefficient memory 805. However, since the number of taps and the coefficient values themselves are not important, α, β, γ... Are used without using specific values.
[0084]
The equalized waveform memory 807 stores the equalized waveform data filtered by the PR equalizing means 806. Here, it is assumed that the same equalization result data as in the conventional example of FIG. 12 is obtained.
[0085]
Level window data set by the user is stored in the level window memory 808.
[0086]
The PR class memory 810 stores a PR class that defines an algorithm for Viterbi decoding.
[0087]
The path memory length memory 811 stores the maximum path length during Viterbi decoding.
[0088]
The normalization level memory 812 stores normalization level data for projecting the equalized waveform data in the equalized waveform memory 807 to the normalization space of −1 to 1.
[0089]
The path metric memory 814 stores the path metric result calculated by the Viterbi decoding unit 813.
[0090]
The SAM window memory 815 stores SAM window data set by the user.
[0091]
Returning to FIG.
(B) The PR class (for example, (1, 1)) used in the Viterbi decoding means 813 is set in the PR class memory 810, the path memory length (for example, 30) is set in the path memory length memory 811, and the normalization level memory A normalization level (for example, 2.0 V = 1.0, 0.0 V = 0.0, −2.0 V = −1.0) is set in 812.
[0092]
(C) A level window for level jitter calculation is set in the level window memory 808. Since PR (1,1) is a ternary level, three windows are defined. Normally, each center value (center) is a value obtained by equally dividing a voltage value normalized to −1 to 1 space. If the input RF signal has asymmetry, it may be set instead of equally divided.
[0093]
(D) The RF signal S10 and the CLOCK signal S11 are input to the input circuit 802 from the optical disk head.
[0094]
(E) The RF signal S10 and the CLOCK signal S11 are subjected to signal processing in a desired level direction by an input circuit 802 including an amplifier, an attenuator, a filter, and the like. The CLOCK signal S11 is delayed by a time of 17 ns stored in the delay time memory 801 by a built-in delay circuit.
[0095]
(F) The RF signal S12 processed by the input circuit 802 is A / D converted at the timing of the phase-adjusted (delayed) CLOCK signal S13, and the converted digital waveform data is stored in the waveform memory 804. The The converted signal is a discrete signal as shown in S14 of FIG.
[0096]
(G) The PR equalizing means 806 reads the waveform data from the waveform memory 804, performs digital filter processing from the coefficients stored in the tap coefficient memory 805, and stores the equalized waveform data in the equalized waveform memory 807.
[0097]
(H) The level jitter calculation means 809 reads the equalized waveform data from the equalized waveform memory 807, extracts the data in the area defined by the level window memory 808, and calculates the level jitter as a data string in the voltage axis direction. At the same time, an amplitude histogram and an amplitude jitter value as shown in FIG. 5 are displayed and output.
[0098]
Here, FIG. 5 will be described.
The amplitude histogram of FIG. 5 is a histogram obtained by viewing the equalized waveform data in the equalized waveform memory 807 of FIG. 4 from the voltage axis direction. Here, since PR (1, 1) is used, a window centered on three values (2.0 V, 0.0 V, −2.0 V) is defined. The dotted line on the histogram is a cursor indicating the window range.
In the upper right corner of the equalized waveform, the amplitude jitter value in the window is shown. The histogram and amplitude jitter results are displayed and output on a CRT or liquid crystal display mounted on the disk signal analyzer.
[0099]
Returning to FIG.
(I) The Viterbi decoding means 813 reads the equalized waveform data stored in the equalized waveform memory 807, and PR (1,1) defined in the PR class memory 810 and the path memory defined in the path memory length memory 811 Viterbi decoding is executed based on the normalization level defined by length = 30 and normalization level memory 812.
The Viterbi decoding algorithm and metric calculation are performed as shown in the trellis diagram of FIG. The sequence is the same as in the conventional example. Then, as shown in FIG. 4, the Viterbi decoding unit 813 performs the state transition of the decoding path, the adopted path metric (path metric of the adopted path), the next path metric (path metric not adopted at the confluence), and the decoding result. Is stored in the path metric memory 814.
[0100]
Here, the trellis diagram of FIG. 6 will be described. The meanings of symbols and the like in the figure are all the same as in the conventional example, but the decoding result, adopted path metric, next path metric, and SAM value (difference metric = next path metric-adopted path metric) are shown in the lower part of the figure. .
[0101]
Returning to FIG.
(J) The SAM value calculation means 816 reads the metric data stored in the path metric memory 814, and calculates the SAM value (difference metric = next-point path metric−adopted path metric) for each bit (SAM value in FIG. 6). . Further, a SAM value histogram is created, and at the same time, a SAM value that falls within the range of the SAM window stored in the SAM window memory 815 is statistically calculated and a display output as shown in FIG. 7 is performed. In PR (1,1) normalized to −1 to 1, the SAM value is distributed around the ideal value = 2. The larger the SAM value (the larger the difference in the accumulated error amount between the adopted path and the next path), the higher the reliability of the decoding path, and the closer to 0 (the probability of being selected in the adopted path and the next path is 50%). It is said that errors are likely to occur. Therefore, by analyzing the SAM histogram shape, jitter value, and the like, it becomes possible to know how much margin there is for a disk signal error with a small number of data points.
[0102]
(K to e) When the same analysis is repeated, remeasurement is performed.
[0103]
(Ka) If the CLOCK signal needs to be adjusted, if you want to analyze the compatibility with the disc signal using a different PR class, or if you want to change the filter coefficient and analyze the optimal response, Change each setting and try again. In this embodiment, since it is not real-time processing by hardware, it is also possible to analyze using already measured data, and in this case, the sequence is (ad) → (g).
[0104]
FIG. 7 will be described. The trend display is a time series display of SAM values in 1-bit units, and the SAM histogram represents the trend as a histogram viewed from the Y-axis direction. These displays are displayed on a CRT or liquid crystal display mounted on the disk signal analyzer.
[0105]
With this configuration, SAM (difference metric) is used as an evaluation parameter for a disc using PRML signal processing for reproduction. Therefore, 10 6 to 7 to be required in the conventional error rate measurement method. Since the disk signal analysis can be performed with a much smaller number of sampling points than the number of sampling points, the evaluation inspection time can be drastically reduced.
[0106]
In addition, the definition of the original data pattern and the output circuit, which are necessary for the conventional error rate measurement, are not required, so that the circuit scale can be reduced and the component cost can be reduced.
[0107]
In addition, since the number of measurement points may be smaller than that of the conventional error rate measurement, it is possible to implement filter processing and calculation processing by software, and to provide a disk signal analysis device with a high degree of freedom that can be applied to various PRML systems. .
[0108]
Further, since the level direction histogram analysis function and the SAM histogram analysis function are provided, the signal quality in the level direction such as amplitude jitter can be evaluated, and the margin analysis for the disc signal error can be visually performed. This is useful not only for PRML systems but also for signal evaluation in the level direction of a disc recorded with at least two values.
[0109]
In the embodiment, the configuration in which the RF signal and the CLOCK signal are input as the disk signal has been described. However, a configuration in which a PLL (Phase Lock Loop) circuit that regenerates a clock from the input RF signal can be incorporated. Thereby, a signal input system can be simplified.
[0110]
In the embodiment, the tap coefficient is set by the user. However, the tap coefficient is automatically set internally (adaptive equalization) so that the optimum tap number is obtained by using the level jitter value or the SAM value. It is also possible.
[0111]
Further, in the embodiment, all data processing except the input circuit and the A / D conversion circuit is realized by software. However, the PR equalization means and the Viterbi decoding means have a relatively high degree of freedom such as DSP and FPGA. A configuration realized by hardware may be adopted.
[0112]
By the way, when measured with the configuration of FIG. 1, when the level jitter becomes large as shown in FIG. 8 or the SAM jitter becomes large as shown in FIG. Since jitter calculation is performed including the portion, it cannot be handled as an evaluation parameter that approximates a normal distribution as shown in FIG.
[0113]
Also, when the adjacent histogram skirts of the windows overlap, it is not possible to confirm the shape of only the histogram of interest.
[0114]
Furthermore, when the PR class or the coding method is changed, the user has to redo the window setting accordingly.
[0115]
These problems can be solved by adopting the configuration shown in FIG.
In FIG. 11, a portion surrounded by a one-dot broken line is a portion overlapping with FIG. 1, and description thereof is omitted.
The level window selection unit 1110 selects a target window for performing level jitter calculation, and uses a key, a mouse, or the like. The level window information and window state for each level window PR class selected by the level window selection means 1110 are held in the level window memory 1111.
[0116]
The level jitter calculator 1112 calculates the level jitter of the target window from the equalized waveform in the equalized waveform memory 1106, the decoding path in the decoding path memory 1109, and the window information in the level window memory 1111.
[0117]
The SAM window selection unit 1113 selects a target window for performing the SAM jitter calculation unit, and uses a key, a mouse, or the like. The SAM window memory 1114 holds the SAM window information and window state for each PR class selected by the SAM window selection means 1113.
[0118]
In the path pattern table memory 1115, a pattern of an adopted path or a next path corresponding to the SAM value for each PR class is registered.
[0119]
The SAM jitter calculating means 1116 calculates the SAM jitter of the target window from the path metric and decoding state transition of the decoding path memory 1109, the window information of the SAM window memory 1114, and the path pattern of the path pattern table memory 1115.
[0120]
12 is a state diagram of each memory in FIG. 11, FIG. 13 is a state transition diagram of PR (1,1), and FIG. 14 is a trellis diagram of Viterbi decoding.
The level window memory 1107 stores ideal window information of equalized waveforms for each PR class and a selection level window state set by the user. FIG. 12 shows only when the d constraint is 1 in PR (1,1), PR (1,2,1), PR (1,2,2,1) equalized to 0V to 2V. As the selection level window state, Window 2 of PR (1, 1) is selected. The d constraint is a constraint during Viterbi decoding based on the number of consecutive zeros (Run Length) during modulation (encoding). For example, in the case of the (1,7) RLL code, since the minimum RunLength is 1, if d constraint = 1, the decoding pattern in FIG. 13 cannot be 1 → 0 → 1, 0 → 1 → 0, that is, S1 → Viterbi decoding is performed excluding the transitions of S0 → S1 and S0 → S1 → S0.
[0121]
The SAM window 1112 stores window information of an ideal SAM value that appears when Viterbi decoding is performed with a d constraint (= 1) added to a (1,7) RLL code signal, and a selected SAM window set by the user. ing. In the PR class, as the number of convolution bits (constraint length) increases, the number of windows increases, so PR (1,1), PR (1,2,1), PR (1,2,2,1) Up to Window10 is shown. As the selected SAM window state, Window 1 of PR (1, 1) is selected.
[0122]
In the path pattern table memory 1115, the adopted path and the next path pattern (decoding state transition) corresponding to the ideal SAM value for each PR class are registered. Since the number of states increases as the PR constraint length increases, FIG. 12 shows only the case of PR (1, 1).
[0123]
When the path of S0 → S0 → S1 is adopted, S0 → S1 → S1 becomes the next point path. From the state of PR (1, 1) in FIG. 13, when the output becomes 1 → 2 and 0 → 1, respectively, the path metric difference is (1 ² +1 ² ) = 2, and if this path pattern exists, it means that the end point of the path belongs to the SAM = 2 window. Similarly, when S0 → S1 → S1 → S0 is adopted and S0 → S0 → S0 → S0 is the next point, the path metric difference is (1 ² +2 ² +1 ¹ ) = 6, and the end point belongs to the window of SAM = 6. When S0.fwdarw.S0.fwdarw.S0.fwdarw.S0 is adopted, there is no next point path due to the d constraint, so that the difference in path metric is ∞, which means that the end point is data not belonging to any window.
[0124]
The operation will be described based on the flowchart of FIG. Note that since an actual apparatus includes both hardware implementation units and software implementation units, a series of operations are executed and processed in real time and in multitasking. However, in the flowchart of FIG.
(A) Tap coefficients (= α, β, γ...) For waveform equalization are set in the tap coefficient memory 1104, and PR class (= PR (1,1)) for Viterbi decoding is set in the PR class memory 1107. Set to.
[0125]
(B) A level window (for example, Window2: Center = 1.00V Span = 1.00V) to be analyzed by the level window selecting unit 1110 is selected and held in the level window memory 1111, and an SAM window (for example, the SAM window selecting unit 1113 is to be analyzed) Window1: SAM = 2) is selected and held in the SAM window memory 1114.
[0126]
(C) An RF signal is input to the input circuit 1101 from the optical disk head.
[0127]
(D) The RF signal is subjected to signal processing in a desired level direction by an input circuit 1101 including an amplifier, an attenuator, an analog filter, a PLL, and the like, and a CLOCK signal for sampling is reproduced and output by an internal PLL. Is done.
[0128]
(E) The RF signal signal-processed by the input circuit 1101 is A / D converted by the A / D conversion circuit 1102 at the timing of the CLOCK signal, and the digital waveform data is stored in the waveform memory 1103.
[0129]
(F) The PR equalizing unit 1105 performs waveform equalization processing on the waveform data stored in the waveform memory 1103 and stores the waveform data in the equalized waveform memory 1106.
[0130]
(G) Viterbi decoding means 1108 extracts the equalized waveform data stored in the equalized waveform memory 1106, performs Viterbi decoding with the algorithm of PR (1,1), and outputs the decoding state transition to the decoding path memory 1109. Stores the path metric, the next path metric and the decoded data of the path.
[0131]
(H) The level jitter calculator 1112 extracts the equalized waveform data stored in the equalized waveform memory 1106, generates a level histogram from the decoding state transition of the decoding path memory 1109, and is defined in the level window memory 1107 at the same time. The jitter in the target window is calculated by extracting the data in the window. FIG. 16 shows the display output.
[0132]
In the case of PR1, the histogram is distributed in three values centering on 0V, 1V, and 2V, but since the selection level window is Window2, only the data of the ideal level center value = 1.0V is extracted. From the state transition diagram of FIG. 13 and the trellis diagram of FIG. 14, since 1 is output in the case of transition from S0 → S1 or S1 → S0, data of 0.94, 1.05, 1.09, and 0.89 are sequentially extracted. By extracting data using the decoding state transition in this way, even in the case of a signal with a large error, it is possible to create a histogram of only Window 2 as shown in FIG. 16 and calculate the jitter.
[0133]
(I) The SAM jitter calculating means 1116 calculates a SAM from the difference of path metrics stored in the decoding path memory 1109, searches the path pattern table memory 1115 to generate a SAM histogram, and simultaneously generates a SAM window memory. The SAM value in the window defined in 1114 is extracted to calculate the jitter of the target window. FIG. 17 shows the display output.
[0134]
When (1,7) RLL code is Viterbi-decoded with PR (1,1) with d constraint, two histograms are distributed around SAM = 2 and 6, but the selected SAM window is Window1, so the ideal SAM Extract only data with median value = 2.0. 1.78, 2.33, 2.34, 1.80, 1.68, 2.11 and 2.34 are sequentially extracted from the trellis diagram of FIG. 14 and the path pattern memory 1113 (SAM = 2 path pattern) of FIG. By extracting data using a path pattern according to the ideal SAM in this way, even in the case of a signal with a large error, a histogram only for Window 1 as shown in FIG. 17 can be created and jitter can be calculated.
[0135]
(J) When repeating the same conditions, (d) to (i) are repeated continuously as they are. When settings such as the tap coefficient, PR class, analysis level window, and analysis SAM window are changed, the level window information, SAM window information, and path pattern information corresponding to the settings are referred to the table, and the histogram analysis of only the selected window is continued. (Ai).
[0136]
When the error is large and the window protrudes, the bottoms of the histograms of the windows overlap as shown in FIG. 18, but in this embodiment, data extraction is performed using the decoding state transition and decoding path pattern table. Therefore, the jitter is calculated from the histogram of the filled portion.
[0137]
According to the embodiment shown in FIG. 11, since the method of referring to the decoding state transition and the decoding path pattern table is used for data extraction of the level window and the SAM window, the error is so large that the adjacent histogram skirts overlap. Even in this case, data corresponding to the window can be reliably extracted, and jitter analysis can be performed with a histogram having a shape closer to a normal distribution.
[0138]
Since the analysis level window and the analysis SAM window can be selected, only the histogram of the window to be analyzed can be extracted, and the shape analysis of the histogram for each equalized waveform level and the histogram for each SAM value can be performed. .
[0139]
Further, by storing the information of the level window and the SAM window in the memory for each PR class, the user does not need to define the window and the operability is improved.
[0140]
【The invention's effect】
As described above, according to the present invention, when evaluating a disc signal recorded with at least two or more values, the analysis time can be shortened and the circuit scale is small, and it can be applied to various PRML systems and has a high degree of freedom. It is possible to realize a disk signal analyzing apparatus that can appropriately perform histogram analysis even when the error is large and suitable for various kinds of disk signal analysis.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an exemplary embodiment of the present invention.
FIG. 2 is a timing chart for explaining the operation of FIG. 1;
FIG. 3 is a flowchart showing an operation flow of the apparatus of FIG. 1;
FIG. 4 is a memory state diagram inside the apparatus of FIG. 1;
5 is an example of an amplitude histogram and amplitude jitter in FIG.
6 is a trellis diagram of Viterbi decoding in FIG. 1. FIG.
7 is a display screen example of the SAM trend and histogram in FIG. 1;
FIG. 8 is a display screen example of a level histogram and level jitter.
FIG. 9 is a display screen example of a SAM histogram and SAM jitter.
10 is an explanatory diagram of a jitter calculation target histogram in the configuration of FIG. 1;
FIG. 11 is a block diagram showing another embodiment of the present invention.
12 is a state diagram of each memory in FIG. 11;
FIG. 13 is a state transition diagram of PR (1,1).
14 is a trellis diagram of Viterbi decoding in FIG. 11. FIG.
FIG. 15 is a flowchart illustrating the operation flow of FIG. 11;
16 is a display screen example of a level histogram and level jitter in the apparatus of FIG.
17 is a display screen example of a SAM histogram and SAM jitter in the apparatus of FIG.
18 is an explanatory diagram of a jitter calculation target histogram in the configuration of FIG. 11;
FIG. 19 is a block diagram showing an example of a conventional disk signal analyzing apparatus.
FIG. 20 is a configuration example diagram of an Nth-order digital transversal filter.
FIG. 21 is a block diagram of an encoder of PR (1,1).
FIG. 22 is a state transition diagram of PR (1,1).
FIG. 23 is a timing chart for explaining the operation of FIG. 19;
24 is a trellis diagram of Viterbi decoding in FIG.
25 is a flowchart showing an operation flow of the apparatus shown in FIG. 19;
[Explanation of symbols]
801 Delay time memory
802, 1101 input circuit
803, 1102 A / D conversion circuit
804, 1103 Waveform memory
805, 1104 Tap coefficient memory
806, 1105 PR equalization means
807, 1106 Equalized waveform memory
808,1111 level window memory
809, 1112 level jitter calculation means
810, 1107 PR class memory
811 Path memory length memory
812 Normalized level memory
813, 1108 Viterbi decoding means
814 Path Metric Memory
815, 1114 SAM window memory
816 SAM value calculation means
1110 Level window selection means
1113 SAM window selection means
1115 Path pattern table memory

Claims (14)

A disk signal analyzing apparatus for use in analytical evaluation of the recorded disc signal at least two or more values, at least, a PR equalization means for separating a signal waveform in the amplitude direction, the Viterbi decoding output data of the PR equalization means and Viterbi decoding means for calculating a path metric as well as, a SAM value computing means for calculating a SAM (difference metric) from the decoding paths and path metrics calculated in the Viterbi decoding means, SAM window specifying multiple range of the SAM With memory,
The SAM value calculation means creates a histogram for each window from the decoding path, path metric, and SAM window memory output from the Viterbi decoding means, and calculates a statistical value. apparatus. 2. The disk signal analyzing apparatus according to claim 1, wherein a digital transversal filter is used as the PR equalizing means. The digital transversal filter disk signal analyzer according to claim 1 or claim 2, wherein in that a memory for storing the tap coefficients. 4. The disk signal analyzing apparatus according to claim 1, further comprising a PR class memory for storing a PR class for determining an algorithm for the Viterbi decoding. 5. The disk signal analyzing apparatus according to claim 1, further comprising a path memory length memory for storing a maximum path length during the Viterbi decoding. 6. The disk signal analysis apparatus according to claim 1, further comprising an equalization waveform memory for storing equalization waveform data output from the PR equalization means. The normalized level memory for storing a maximum value and a minimum value for defining a range for projecting the equalized waveform data stored in the equalized waveform memory to a normalized level is provided. 6. The disk signal analyzing apparatus according to 6. 2. The disk signal analyzing apparatus according to claim 1, further comprising means for inputting an RF signal and a clock signal as the disk signal and adjusting a phase of the clock signal. 2. The disk signal analyzing apparatus according to claim 1, further comprising means for inputting an RF signal as the disk signal and reproducing a clock signal from the RF signal. A level window memory specifying multiple level ranges, from the output of the range and the PR equalization means of the level window memory, level jitter calculating means for calculating a statistical value by creating a histogram of each of said windows includes a city The disk signal analyzing apparatus according to claim 1, wherein 11. The disk signal analyzing apparatus according to claim 10, wherein the level jitter calculating means updates the tap coefficient memory to an optimum value using an adaptive equalization filter algorithm based on the calculated statistic. 12. The disk signal analyzing apparatus according to claim 1 or 11, wherein a decoding state transition and a decoding path pattern table are referred to when extracting data of the level window and the SAM window. Disk signal analyzer according to claim 12, characterized in that extract only histogram window to be these analyzes the level window and analyzed like SAM window to be analyzed as a possible choice. Disk signal analyzer according to claim 1 or claim 13, characterized in that a memory for storing information of the level window and SAM window for each PR class.

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