JP2008005921A - Game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a game machine capable of demonstrating a desired image processing performance without increasing the number of memories provided in a control means for image processing. <P>SOLUTION: The game machine includes a CGROM 83 for storing two or more pieces of image data including the image data of identification information and a plotting processor for performing the processing of making an image display device 9 display images on the basis of the image data stored in the CGROM 83 in response to the command of a microcomputer for performance control. The CGROM 83 includes ROMs 83A and 83B from which the image data are read when the bus width of a data bus is set to 64 bits and a ROM 83C from which the image data are read when the bus width of the data bus is set to 32 bits. Moving image data are stored in the ROM 83C, and the plotting processor changes the setting of the bus width of the data bus to 32 bits when reading the image data from the ROM 83C. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention can perform variable display of a plurality of types of identification information that can be identified by each image display device, and can control to a specific gaming state advantageous to the player when the display result of the identification information becomes a specific display result. The present invention relates to a game machine such as a pachinko machine.

  As a gaming machine such as a pachinko machine, a variable display is performed by updating and displaying predetermined identification information (for example, a symbol) on an image display device such as a liquid crystal display (LCD), and a stop symbol (display) There is a game that enhances the game interest by executing a so-called variable display game that informs whether or not to give a predetermined game value depending on the result.

  The variable display game is a game in which when the “big hit” occurs, the stop symbol form when the symbol update display is completely stopped is changed to a specific display form. When it is a “hit”, it is very easy to win a game ball in the big prize opening by opening a special electric accessory called a big prize opening. Then, the player is provided with a state in which the winning of the game ball is extremely easy for a certain period of time.

  Hereinafter, a state in which the prize winning opening is in an open state and the winning of a game ball is extremely easy is referred to as a specific game state. When entering the specific gaming state, for example, the stop symbol pattern of the display symbol displayed on the image display device becomes a predetermined specific display mode (generally, the stop symbols are aligned in the same symbol).

  In the variable display game, the player pays attention to whether or not the mode of the stop symbol becomes the specific display mode and becomes a “hit”. For this reason, various effects are displayed to enhance the game entertainment, such as changing the variation of the symbols, until the symbol is finalized (final stop) so that it can be determined whether or not it will be a “big hit”. Is called.

  As such an effect, for example, in the image display device, a symbol other than the symbol that becomes the final stop symbol (for example, the middle symbol of the left and right middle symbols) continues for a predetermined time and matches a specific display result. Before the final result is displayed, such as when it is stopped, swinging, enlarged or reduced or deformed, or when multiple symbols change synchronously with the same symbol, or the position of the displayed symbol is switched. There is a reach effect performed in a state where the possibility of occurrence of big hits is continuing (hereinafter, these states are referred to as reach states). Further, the reach state and its state are referred to as a reach mode. Furthermore, variable display including reach production is called reach variable display.

  Usually, a drawing processor for drawing (for image processing) is mounted on a control board for controlling the image display device. Further, the control board is provided with a ROM for storing various image data, and a frame memory that is a RAM for developing an image displayed on the image display device. The drawing processor reads predetermined image data stored in the ROM based on an instruction from the host CPU that performs display control, and expands the read image data in a predetermined area of the frame memory. Then, an image is displayed on the image display device based on the image data read from the frame memory. Note that when the image data stored in the ROM is compressed, the drawing processor performs a process of expanding the image data read from the ROM. Such a drawing processor is generally provided with a function to draw (synthesize) a still image or a moving image (hereinafter also referred to as a movie image).

  As described above, the drawing processor reads image data from the ROM and writes or reads image data to the RAM. In general, data transfer between the drawing processor and the ROM and RAM is performed via a data bus.

In order to improve the image processing performance of the drawing processor, it is conceivable to increase the bus width of the data bus. When the bus width of the data bus is wide (for example, 64 bits), the data transfer speed between the rendering processor and the ROM and RAM is substantially smaller than when the bus width is narrow (for example, 16 bits or 32 bits). This is because the image processing speed is increased. In addition, there is a gaming machine in which when a plurality of RAMs are provided, the image processing performance is improved by configuring the bus between the drawing processor and the RAM to be switchable (see, for example, Patent Document 1). .)
Japanese Patent Publication No. 2006-75457 (paragraphs 0038-0040)

  However, when the bus width of the data bus is wide, a ROM or RAM that matches the bus width must be used. For example, when the bus width of the data bus is 64 bits, it is necessary to use a ROM or RAM capable of inputting / outputting 64 bits of data or two ROMs or RAMs capable of inputting / outputting 32 bits of data. In general, ROMs and RAMs capable of inputting and outputting 64-bit data are more expensive than ROMs and RAMs capable of inputting and outputting 32-bit data, and the manufacturing cost of gaming machines is increased. In addition, when two ROMs and RAMs are used, the manufacturing cost of the gaming machine is naturally higher than when one ROM and RAM are used.

  The disadvantage that the manufacturing cost of the gaming machine becomes high is particularly remarkable when the capacity of the ROM or RAM may be small. For example, unless it is specially manufactured, generally only ROM or RAM having a fixed capacity such as 64 kbytes or 256 kbytes can be obtained. Then, even when it is sufficient to use a small capacity ROM or RAM, it may be necessary to use a large capacity ROM or RAM. In that case, when it is necessary to use a ROM or RAM capable of inputting / outputting 64-bit data, or using two ROMs or RAM capable of inputting / outputting 32-bit data, the manufacturing cost is further increased. Become.

  Therefore, an object of the present invention is to provide a gaming machine that can exhibit desired image processing performance without increasing the number of memories used in the control means for image processing.

  The gaming machine according to the present invention performs variable display of a plurality of types of identification information (for example, decorative symbols) that can be identified by an image display device (for example, the image display device 9), and the display result of the identification information is specified and displayed. A gaming machine that can be controlled to a specific gaming state (for example, a jackpot gaming state) advantageous to the player when a result (for example, a jackpot symbol) is achieved, and a command for controlling the display state of the image display device An effect control microcomputer to perform (for example, effect control microcomputer 100), an image data storage means (for example, CGROM 83) for storing a plurality of image data including image data of each identification information, and a data bus (for example, The image data stored in the image data storage means via the CG bus is connected to the image data storage means so that it can be read out. A drawing processor (for example, a drawing processor 109) that performs processing for displaying an image on the image display device based on the image data stored in the image data storage means in response to a command from the microcomputer; The means includes a first ROM (eg, ROM 83A, 83B) from which image data is read when the bus width of the data bus is set to the first bus width (eg, 64 bits), and the bus width of the data bus. Includes a second ROM (for example, ROM 83C) from which image data is read when the second bus width (for example, 32 bits) is set to be narrower than the first bus width. Is stored with moving image data (for example, compressed data), and when the drawing processor reads the image data from the second ROM, The bus width setting is changed from the first bus width to the second bus width (for example, the upper 32 bits of the CG bus according to the fact that “1” is set in the data bus mode register in the process of step S963). Is disabled).

  The second ROM stores moving image data in a compressed state, and the drawing processor may be configured to include decoding means (for example, a moving image decompression unit 89) for decoding the compressed data. Good.

  The effect control microcomputer is a display effect selection means (for example, in the effect control microcomputer 100) that selects a display effect to be executed on the image display device when variable display of identification information is performed from a plurality of types of display effects. , A portion for executing the processing of steps S840 and S842. A variation pattern to be used may be selected from a plurality of types of variation patterns in accordance with the received variation pattern command), and the plurality of types of display effects are displayed on the image display device. When the display result of the identification information is a specific display result, it includes a predetermined display effect (for example, a super reach effect) that is easier to select than when it is not a specific display result. When the predetermined display effect is selected as the display effect, the bus width setting of the data bus is set to the second Read the image data from the second ROM (for example, in response to selection of a process table including process data indicating transfer of moving image data, the data bus mode register is read in step S966). After “1” is set and the processing of steps S981 to S985 is executed, the processing of steps S1041 to S1052 may be executed).

  The first ROM (eg, ROM 83A, 83B) may be configured to store a sprite image (eg, still image data) used for displaying identification information as image data.

  The drawing processor includes a storage unit (for example, a VRAM 84B) that stores image data read from the image data storage unit, a frame storage unit (for example, a frame memory 84A) in which image data is set, and a frame storage unit. An image display means (for example, a display signal control unit 87) for displaying an image on the image display device based on the set image data, and when the power supply to the gaming machine is started, the use frequency is determined from the predetermined image data. Transfer means for reading high image data from the image data storage means and transferring it to a fixed storage area in the storage means (for example, a fixed area in the VRAM 84B) (for example, the disease is executed by the processor 109 in steps S924 and S925) Based on this, the processing of steps S1001 to S1006 is executed. And when the image data to be set in the frame storage means is transferred to the fixed storage area, the image data is read from the fixed storage area and the frame is read out. Set in the storage means (for example, execute the processes in steps S1025 to S1030 based on the execution of the processes in steps S972 to S976), and set the frame storage means when setting the image data in the frame storage means When the image data to be processed is not transferred to the fixed storage area, the image data is read from the image data storage means, and the read image data is set in the frame storage means via the temporary storage area in the storage means (for example, step Based on the execution of the processing of S981 to S984, Tsu processing execution flop S1031～S1040) may be configured so.

  The plurality of types of identification information is common identification information (for example, decoration corresponding to image data stored in the common image data area) used in any of the plurality of game modes (for example, production modes # 1 to # 3). And a transfer means for each of the gaming machines, wherein each of the plurality of selection identification information used in each of the plurality of gaming modes (for example, a decorative pattern corresponding to the image data stored in the selected image data area). When the power supply is started, the image data of the common identification information is read from the image data storage unit and transferred to the fixed storage area in the storage unit (for example, the step based on the processing in steps S924 and S925 being executed). The processing of S1001 to S1006 is executed), and the image of the selection identification information used in the game mode when the game mode is confirmed The data may be read from the image data storage unit and transferred to the storage unit (for example, the processing of steps S1011 to S1021 is executed based on the execution of the processing of steps S877 and S941 to 951). Good.

  In the first aspect of the invention, the image data storage means includes a first ROM from which image data is read when the bus width of the data bus is set to the first bus width, and the bus width of the data bus is the first bus width. And a second ROM from which image data is read out when the second bus width is set to be narrower than the first bus width. The second ROM stores moving image data, and a drawing processor When the image data is read from the second ROM, the bus width setting of the data bus is changed from the first bus width to the second bus width. The ROM of the image data storage means from which the image data is read when the second bus width is changed is more than the ROM from which the image data is read out when the bus width of the data bus is set to the first bus width. ,Few Tsu capture the data input and output can ROM can be used for, as a result, there is an effect of reducing the number of used memory constituting the image data storage means. In addition, the bus width of the data bus becomes narrower when reading moving image data, but since the control of moving images in the rendering processor takes more time than the control of still images, image processing is possible even if the bus width is reduced. The performance can be prevented from deteriorating.

  In the second aspect of the invention, the moving image data is stored in the second ROM in a compressed state, and the drawing processor includes a decoding unit for decoding the compressed data. Since it takes more time than still image control, even if the bus width is narrowed to reduce the image data reading speed, the image processing performance does not deteriorate.

  In the invention according to claim 3, when the display processor selects the predetermined display effect as the display effect, the drawing processor changes the bus width setting of the data bus to the second bus width, Since the image data is read out from the ROM, the moving image data stored in the second ROM is used when the predetermined display effect is selected, which reduces the image processing performance. Therefore, it is possible to execute a game effect that improves the interest of the game.

  In the invention according to claim 4, since the sprite image used for displaying the identification information as image data is stored in the first ROM, the identification information can be processed quickly. Can do.

  According to the fifth aspect of the present invention, when the drawing processor starts to supply power to the gaming machine, it reads out image data whose use frequency is higher than the predetermined image data from the image data storage means, and the fixed storage area in the storage means When the image data to be set in the frame storage means is transferred to the fixed storage area when the image data is set in the frame storage means, the image data is read from the fixed storage area and stored in the frame storage means. Since it is configured to set, the image data can be quickly set in the frame storage means when the variable display of the identification information is performed, and the image after switching to the image display device (variable) Displayed image) can be displayed. Further, after power supply to the gaming machine is started, it is not necessary to read out frequently used image data from the image data storage means, and the processing load on the drawing processor can be reduced.

  In the invention according to claim 6, when the power supply to the gaming machine is started, the transfer means reads the image data of the common identification information from the image data storage means, transfers it to the fixed storage area in the storage means, and the game mode Since the image data of the selected identification information used in the game mode is read from the image data storage means and transferred to the storage means when the game is confirmed, the image data of a plurality of identification information for each game mode Compared with storing image data in the image data storage means, the storage capacity of the image data storage means can be reduced. Further, after the variable display of the identification information is started for the first time, it is not necessary to read the image data of the common identification information from the image data storage means, and the processing load on the drawing processor can be reduced.

Embodiment 1 FIG.
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
First, the overall configuration of a pachinko gaming machine that is an example of a gaming machine will be described. FIG. 1 is a front view of a pachinko gaming machine as viewed from the front. In the following embodiment, a pachinko gaming machine will be described as an example. However, the gaming machine according to the present invention is not limited to a pachinko gaming machine, and a predetermined number of gaming media are paid out as prizes according to the game. It can also be applied to other gaming machines such as slot machines.

  The pachinko gaming machine 1 includes an outer frame (not shown) formed in a vertically long rectangular shape and a game frame attached to the inside of the outer frame so as to be openable and closable. Further, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape that is provided in the game frame so as to be opened and closed. The game frame includes a front frame (not shown) installed to be openable and closable with respect to the outer frame, a mechanism plate to which mechanism parts and the like are attached, and various parts attached to them (excluding a game board described later). Is a structure including

  As shown in FIG. 1, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2 is a hitting ball supply tray (upper plate) 3. Under the hitting ball supply tray 3, an extra ball receiving tray 4 for storing game balls that cannot be accommodated in the hit ball supply tray 3 and a hitting operation handle (operation knob) 5 for launching the game balls are provided. A game board 6 is detachably attached to the back surface of the glass door frame 2. The game board 6 is a structure including a plate-like body constituting the game board 6 and various components attached to the plate-like body. A game area 7 is formed on the front surface of the game board 6.

  Near the center of the game area 7, an image display device (variable display device) 9 including a plurality of variable display portions each variably displaying a decorative pattern for performance is provided. The image display device 9 has, for example, three variable display portions (symbol display areas) of “left”, “middle”, and “right”. The image display device 9 performs variable display of the decorative symbol as a decorative symbol (for production) during the variable symbol special symbol display period of the special symbol indicator 8. The image display device 9 that performs variable display of decorative designs is controlled by an effect control microcomputer mounted on the effect control board and a drawing processor. At the bottom of the image display device 9, four special symbol hold memory indicators 18 for displaying the number of valid winning balls that have entered the start winning opening 14, that is, the number of hold memories (also referred to as start memory or start prize memory), are provided. ing. The special symbol reservation storage display 18 displays up to four reservation storage numbers in the order of winning. The special symbol hold storage display 18 increases the number of LEDs in the lit state by 1 each time there is a start winning in the start winning opening 14. Then, each time the special symbol display 8 starts variable display, the special symbol hold storage indicator 18 reduces the number of LEDs in the lit state by 1 (that is, turns off one LED). Specifically, the special symbol hold storage display 18 shifts the lighting state each time variable display is started on the special symbol display 8. In this example, the upper limit number (up to 4) is provided for the number of starting memories by winning to the start winning opening 14, but the upper limit number may be four or more.

  A special symbol display (special symbol display device) 8 that variably displays a special symbol as identification information is provided on the upper part of the image display device 9. In this embodiment, the special symbol display 8 is realized by a simple and small display (for example, 7 segment LED) capable of variably displaying numbers 0 to 9, for example. The special symbol display 8 may be configured to variably display a larger number of numbers such as 0 to 99 in order to make it difficult for the player to grasp a specific stop symbol. Further, the image display device 9 performs variable display of the decorative symbol as a symbol for decoration (for production) during the variable symbol display period of the special symbol by the special symbol indicator 8.

  Below the image display device 9 is provided a variable winning ball device 15 that forms a start winning opening 14. The variable winning ball device 15 is opened by the solenoid 16, and when the variable winning ball device 15 is opened, the game ball can be easily won at the start winning port 14. The game ball won in the start winning opening 14 is guided to the back of the game board 6 and detected by the start opening switch 14a.

  Below the variable winning ball apparatus 15, a special variable winning ball apparatus 20 that is opened by a solenoid 21 in a specific gaming state (big hit state) is provided. The special variable winning ball apparatus 20 has an opening / closing plate, and the large winning opening (variable winning ball apparatus) is opened by controlling the opening / closing plate to be opened. The winning ball that has won the special variable winning ball device 20 is detected by the count switch 23.

  When a game ball wins the gate 32 and is detected by the gate switch 32a, the variable display of the normal symbol display 10 is started. In this embodiment, variable display is performed by alternately lighting left and right lamps (designs can be visually recognized when lit). For example, if the right lamp is lit at the end of variable display, it is a win. When the stop symbol on the normal symbol display 10 is a predetermined symbol (winning symbol), the variable winning ball device 15 is opened for a predetermined number of times. In the vicinity of the normal symbol display 10, a normal symbol start memory display 41 having a display unit with four LEDs for displaying the number of winning balls entered into the gate 32 is provided. Each time there is a prize at the gate 32, the normal symbol start memory display 41 increases the number of LEDs to be turned on by one. Then, every time variable display on the normal symbol display 10 is started, the number of LEDs to be lit is reduced by one.

  The game board 6 is provided with a plurality of winning ports (ordinary winning ports) 29, 30, 33, and 39. The winning holes 29, 30, 33, and 39 for the game balls are awarded to the winning port switches 29a and 30a, respectively. , 33a, 39a. Each winning opening 29, 30, 33, 39 constitutes a winning area provided in the game board 6 as an area for accepting game media and allowing winning. The start winning opening 14 and the big winning opening also constitute a winning area that accepts game media and allows winning. Decorative lamps 25 blinking and displayed during the game are provided around the left and right sides of the game area 7, and an outlet 26 for absorbing a game ball that has not won a prize is provided at the bottom. Two speakers 27 that emit sound effects are provided on the left and right upper portions outside the game area 7. On the outer periphery of the game area 7, a top frame lamp 28a, a left frame lamp 28b, and a right frame lamp 28c are provided. Further, a decoration LED is installed around each structure (such as a big prize opening) in the game area 7. The top frame lamp 28a, the left frame lamp 28b, the right frame lamp 28c, and the decoration LED are examples of a decorative light emitter provided in the gaming machine.

  In this example, a prize ball LED 51 that is lit while paying out a prize ball is provided in the vicinity of the left frame lamp 28b, and a ball break LED 52 that is lit when the refill ball is cut is provided in the vicinity of the top frame lamp 28a. It has been. As described above, the pachinko gaming machine 1 of this embodiment is provided with lamps and LEDs as light emitters in various places. Further, a prepaid card unit (hereinafter also simply referred to as a “card unit”) that enables ball lending by inserting a prepaid card is installed adjacent to the pachinko gaming machine 1 (not shown).

  The card unit includes, for example, a use indicator lamp that indicates whether or not the card unit is in a usable state, a connection table direction indicator that indicates which side of the pachinko gaming machine 1 corresponds to the card unit, When checking the card insertion indicator lamp indicating that the card is inserted, the card insertion slot into which the card as a recording medium is inserted, and the card reader / writer mechanism provided on the back of the card insertion slot A card unit lock is provided to release the unit.

  The game balls launched from the hit ball launching device enter the game area 7 through the hit ball rail, and then descend the game area 7. When the game ball enters the start winning opening 14 and is detected by the start opening switch 14a, the special symbol on the special symbol display 8 starts variable display (variation) as long as the variable display of the symbol can be started. The decorative design on the display device 9 starts variable display (variation). If it is not in a state where the variable display of symbols can be started, the start winning memory number is increased by one.

  The variable display of the special symbol on the special symbol display 8 and the variable display of the decorative symbol on the image display device 9 are stopped when a certain time has passed. If the special symbol (stop symbol) at the time of stoppage is a jackpot symbol (specific display result), the game shifts to a jackpot gaming state. That is, the special variable winning ball apparatus 20 is released until a predetermined time elapses or a predetermined number (for example, 10) of gaming balls wins.

  When the game ball wins the gate 32, the normal symbol display unit 10 is in a state where the normal symbol is variably displayed. Further, when the stop symbol on the normal symbol display 10 is a predetermined symbol (winning symbol), the variable winning ball device 15 is opened for a predetermined time. Further, in the probability variation state, the probability that the stop symbol in the normal symbol display 10 becomes a winning symbol is increased, and the opening time and the number of times of opening of the variable winning ball device 15 are increased.

  FIG. 2 is a block diagram showing an example of the circuit configuration of the main board (game control board) 31. 2 also shows the payout control board 37, the effect control board 80, and the like. A game control microcomputer (corresponding to game control means) 560 for controlling the pachinko gaming machine 1 according to a program is mounted on the main board 31. The game control microcomputer 560 includes a ROM 54 for storing a game control (game progress control) program and the like, a RAM 55 as storage means used as a work memory, a CPU 56 for performing control operations in accordance with the program, and an I / O port unit 57. including. In this embodiment, the ROM 54 and the RAM 55 are built in the game control microcomputer 560. That is, the game control microcomputer 560 is a one-chip microcomputer. The one-chip microcomputer only needs to incorporate at least the CPU 56 and the RAM 55, and the ROM 54 may be external or built-in. The I / O port unit 57 may be externally attached.

  In the game control microcomputer 560, the CPU 56 executes control in accordance with a program stored in the ROM 54. Therefore, the game control microcomputer 560 (or the CPU 56) executes (or performs processing) hereinafter. Specifically, the CPU 56 executes control according to a program. The same applies to microcomputers mounted on substrates other than the main substrate 31.

  Further, an input driver circuit 58 for supplying detection signals from the gate switch 32a, the start port switch 14a, the count switch 23, and the winning port switches 29a, 30a, 33a, 39a to the game control microcomputer 560 is also mounted on the main board 31. Yes. The main board also includes an output circuit 59 for driving the solenoid 16 for opening and closing the variable winning ball device 15 and the solenoid 21 for opening and closing the special variable winning ball device 20 that forms a big winning opening in accordance with a command from the game control microcomputer 560. 31. Further, a system reset circuit (not shown) for resetting the game control microcomputer 560 when the power is turned on, and an information output signal such as jackpot information indicating the occurrence of a jackpot gaming state are sent to an external device such as a hall computer. An information output circuit (not shown) for outputting is also mounted on the main board 31.

  In this embodiment, the effect control means (configured by the effect control microcomputer) mounted on the effect control board 80 receives the effect control command from the game control microcomputer 560 via the relay board 77. The display control of the image display device 9 that receives and displays the decorative design variably is performed.

  FIG. 3 is a block diagram illustrating a circuit configuration example of the relay board 77, the effect control board 80, the lamp driver board 35, and the audio output board 70. In the example shown in FIG. 3, the lamp driver board 35 and the audio output board 70 are not equipped with a microcomputer, but may be equipped with a microcomputer. Further, without providing the lamp driver board 35 and the audio output board 70, only the effect control board 80 may be provided for effect control.

  The effect control board 80 has an effect control microcomputer 100 including an effect control CPU 101 and a RAM. The RAM may be externally attached. In the effect control board 80, the effect control CPU 101 operates in accordance with a program stored in a built-in or external ROM (not shown), and receives a capture signal from the main board 31 input via the relay board 77 ( In response to the (effect control INT signal), an effect control command is received via the input driver 102 and the input port 103. Further, the effect control CPU 101 causes the drawing processor (VDP: video display processor) 109 to perform display control of the image display device 9 based on the effect control command.

  In this embodiment, a rendering processor 109 that controls the display of the image display device 9 in cooperation with the rendering control microcomputer 100 is mounted on the rendering control board 80. The drawing processor 109 has an address space independent of the effect control microcomputer 100, and maps the VRAM therein. VRAM is a buffer memory for developing image data. Then, the drawing processor 109 outputs the image data in the VRAM to the image display device 9 via the frame memory.

  The effect control CPU 101 outputs a command for reading necessary data from the CGROM (not shown) to the drawing processor 109 in accordance with the received effect control command. The CGROM stores character image data and moving image data displayed on the image display device 9, specifically, a person, characters, figures, symbols (including decorative designs), and background image data in advance. ROM. The drawing processor 109 reads image data from the CGROM in response to the instruction from the effect control CPU 101. Then, the drawing processor 109 executes display control based on the read image data.

  The effect control command and the effect control INT signal are first input to the input driver 102 on the effect control board 80. The input driver 102 allows the signal input from the relay board 77 to pass only in the direction toward the inside of the effect control board 80 (does not pass the signal in the direction from the inside of the effect control board 80 to the relay board 77). It is also a unidirectional circuit as a regulating means.

  As a signal direction regulating means, the signal inputted from the main board 31 is allowed to pass through the relay board 77 only in the direction toward the effect control board 80 (the signal is not passed in the direction from the effect control board 80 to the relay board 77). The unidirectional circuit 74 is mounted. For example, a diode or a transistor is used as the unidirectional circuit. FIG. 3 illustrates a diode. A unidirectional circuit is provided for each signal. Furthermore, since the effect control command and the effect control INT signal are output from the main board 31 via the output port 571 that is a unidirectional circuit, the signal from the relay board 77 toward the inside of the main board 31 is restricted. That is, the signal from the relay board 77 does not enter the inside of the main board 31 (the game control microcomputer 560 side). The output port 571 is a part of the I / O port unit 57 shown in FIG. Further, a signal driver circuit that is a unidirectional circuit may be further provided outside the output port 571 (on the relay board 77 side).

  Further, the effect control CPU 101 outputs a signal for driving the lamp to the lamp driver board 35 via the output port 105. Further, the production control CPU 101 outputs sound number data to the audio output board 70 via the output port 104.

  In the lamp driver board 35, a signal for driving the lamp is input to the lamp driver 352 via the input driver 351. The lamp driver 352 amplifies a signal for driving the lamp and supplies the amplified signal to each lamp provided on the frame side such as the top frame lamp 28a, the left frame lamp 28b, and the right frame lamp 28c. Further, it is supplied to a decorative lamp 25 provided on the frame side.

  In the voice output board 70, the sound number data is input to the voice synthesis IC 703 via the input driver 702. The voice synthesizing IC 703 generates voice or sound effect according to the sound number data, and outputs it to the amplifier circuit 705. The amplification circuit 705 outputs an audio signal obtained by amplifying the output level of the speech synthesis IC 703 to a level corresponding to the volume set by the volume 706 to the speaker 27. The voice data ROM 704 stores control data corresponding to the sound number data. The control data corresponding to the sound number data is a collection of data indicating the sound effect or sound output mode in a time series in a predetermined period (for example, a decorative symbol variation period).

  FIG. 4 is a block diagram showing a circuit configuration of the drawing processor 109. FIG. 4 also shows a CPU (production control CPU) 101, a ROM 112 for storing production control programs, various production patterns such as symbol display, light emission, and voice output, and a RAM 113 used as a work memory. ing.

  When executing the display control of the image display device 6, the effect control CPU 101 gives a command corresponding to the effect control command to the drawing processor 109. The drawing processor 109 reads necessary data from the CGROM 83 or the like in accordance with the command. The drawing processor 109 generates image data to be displayed on the image display device 9 according to the input data, and outputs R (red), G (green), B (blue) signals and a synchronization signal to the image display device 9. . The image display device 9 performs, for example, screen display by a dot matrix system that drives a large number of pixels (pixels).

  The SDRAM 84 has a frame buffer area and a VRAM area. The drawing processor 109 includes a drawing control unit 91, a display signal control unit 87 for outputting a signal to the image display device 9, and a moving image decompression unit 89 that performs a moving image decoding process. The drawing control unit 91 includes a VRAM address generation unit and the like.

  A CG bus and a VRAM bus are provided inside the drawing processor 109. A CG bus interface (CG bus I / F) 93 is installed between the CGROM 83 and the CG bus. The CPU I / F 92 is also connected to the CG bus, and the effect control CPU 101 can access the portion connected to the CG bus via the CPU I / F 92. Specifically, the effect control CPU 101 can access the drawing control register 95 connected to the CG bus. The drawing control register 95 stores a command from the effect control CPU 101 to the drawing control unit 91. A VRAM I / F 94 is installed between the SDRAM 84 and the VRAM bus. Note that the moving picture decompression unit 89 can access the VRAM 84 via the VRAM bus, and can access the drawing control register 95 and the CGROM 83 via the CG bus.

  Next, the operation of the gaming machine will be described. FIG. 5 is a flowchart showing main processing executed by the game control microcomputer 560 on the main board 31. When the gaming machine is turned on and the input level of the reset terminal to which the reset signal is input becomes high level, the game control microcomputer 560 (specifically, the CPU 56) determines whether the contents of the program are valid. After executing the security check process, which is a process for confirming whether or not, the main process after step S1 is started. In the main process, the CPU 56 first performs necessary initial settings.

  In the initial setting process, the CPU 56 first sets the interrupt prohibition (step S1). Next, the interrupt mode is set to interrupt mode 2 (step S2), and a stack pointer designation address is set to the stack pointer (step S3). After initialization of the built-in device (CTC (counter / timer) and PIO (parallel input / output port), which are built-in devices (built-in peripheral circuits)) is performed (step S4), the RAM is accessible (Step S5). In interrupt mode 2, the address synthesized from the value (1 byte) of the specific register (I register) built in the CPU 56 and the interrupt vector (1 byte: least significant bit 0) output from the built-in device is interrupted. It is a mode that indicates a cover address.

  Next, the CPU 56 checks the state of the output signal of the clear switch (for example, mounted on the power supply board) input via the input port (step S6). When the on-state is detected in the confirmation, the CPU 56 executes a normal initialization process (steps S10 to S15).

  If the clear switch is not on, check whether data protection processing of the backup RAM area (for example, power supply stop processing such as addition of parity data) was performed when power supply to the gaming machine was stopped (Step S7). When it is confirmed that such protection processing is not performed, the CPU 56 executes initialization processing. Whether there is backup data in the backup RAM area is confirmed, for example, by the state of the backup flag set in the backup RAM area in the power supply stop process. In this example, if “55H” is set in the backup flag area, it means that there is a backup (ON state), and if a value other than “55H” is set, it means that there is no backup (OFF state).

  After confirming that there is a backup, the CPU 56 performs a data check of the backup RAM area (parity check in this example) (step S8). In step S8, the calculated checksum is compared with the checksum calculated and stored by the same process in the power supply stop process. When the power supply is stopped after an unexpected power failure or the like, the data in the backup RAM area should be saved, so the check result (comparison result) is normal (matched). That the check result is not normal means that the data in the backup RAM area is different from the data when the power supply is stopped. In such a case, since the internal state cannot be returned to the state when the power supply is stopped, an initialization process that is executed when the power is turned on is not performed when the power supply is stopped.

  If the check result is normal, the CPU 56 performs a game state restoration process for returning the internal state of the game control means and the control state of the electrical component control means such as the effect control means to the state when the power supply is stopped. Specifically, the start address of the backup setting table stored in the ROM 54 is set as a pointer (step S41), and the contents of the backup setting table are sequentially set in the work area (area in the RAM 55) (step S42). ). The work area is backed up by a backup power source. In the backup setting table, initialization data for an area that may be initialized in the work area is set. As a result of the processing in steps S41 and S42, the saved contents of the work area that should not be initialized remain as they are. The parts that should not be initialized include, for example, data indicating the gaming state before the power supply is stopped (special symbol process flag, etc.), the area where the output state of the output port is saved (output port buffer), unpaid prize balls This is the part where data indicating the number is set.

  Further, the CPU 56 performs a game state restoration process (step S43). In the gaming state recovery process, the CPU 56 performs control to transmit a power failure recovery command as an initialization command at the time of power supply recovery. Then, the process proceeds to step S15.

  In this embodiment, it is confirmed whether the data in the backup RAM area is stored using both the backup flag and the check data. However, only one of them may be used. That is, either the backup flag or the check data may be used as an opportunity for executing the game state restoration process.

  In the initialization process, the CPU 56 first performs a RAM clear process (step S10). The entire area of the RAM 55 may not be initialized, and predetermined data (for example, count value data of a counter for generating a big hit determination random number) may be left as it is. Further, the start address of the initialization setting table stored in the ROM 54 is set as a pointer (step S11), and the contents of the initialization setting table are sequentially set in the work area (step S12).

  By the processing of steps S11 and S12, for example, a normal symbol determination random number counter, a normal symbol determination buffer, a special symbol buffer, a total prize ball number storage buffer, a special symbol process flag, an award ball flag, a ball out flag, and a payout stop An initial value is set to a flag such as a flag for selectively performing processing according to the control state.

  Further, the CPU 56 sets an initialization command transmission request flag in order to transmit an initialization command for initializing the sub board to the sub board (step S13). Examples of the initialization command include a command indicating an initial symbol displayed on the image display device 9.

  In step S15, the CPU 56 sets a register of the CTC built in the game control microcomputer 560 so that a timer interrupt is periodically taken every predetermined time (for example, 2 ms). That is, a value corresponding to, for example, 2 ms is set in a predetermined register (time constant register) as an initial value. In this embodiment, it is assumed that a timer interrupt is periodically taken every 2 ms.

  When the execution of the initialization process (steps S10 to S15) is completed, the CPU 56 repeatedly executes the display random number update process (step S17) and the initial value random number update process (step S18) in the main process. When executing the display random number update process and the initial value random number update process, the interrupt disabled state is set (step S16). When the display random number update process and the initial value random number update process are finished, the interrupt enabled state is set. Set (step S19). In this embodiment, the display random number is a random number for determining the variation pattern, and the display random number update process is a process for updating the count value of the counter for generating the display random number. The initial value random number update process is a process for updating the count value of the counter for generating the initial value random number. The initial value random number is a random number for determining an initial value of a count value, such as a counter for generating a random number for determining whether or not to make a big hit (a big hit determination random number generation counter). A game control process for controlling the progress of the game, which will be described later (the game control microcomputer 560 itself controls game devices such as an image display device, a variable winning ball device, a ball payout device, etc. provided in the gaming machine. In a process to transmit, a command signal to be controlled by another microcomputer, or a game device control process), the count value of the jackpot determination random number generation counter or the like is one round (a jackpot determination random number generation counter or the like) When the value is incremented by the number of values between the minimum value and the maximum value that can be taken, the initial value is set in the counter.

  When the timer interrupt occurs, the CPU 56 executes the timer interrupt process in steps S20 to S34 shown in FIG. In the timer interrupt process, first, a power-off detection process for detecting whether or not a power-off signal is output (whether or not an on-state is turned on) is executed (step S20). The power-off signal is output when, for example, a voltage drop monitoring circuit mounted on the power supply board detects a drop in the voltage of the power supplied to the gaming machine. In the power-off detection process, when detecting that the power-off signal has been output, the CPU 56 executes a power supply stop process for saving necessary data in the backup RAM area. Next, detection signals of the gate switch 32a, the start port switch 14a, the count switch 23, and the winning port switches 29a, 30a, 33a, and 39a are input via the input driver circuit 58, and the state determination is performed (switch processing). : Step S21).

  Next, the CPU 56 executes a display control process for performing display control of the special symbol display 8, the normal symbol display 10, the special symbol hold storage display 18, and the normal symbol hold storage display 41 (step S22). For the special symbol display 8 and the normal symbol display 10, control for outputting a drive signal to each display is executed according to the contents of the output buffer set in steps S32 and S33.

  Next, a process of updating the count value of each counter for generating each determination random number such as a big hit determination random number used for game control is performed (determination random number update process: step S23). The CPU 56 further performs a process of updating the count value of the counter for generating the initial value random number and the display random number (initial value random number update process, display random number update process: steps S24 and S25).

FIG. 7 is an explanatory diagram showing each random number. Each random number is used as follows.
(1) Random 1: Decide whether or not to generate a big hit in response to the variable display of a special symbol based on the winning of a game ball at the start winning opening (for big hit determination)
(2) Random 2: Determines the special symbol detachment symbol (stop symbol) (for detachment symbol determination)
(3) Random 3: Determines the special symbol stop symbol when generating a big hit (for big hit symbol determination)
(4) Random 4: Determine the variation pattern (variation time) of the special symbol (for variation pattern determination)
(5) Random 5: Determines whether or not to generate a hit based on a normal symbol (for normal symbol hit determination)
(6) Random 6: Determine the initial value of random 1 (for determining the random 1 initial value)
(7) Random 7: Determine the initial value of random 5 (for determining the random 5 initial value)

  In step S23 in the game control process shown in FIG. 6, the game control microcomputer 560 determines (1) big hit determination random number, (3) big hit symbol determination random number, and (5) normal symbol hit determination. The counter for generating a random number for use is incremented (added by 1). That is, they are determination random numbers, and other random numbers are display random numbers or initial value random numbers. In addition, in order to improve a game effect, you may make it use random numbers other than the random number of said (1)-(7). In this embodiment, the big hit determination random number is a software random number generated based on a program by the game control microcomputer 560. However, as the big hit determination random number, hardware external to the game control microcomputer 560 is used. Alternatively, a random number generated by hardware built in the game control microcomputer 560 may be used.

  Further, the CPU 56 performs special symbol process processing (step S26). In the special symbol process, the corresponding symbol is executed in accordance with a special symbol process flag for controlling the special symbol display 8 and the special winning award in a predetermined order. The CPU 56 updates the value of the special symbol process flag according to the gaming state.

  Next, normal symbol process processing is performed (step S27). In the normal symbol process, the CPU 56 executes a corresponding process according to the normal symbol process flag for controlling the display state of the normal symbol display 10 in a predetermined order. The CPU 56 updates the value of the normal symbol process flag according to the gaming state.

  Further, the CPU 56 performs a process of sending an effect control command to the effect control microcomputer 100 (effect control command control process: step S28).

  Further, the CPU 56 performs information output processing for outputting data such as jackpot information, start information, probability variation information supplied to the hall management computer, for example (step S29).

  Further, the CPU 56 executes prize ball processing for setting the number of prize balls based on the detection signals of the start port switch 14a, the count switch 23, and the prize opening switches 29a, 30a, 33a, 39a (step S30). Specifically, the payout control mounted on the payout control board 37 in response to winning detection based on any of the start opening switch 14a, the count switch 23 and the winning opening switches 29a, 30a, 33a, 39a being turned on. A payout control command indicating the number of prize balls is output to the microcomputer. The payout control microcomputer drives the ball payout device 97 in accordance with a payout control command indicating the number of winning balls.

  In this embodiment, a RAM area (output port buffer) corresponding to the output state of the output port is provided. However, the CPU 56 relates to on / off of the solenoid in the RAM area corresponding to the output state of the output port. The contents are output to the output port (step S31: output process).

  Further, the CPU 56 performs special symbol display control processing for setting special symbol display control data for effect display of the special symbol in the output buffer for setting the special symbol display control data according to the value of the special symbol process flag ( Step S32). For example, if the variation speed is 1 frame / 0.2 seconds until the end flag is set when the start flag set in the special symbol process is set, the CPU 56, for example, every 0.2 seconds passes. Then, the value of the display control data set in the output buffer is incremented by one. Further, the CPU 56 performs variable display of the special symbol on the special symbol display 8 by outputting a drive signal in step S22 according to the display control data set in the output buffer.

  Further, the CPU 56 performs a normal symbol display control process for setting normal symbol display control data for effect display of the normal symbol in an output buffer for setting the normal symbol display control data according to the value of the normal symbol process flag ( Step S33). For example, when the start flag related to the variation of the normal symbol is set, the CPU 56 switches the display state (“◯” and “×”) for the variation rate of the normal symbol every 0.2 seconds until the end flag is set. With such a speed, the value of the display control data set in the output buffer (for example, 1 indicating “◯” and 0 indicating “x”) is switched every 0.2 seconds. Further, the CPU 56 outputs a normal signal on the normal symbol display 10 by outputting a drive signal in step S22 according to the display control data set in the output buffer. Thereafter, the interrupt permission state is set (step S34), and the process is terminated.

  With the above control, in this embodiment, the game control process is started every 2 ms. The game control process corresponds to the processes in steps S21 to S33 (excluding step S29) in the timer interrupt process. In this embodiment, the game control process is executed by the timer interrupt process. However, in the timer interrupt process, for example, only a flag indicating that an interrupt has occurred is set, and the game control process is performed by the main process. May be executed.

  FIG. 8 is an explanatory diagram showing an example of the jackpot determination value. The CPU 56 extracts the count value of the counter for generating the big hit determination random number at a predetermined time and uses the extracted value as the big hit determination random value. The big hit determination random number is shown in FIG. If it coincides with the judgment value, it is determined that the special symbol is a big hit (probability big hit or normal big hit). In FIG. 8B, numerical values are not shown and the number of numerical values is shown. In the normal state, the CPU 56 compares the jackpot determination random number value with the jackpot determination value described in FIG. In the probability variation state, the jackpot determination random number value is compared with the jackpot determination values set for the number of pieces described in FIG. The numerical values described in FIG. 8A are set in the ROM 54 as normal jackpot determination values, and the numerical values for the number of numbers described in FIG. 8B are set in the ROM 54 as probability variation big hit determination values. Yes. The probability variation big hit is a big hit that shifts the gaming state after the big hit game to a probable state where there is a high probability of being determined to be a big hit compared to the normal state. Usually, the big hit is a big hit that shifts the gaming state after the big hit game to a state that is not a probable change state.

  In the probability variation state, the probability that the stop symbol of the normal symbol is determined as a winning symbol may be increased, the opening time of the variable winning ball device 15 may be increased, or the number of times of opening may be increased.

  FIG. 9 is an explanatory diagram showing an example of a plurality of types of decorative symbols that are variably displayed on each of the “left”, “middle”, and “right” variable display portions on the display screen of the image display device 9. In this embodiment, in each of the “left”, “middle”, and “right” variable display portions provided on the display screen of the image display device 9, the symbols indicating the numbers “1” to “9” are, for example, It is variably displayed in combination with a predetermined figure such as a quadrangle, a circle, a substantially diamond, or a star hexagon. A corresponding symbol number is assigned to each of the decorative symbols. The arrangement of decorative symbols displayed in each variable display section includes a common symbol displayed in the same display mode regardless of whether the production state (production mode) is production mode # 1 to # 3, and production. Selection symbols displayed in different display modes according to modes # 1 to # 3 are included.

  For example, symbols indicating numbers “1” to “6”, “8”, and “9” are combined with a rectangular figure regardless of which of the production modes # 1 to # 3. The symbol indicating the number “7” is combined with a circular figure when in the production mode # 1, combined with a substantially rhombus figure when in the production mode # 2, and a star-shaped hexagon when in the production mode # 3. Combined with the figure. The decorative symbols corresponding to the symbol numbers “1” to “6”, “8”, and “9” are common symbols, and the decorative symbol corresponding to the symbol number “7” is a selected symbol.

  In this embodiment, the effect mode is controlled to effect mode # 1 when the game state is the normal state, and the effect mode is controlled to effect mode # 2 when the game state is the short time state, and the game state The production mode is controlled to the production mode # 3 when is in a certain change state. However, such a method of dividing the production mode is an example. For example, the player can select the production mode by operating means such as a push button provided on the gaming machine, or according to the time. You may comprise so that production mode may be switched.

  FIG. 10 is an explanatory diagram showing an example of a variation pattern used in this embodiment. In FIG. 10, “EXT” indicates the second byte of EXT data in the effect control command having a two-byte structure. “Variation time” indicates the variation time of the special symbol (variable display period of identification information).

  “Normal fluctuation” is a fluctuation pattern without a reach mode. “Normal reach” is a variation pattern that is accompanied by a reach mode but whose display result (stop symbol) does not become a big hit symbol. “Reach A” is a variation pattern having a reach form different from “normal reach”. Different reach modes mean that different modes of change (speed, direction of rotation, etc.), characters, etc. appear in the reach change time (the period during which the reach effect is performed). For example, in “normal reach”, a reach mode is realized by only one type of change mode, whereas in “reach A”, a reach mode including a plurality of change modes having different speeds and directions of change is realized.

  “Reach B” is a fluctuation pattern having a reach mode different from “Normal reach” and “Reach A”. “Reach C” is a variation pattern having a reach form different from “normal reach”, “reach A”, and “reach B”. “Super reach” is a variation pattern having a reach manner different from “normal reach”, “reach A”, “reach B”, and “reach C”, and is a variation pattern having a reach manner by moving images. Note that “reach A”, “reach B”, and “reach C” may or may not be a big hit. In addition, “Super Reach” may be a big hit or not a big hit, but if variable display by “Super Reach” is executed, the stop symbol becomes a big hit symbol at a very high rate. In “Super Reach”, it may always be a big hit.

  “Normal variation / shortening” is a variation pattern that does not involve a reach mode, but the variation time (variable display time) is shorter than “normal variation”. “Reach A / shortening” is a variation pattern having a reach manner similar to “reach A”, but the reach variation time is shorter than “reach A”. “Reach B / shortening” is a variation pattern having a reach manner similar to “reach B”, but the reach variation time is shorter than “reach B”.

  11A to 11D are explanatory diagrams illustrating an example of a variation pattern table. The CPU 56 extracts a count value of a counter for generating a variation pattern determination random number at a predetermined time and uses the extracted value as the variation pattern determination random number. The variation pattern determination random number is shown in FIG. When the number of determination values matches the number of determination values, the variation pattern corresponding to the determination value is determined as the variation pattern to be used. Therefore, the variation pattern table is a table in which a determination value to be compared with the variation pattern determination random number is set in correspondence with the variation pattern. The variation pattern table is set in the ROM 54.

  FIG. 11A shows a variation pattern table (outlier variation pattern table) used when the gaming state is the normal state and it is determined to be out of play. FIG. 11B is a variation pattern table (big hit variation pattern table) used when the gaming state is a normal state and it is determined to be a big hit. FIG. 11C shows a variation pattern table (displacement variation pattern table at the time shortening) used when the gaming state is the probability variation state or the time reduction state and is determined to be out of play. FIG. 11D is a fluctuation pattern table (short-time big hit fluctuation pattern table) used when the gaming state is a probability change state or a short-time state and is determined to be a big hit.

  In the probability variation state and the short time state, the variation time of the special symbol is shortened compared to the normal state. In addition, the normal symbol variation time may be shortened in the probability variation state and the short time state.

  In this embodiment, the same variation pattern table is used in both the probability variation state and the short-time state. That is, although the types of variation patterns to be selected are the same, the variation pattern group used in the probability variation state (can be used). A plurality of variation patterns) and a variation pattern group used in the short-time state may be separated.

  Next, a method for sending a control command from the game control microcomputer 560 to the effect control microcomputer 100 will be described. FIG. 12 is an explanatory diagram showing a signal line of an effect control command transmitted from the main board 31 to the effect control board 80. As shown in FIG. 12, in this embodiment, the effect control command is transmitted from the main board 31 to the effect control board 80 via the relay board 77 by using eight signal lines of the effect control signals D0 to D7. Further, between the main board 31 and the effect control board 80, a signal line of the effect control INT signal for transmitting the capture signal (effect control INT signal) is also wired.

  In this embodiment, the effect control command has a 2-byte structure, the first byte represents MODE (command classification), and the second byte represents EXT (command type). The first bit (bit 7) of the MODE data is always set to “1”, and the first bit (bit 7) of the EXT data is always set to “0”. Note that such a command form is an example, and other command forms may be used. For example, a control command composed of 1 byte or 3 bytes or more may be used.

  As shown in FIG. 13, the 8-bit effect control command data of the effect control command is output in synchronization with the effect control INT signal. The effect control microcomputer 100 mounted on the effect control board 80 detects that the effect control INT signal has risen, and starts a 1-byte data capturing process through an interrupt process. Therefore, when viewed from the effect control microcomputer 100, the effect control INT signal corresponds to a signal that triggers the capture of effect control command data.

  The effect control command is sent only once so that the effect control microcomputer 100 can recognize it. In this example, “recognizable” means that the level of the effect control INT signal changes, and that it is sent only once so as to be recognizable means that, for example, each of the first and second bytes of the effect control command data Accordingly, the production control INT signal is output in a pulse shape (rectangular wave shape) only once. The effect control INT signal may have a polarity opposite to that shown in FIG.

  FIG. 14 is an explanatory diagram showing an example of the contents of the effect control command transmitted by the game control microcomputer 560. In the example shown in FIG. 14, commands 8001 (H) to 8009 (H) are effect control commands (variation) for designating a variation pattern of decorative symbols that are variably displayed on the image display device 9 in response to variable display of special symbols. Pattern command). The effect control command for designating the variation pattern is also a command for designating the start of variation. Therefore, when receiving any one of the commands 8001 (H) to 8009 (H), the effect control microcomputer 100 controls the image display device 9 to start variable display of decorative symbols. In this embodiment, since the variable display of the special symbol and the variable display of the decorative symbol are synchronized (the variable display start time and the variable display end time are the same), the decorative pattern variation pattern (variation time) Determining also means determining the variation pattern (variation time) of the special symbol.

  The commands 8C01 (H) to 8C05 (H) are effect control commands indicating whether or not to make a big hit and a gaming state after the big hit game. The effect control microcomputer 100 determines the display result of the decorative symbols in response to the reception of the commands 8C01 (H) to 8C05 (H). Therefore, the commands 8C01 (H) to 8C05 (H) are referred to as display result specifying commands.

  The command 8F00 (H) is an effect control command (symbol confirmation designation command) indicating that the special symbol variable display (variation) is terminated and the display result (stop symbol) is derived and displayed. When receiving the symbol confirmation designation command, the effect control microcomputer 100 ends the variable display (fluctuation) of the decorative symbols and derives and displays the display result. The derived display is to finally stop and display the symbol.

  Command 9000 (H) is an effect control command (power-on designation command) transmitted when power supply to the gaming machine is started. Command 9200 (H) is an effect control command (power failure recovery designation command) transmitted when power supply to the gaming machine is resumed. When the power supply to the gaming machine is started, the gaming control microcomputer 560 transmits a power failure recovery designation command if data is stored in the backup RAM, and if not, designates power-on. Send a command.

  Command 9F00 (H) is an effect control command (customer waiting demonstration designation command) for designating a customer waiting demonstration.

  The command A000 (H) is an effect control command for displaying the fanfare screen, that is, designating the start of the big hit game (big hit start designation command: fanfare designation command). The command A1XX (H) is an effect control command (special command during opening of a big winning opening) indicating a display during the opening of the big winning opening for the number of times (round) indicated by XX. A2XX (H) is an effect control command (designation command after opening the big winning opening) indicating the closing of the big winning opening for the number of times (round) indicated by XX. The command A300 (H) is an effect control command for displaying the jackpot end screen, that is, the end of the jackpot game (a jackpot end designation command: an ending designation command).

  The command C0XX (H) is an effect control command (holding memory number designation command) for designating the starting winning memory number (holding memory number). XX indicates the number of reserved memories.

  The effect control microcomputer 100 (specifically, the effect control CPU 101) mounted on the effect control board 80 receives the above-described effect control command from the game control microcomputer 560 mounted on the main board 31. Then, the display state of the effect display device 9 is changed according to the content shown in FIG. 14, the display state of the lamp is changed, and the sound number data is output to the audio output board 70.

  FIG. 15 is an explanatory diagram illustrating an example of the transmission timing of the effect control command. As shown in FIG. 15, the game control microcomputer 560 transmits a variation pattern command, a display result specifying command, and a pending storage number designation command at the start of variation. When the variable display time has elapsed, a symbol confirmation designation command is transmitted.

  Note that before transmitting the variation pattern command, a background designation command for designating a background image in the image display device 9 according to the gaming state (eg, normal state / short time state / probability variation state) may be transmitted. In that case, out of the display result specifying commands shown in FIG. 14, the display result specifying commands (display result 1 specifying command, display result 2 specifying command, display result 3 specifying command) specified for losing may be combined into one command. it can.

  FIG. 16 is a flowchart illustrating an example of a special symbol process (step S26) program executed by the game control microcomputer 560 (specifically, the CPU 56) mounted on the main board 31. As described above, in the special symbol process, a process for controlling the special symbol display 8 and the special winning opening is executed. In the special symbol process, the CPU 56 performs start port switch passing processing if the start port switch 14a for detecting that a game ball has won the start winning port 14 is turned on, that is, if a start winning has occurred. Execute (step S312). Then, any one of steps S300 to S310 is performed.

  The processes in steps S300 to S310 are as follows.

  Special symbol normal processing (step S300): Executed when the value of the special symbol process flag is zero. When the game control microcomputer 560 is ready to start the variable display of the special symbol, it checks the number of reserved memories (the number of start winning memories). The reserved memory number can be confirmed by the count value of the reserved memory number counter. Then, the internal state (special symbol process flag) is updated to a value (1 in this example) corresponding to step S301.

  Special symbol stop symbol setting process (step S301): Executed when the value of the special symbol process flag is 1. The stop symbol after the variable display of the special symbol is determined. Then, the internal state (special symbol process flag) is updated to a value (2 in this example) corresponding to step S302.

  Fluctuation pattern setting process (step S302): executed when the value of the special symbol process flag is 2. The variation pattern is determined, and the variation time in the variation pattern (variable display time: the time from when variable display is started until the display result is derived and displayed (stop display)) is used as the variable symbol variable display variation time. To decide. In addition, a variation time timer that measures the variation time of the determined special symbol is started. Then, the internal state (special symbol process flag) is updated to a value (3 in this example) corresponding to step S303.

  Display result specifying command transmission process (step S303): executed when the value of the special symbol process flag is 3. Control for transmitting a display result specifying command to the production control microcomputer 100 is performed. Then, the internal state (special symbol process flag) is updated to a value (4 in this example) corresponding to step S304.

  Reserved memory number transmission processing (step S304): This processing is executed when the value of the special symbol process flag is 4. Control is performed to transmit a reserved memory number designation command to the production control microcomputer 100. Then, the internal state (special symbol process flag) is updated to a value (5 in this example) corresponding to step S305.

  Special symbol changing process (step S305): This process is executed when the value of the special symbol process flag is 5. When the variation time of the variation pattern selected in the variation pattern setting process elapses (the variation time timer set in step S302 times out, that is, the variation time timer value becomes 0), the internal state (special symbol process flag) is stepped. Update to a value corresponding to S306 (6 in this example).

  Special symbol stop process (step S306): This is executed when the value of the special symbol process flag is 6. The variable display on the special symbol display 8 is stopped and the stop symbol is derived and displayed. In addition, control for transmitting a symbol confirmation designation command to the effect control microcomputer 100 is performed. If the big hit flag is set, the internal state (special symbol process flag) is updated to a value corresponding to step S307 (7 in this example). If the big hit flag is not set, the internal state (special symbol process flag) is updated to a value corresponding to step S300 (0 in this example). The effect control microcomputer 100 controls the image display device 9 to stop the decorative symbols when it receives the symbol confirmation designation command transmitted by the game control microcomputer 560.

  Big hit display process (step S307): This process is executed when the value of the special symbol process flag is 7. A predetermined period is measured by the big hit display time timer, and when the predetermined period elapses, the internal state (special symbol process flag) is updated to a value corresponding to step S308 (8 in this example).

  Preliminary winning opening opening process (step S308): executed when the value of the special symbol process flag is 8. In the pre-opening process for the big prize opening, control for opening the big prize opening is performed. Specifically, a counter (for example, a counter that counts the number of game balls that have entered the big prize opening) is initialized, and the solenoid 21 is driven to open the big prize opening. Also, the execution time of the special prize opening opening process is set by the timer, and the internal state (special symbol process flag) is updated to a value corresponding to step S309 (9 in this example). The pre-opening process for the big winning opening is executed for each round, but when the first round is started, the pre-opening process for the big winning opening is also a process for starting the big hit game.

  Large winning opening opening process (step S309): This process is executed when the value of the special symbol process flag is 9. A control for transmitting an effect control command for round display during the big hit gaming state to the effect control microcomputer 100, a process for confirming the completion of the closing condition of the big prize opening, and the like are performed. If the closing condition for the big prize opening is satisfied and there are still remaining rounds, the internal state (special symbol process flag) is updated to shift to step S308. When all rounds are completed, the internal state (special symbol process flag) is updated to a value corresponding to step S310 (in this example, 10 (decimal number)).

  Big hit end process (step S310): executed when the value of the special symbol process flag is 10. Control for causing the microcomputer 100 for effect control to perform display control for notifying the player that the big hit gaming state has ended is performed. Further, a process for setting a flag (for example, a probability variation flag) indicating a gaming state is performed. Then, the internal state (special symbol process flag) is updated to a value (0 in this example) corresponding to step S300.

  FIG. 17 is a flowchart showing the start port switch passing process in step S312. In the start port switch passing process, the CPU 56 checks whether or not the reserved storage number is 4 which is the upper limit value (step S111). If the number of reserved memories is 4, the process is terminated.

  When the number of reserved memories is not 4, the value of the reserved memory number counter indicating the number of reserved memories is incremented by 1 (step S112). Further, the CPU 56 extracts software random numbers (such as a counter value for generating a jackpot determination random number), and stores them as a storage area in the reserved storage buffer corresponding to the value of the reserved storage number counter as the extracted random number value. The process to store in is executed (step S113). In the reserved storage buffer, the same number of storage areas as the upper limit value of the reserved storage number are secured. Further, a counter for generating a jackpot determination random number and the like and a holding storage buffer are formed in the RAM 55. In step 113, random values 1 to 4 (see FIG. 7) are extracted and stored in the storage area. Further, control is performed to transmit a reserved memory number designation command in which the value of the reserved memory number counter is set in the EXT data (step S114).

  Specifically, when the CPU 56 transmits an effect control command to the effect control microcomputer 100, the address of the command transmission table corresponding to the effect control command (preliminarily set for each command in the ROM) is given. Set to pointer. And the address of the command transmission table according to an effect control command is set to a pointer, and an effect control command is transmitted in an effect control command control process (step S28).

  Further, the image display device 9 is provided with a reserved memory number display area, and the effect control microcomputer 100 displays an image indicating the reserved memory number designated by the received reserved memory number designation command in the reserved memory number display area. It may be configured.

  FIG. 18 is a flowchart showing the special symbol normal process (step S300) in the special symbol process. In the special symbol normal process, the CPU 56 checks the value of the number of reserved storage (step S51). Specifically, the count value of the pending storage number counter is confirmed.

  If the reserved memory number is not 0, the CPU 56 reads out each random number value stored in the storage area corresponding to the reserved memory number = 1 in the reserved memory number buffer of the RAM 55 and stores it in the random number buffer area of the RAM 55 (step S52). Then, the value of the reserved memory number is decreased by 1 (the count value of the reserved memory number counter is decremented by 1), and the contents of each storage area are shifted (step S53). That is, each random number value stored in the storage area corresponding to the reserved memory number = n (n = 2, 3, 4) in the reserved memory number buffer of the RAM 55 is stored in the storage area corresponding to the reserved memory number = n−1. To store. Therefore, the order in which the random number values stored in the respective storage areas corresponding to the number of reserved memories is extracted always matches the order of the number of reserved memories = 1, 2, 3 and 4. Yes. Thereafter, the value of the special symbol process flag is updated to a value corresponding to the special symbol stop symbol setting process (step S301) (step S54).

  FIG. 19 is a flowchart showing the special symbol stop symbol setting process (step S301) in the special symbol process. In the special symbol stop symbol setting process, the CPU 56 reads random 1 (random number for jackpot determination) from the random number buffer area (step S61), and executes the jackpot determination module (step S62). The jackpot determination module is a program that compares a jackpot determination value (see FIG. 8) determined in advance with a jackpot determination random number, and executes a process of determining a jackpot if they match. Note that when the gaming state is in a probable change state, the CPU 56 uses the jackpot determination value in the table in which jackpot determination values for the number as shown in FIG. 8B are set, and the gaming state is in the normal state (time reduction). (Including the state), the jackpot determination value in the table in which the jackpot determination value as shown in FIG. 8A is set is used. If it is determined to be a big hit (step S63), the process proceeds to step S81. Note that deciding whether or not to make a big hit means deciding whether or not to shift to the big win gaming state, but deciding whether or not to make the stop symbol in the special symbol display 8 a big hit symbol. It is also a thing.

  If it is decided not to win, the CPU 56 reads out the design symbol random number from the random number buffer area (step S64), and determines the stop symbol based on the design symbol random number (step S65). In this case, an off symbol (for example, any of even symbols) is determined. Then, the process proceeds to step S90.

  In step S81, the CPU 56 sets a big hit flag. Then, the big hit symbol determining random number is read from the random number buffer area (step S82), and the big hit symbol (for example, one of the odd symbols) is determined as the stop symbol based on the big hit symbol determining random number (step S83). Here, the stop symbol is determined without distinguishing between the probability variation big hit and the normal big hit, but the stop symbol may be determined separately. For example, when it is determined that the probability variation big hit, the stop symbol is determined as “7”, and when it is determined as the normal big hit, the stop symbol is determined as any one of the odd symbols other than “7”. May be.

  Next, the CPU 56 sets a probability variation jackpot flag if it is determined to be a probability variation jackpot (steps S84 and S85). Then, the value of the special symbol process flag is updated to a value corresponding to the variation pattern setting process (step S302) (step S86). When the probability change big hit flag is set, the game state is shifted to the probability change state when the big hit game ends.

  In step S90, the CPU 56 checks whether or not the probability variation flag is set. If not set, the process proceeds to step S95. If it is set, the value of the probability variation counter is decremented by 1 (step S91). When the value of the probability variation counter reaches 0, a probability variation end flag is set (steps S92 and S93), and the process proceeds to step S86. If the value of the probability variation counter is not 0, the process proceeds to step S86 as it is. When the probability change end flag is set, the gaming state is shifted from the probability change state to the time-short state when the variable symbol special display is ended.

  In step S95, the CPU 56 checks whether or not the time reduction flag is set. If not set, the process proceeds to step S86. If it is set, the value of the time reduction counter is decremented by 1 (step S96). When the value of the time reduction counter becomes 0, the time reduction end flag is set (steps S97, S98), and the process proceeds to step S86. If the value of the time reduction counter is not 0, the process proceeds to step S86 as it is. In addition, when the short-time end flag is set, the gaming state is shifted from the short-time state to the normal state when the variable symbol special display ends.

  In this embodiment, whether or not to make a big hit and whether or not to control the probability variation state is determined based on the big hit determination random number (see FIG. 8), but based on the big hit determination random number And determining whether or not to make a big hit, and determining to control to a probable change state when a predetermined big win symbol (predetermined probability variation big hit symbol) is determined based on the random number for determining the big hit symbol You may do it.

  FIG. 20 is a flowchart showing the variation pattern setting process (step S302) in the special symbol process. In the variation pattern setting process, the CPU 56 reads the variation pattern determination random number from the random number buffer area (step S101). Then, a variation pattern is selected from the variation pattern table (see FIG. 11) based on the variation pattern determination random number (step S102). Here, when the gaming state is the normal state and it is determined to be out of play, a variation pattern is selected from the out-of-range variation pattern table (see FIG. 11A). When the gaming state is a normal state and it is determined to be a big hit, a fluctuation pattern is selected from the big hit fluctuation pattern table (see FIG. 11B). When the gaming state is a probability change state or a time reduction state and it is determined to be out of play, a variation pattern is selected from the deviation variation pattern table (see FIG. 11C) during the time reduction. When the gaming state is a probability change state or a time saving state and it is determined to be a big hit, a fluctuation pattern is selected from the time reduction big hit fluctuation pattern table (see FIG. 11D).

  Then, the CPU 56 performs control to transmit a variation pattern command (see FIG. 14) corresponding to the variation pattern selected in step S102 to the effect control microcomputer 100 (step S103). Moreover, the variation of the special symbol is started (step S104). For example, a start flag referred to in the special symbol display control process in step S32 is set. Further, a value corresponding to the variation time is set in the variation time timer formed in the RAM 55 (step S105). Then, the value of the special symbol process flag is updated to a value corresponding to the display result specifying command transmission process (step S303) (step S106).

  FIG. 21 is a flowchart showing the display result specifying command transmission process (step S303). In the display result specifying command transmission process, the CPU 56 performs control to transmit an effect control command (see FIG. 14) of any one of display result 1 designation to display result 5 designation (step S107). Here, if it is decided to win the probability big hit, a display result 5 designation command is transmitted, and if it is decided to make the normal big hit, a display result 4 designation command is transmitted. If the probability change end flag is set in the process of step S93, a display result 2 designation command is transmitted. If the time reduction end flag is set in the process of step S98, a display result 3 designation command is transmitted. To do. Otherwise, a display result 1 designation command is transmitted. Then, the value of the special symbol process flag is updated to a value corresponding to the reserved storage number designation command transmission process (step S304) (step S108).

  FIG. 22 is a flowchart showing the pending storage number designation command transmission process (step S304). In the reserved memory number designation command transmission process, the CPU 56 performs control to transmit a reserved memory number designation command in which the value of the reserved memory number counter is set in the EXT data (step S117). Thereafter, the value of the special symbol process flag is updated to a value corresponding to the special symbol changing process (step S305) (step S118).

  FIG. 23 is a flowchart showing the special symbol changing process (step S305) in the special symbol process. In the special symbol changing process, the CPU 56 subtracts 1 from the variable time timer (step S121), and when the variable time timer times out (step S122), the value of the special symbol process flag corresponds to the special symbol stop process (step S306). The updated value is updated (step S123). If the variable time timer has not timed out, the process ends.

  FIG. 24 is a flowchart showing the special symbol stop process (step S306) in the special symbol process. In the special symbol stop process, the CPU 56 sets an end flag referred to in the special symbol display control process in step S32 to end the variation of the special symbol, and performs control for deriving and displaying the stop symbol on the special symbol display unit 8. (Step S131). Moreover, control which transmits the symbol determination designation | designated command to the microcomputer 100 for production control is performed (step S132). If the big hit flag is not set, the process proceeds to step S141 (step S133).

  When the big hit flag is set, control for transmitting the big hit start designation command is performed (step S135). In addition, a value corresponding to the jackpot display time (a time for notifying the occurrence of the jackpot in the image display device 9, for example) is set in the jackpot display time timer (step S136), and the value of the special symbol process flag is set to the jackpot display processing ( The value is updated to a value corresponding to step S307) (step S137). In the big hit display process, when the big hit display time timer times out, the CPU 56 updates the value of the special symbol process flag to a value corresponding to the big winning opening opening pre-process (step S308).

  In step S141, the CPU 56 checks whether or not the probability variation end flag is set. If the probability variation end flag is not set, the process proceeds to step S146. If the probability variation end flag is set, the probability variation end flag is reset (step S142), the probability variation flag is reset and the probability variation state is terminated (step S143). Further, the time reduction flag is set to change the gaming state to the time reduction state (step S144). 50 is set in the hour / hour counter indicating the number of possible fluctuations in the hour / short state (step S145). Then, the process proceeds to step S149.

  In step S146, the CPU 56 checks whether or not the time reduction end flag is set. If the time saving end flag is not set, the process proceeds to step S149. If the time reduction end flag is set, the time reduction end flag is reset (step S147), and the time reduction flag is reset to end the time reduction state (step S148). The gaming state shifts to the normal state by resetting the time reduction flag.

  Then, the value of the special symbol process flag is updated to a value corresponding to the special symbol normal process (step S300) (step S149).

  FIG. 25 is a flowchart showing the big hit end process (step S310) in the special symbol process. In the jackpot end process, the CPU 56 resets the jackpot flag (step S151) and performs control to transmit a jackpot end designation command (step S152).

  Then, it is confirmed whether or not the probability variation big hit flag is set (step S153). If the probability variation jackpot flag is set, the probability variation jackpot flag is reset (step S154). A probability change flag is set to shift the gaming state to the probability change state (step S155). If the gaming state at that time is a probability variation state, the probability variation flag has already been set. Further, if the gaming state at that time is the time saving state, the time saving flag is reset (step S156). Then, 100 is set in the probability variation counter indicating the number of possible fluctuations in the probability variation state (step S157), and the value of the special symbol process flag is updated to a value corresponding to the special symbol normal process (step S300) (step S158).

  If the probability variation big hit flag is not set, it is confirmed whether or not the probability variation flag is set (step S161). If the probability change flag is set, the probability change flag is reset (step S162), the time reduction flag is set (step S163), and the gaming state is shifted from the probability change state to the time reduction state. In addition, 50 is set in the time reduction counter (step S164), and the process proceeds to step S158.

  If the probability change flag is not set, if the gaming state at that time is a short-time state, the short-time flag is reset to shift the gaming state from the short-time state to the normal state (step S165), and the process proceeds to step S158. Transition.

  Next, an example of the variation of the decorative design will be described. 26 and 27 are explanatory diagrams showing the display state of the image display device 9 when the reach effect by super reach is executed. The rectangles shown in FIGS. 26A to 27P indicate display screens in the image display device 9. At the start timing of variable display, the left middle right symbol indicating the previous variable display result as shown in FIG. 26A starts rotating, and the left middle right symbol as shown in FIG. It will be in a rotated state. After high-speed rotation is performed for a predetermined period and the left symbol is rotated at a low speed by several symbols, when the left symbol is temporarily stopped, the left symbol is temporarily stopped as shown in FIG. The temporary stop state is a state where the stop symbol is stopped at a stage before the stop symbol is confirmed (finally stopped). In the temporary stop state, for example, the symbol fluctuates up and down or from side to side.

  Next, after the right symbol is rotated at a low speed by several symbols, when the right symbol is temporarily stopped, the right symbol is temporarily stopped as shown in FIG. 26 (D). In this example, the left and right symbols are both “7” and the reach is temporarily stopped. This is called reach establishment. After reaching the reach display state as shown in FIG. 26D, a reach effect by super reach is executed.

  In reach production by super reach, production by medium speed rotation is first executed. Specifically, as shown in FIG. 26 (E), after “reach” is displayed to notify that the reach state has been reached, the middle symbol is rotated at a low speed by several symbols, and then the middle symbol is displayed. When the temporary stop timing is reached, the middle symbol is temporarily stopped as shown in FIG. When the middle symbol is temporarily stopped, the effect by the medium speed rotation ends.

  When the effect by the medium speed rotation is finished, the effect by the high speed rotation is executed. Specifically, as shown in FIG. 26 (G), after the display of “high-speed reach” for informing that the reach effect by high-speed rotation is executed, the high-speed rotation of the middle symbol is performed for a predetermined period. When the intermediate symbol temporary stop timing is reached, the intermediate symbol is temporarily stopped as shown in FIG. When the middle symbol is temporarily stopped, the effect of high-speed rotation ends.

  When the effect by the high speed rotation is finished, the moving image effect is executed. In the moving image effect, as shown in FIG. 27 (I), the display of “special reach” for notifying that the effect further developed than the effect by the high-speed rotation is executed is displayed, and the left and right during the temporary stop are displayed. The symbol is reduced and moved to the lower part of the screen, and the middle symbol starts to rotate at high speed. Next, moving image display based on the moving image data is started, and display control is performed so that the character image gradually appears as shown in FIG. As shown in FIG. 27 (K), after the character image is completely displayed, the intermediate symbol is temporarily stopped at the temporary stop timing of the intermediate symbol. In the temporarily stopped state of the middle symbol, as shown in FIG. 27 (L), a moving image in which the character image swings down the hammer is displayed. In this example, moving image data for displaying a character image as a moving image is created so that the place where the middle symbol during the temporary stop is located coincides with the place where the hammer is swung down. Therefore, on the display screen of the image display device 9, an effect display is realized in which the character image swings down the hammer and hits the middle symbol that is temporarily stopped.

  Next, the temporarily stopped middle symbol disappears from the screen, and as shown in FIG. 27 (M), the middle symbol (“7” in this example) displayed next to the disappeared symbol descends from the top of the screen. A coming display is made. As shown in FIG. 27 (N), when the middle symbol coming down from the upper part of the screen is in a temporary stop state, the moving image performs an operation such that the character image poses with the right hand based on the moving image data. An image is displayed. Then, as shown in FIG. 27 (O), a display is made such that the character image gradually disappears. When the character disappears completely, the moving image effect based on the moving image data ends, and the left middle right symbol is finally stopped and displayed as shown in FIG. When the left middle right symbol is stopped and displayed, the moving image effect is completed and the super reach effect is completed.

  In this embodiment, the moving image display based on the moving image data in Super Reach and the decorative design are configured to be displayed synchronously on the image display device 9, but a moving image including each decorative design is displayed. The moving image data for reproducing the image is not created in advance. That is, the moving image data for realizing the moving image display of the character image and the still image data of the decorative design are created separately and stored in the ROM. Then, the drawing processor 109 synthesizes the moving image data and the still image data when executing the super reach effect. Therefore, the capacity of moving image data can be reduced, and the capacity of a ROM for storing moving image data can be reduced.

  In this embodiment, the super reach effect is an effect in which an effect due to medium speed rotation, an effect due to high speed rotation, and an effect due to moving images are sequentially executed. Therefore, the contents of the effects of other reach effects (normal reach, reach A, etc.) are developed. In such a case, the appearance of the moving image display makes it possible for the player to have a great expectation for the big hit, and the interest of the game can be improved.

  FIG. 28 is an explanatory diagram showing an example of the effect aspect of reach production used in the normal state in this embodiment. As shown in FIG. 28, the reach effects used in the normal state include five types of reach effects of normal reach, reach A, reach B, reach C, and super reach. Normal reach rotates the special symbol (medium symbol) that stops last while maintaining the reach after the display status of the special symbol has reached the reach mode (the left and right symbols are aligned in the same pattern) at medium speed. ). That is, the normal reach is a normal reach effect that is not a special effect that raises the player's expectation for the big hit. Reach A and Reach B are developments of normal reach, and the special symbol (medium symbol) that stops last while maintaining the reach mode is rotated at medium speed, and the special symbol is rotated at high speed when a predetermined period has elapsed. Or it is an effect of reverse rotation. Reach B is an effect including a so-called return effect (an effect by a display in which the symbol rotates backward after the symbol stop position and the symbol returns to the stop position).

  Reach C and Super Reach are an extension of Reach A. The special symbol (medium symbol) that stops last while maintaining the reach mode is rotated at medium speed, and the special symbol is rotated at high speed, and then frame advance or This is an effect in which a moving image effect is executed.

  In this embodiment, the jackpot occurrence probability for the appearance of the reach effect increases in the order of normal reach, reach A, reach B, reach C, and super reach. Specifically, for example, when super reach appears, the probability of winning a big hit is configured to be higher than when other reach effects appear (see FIG. 11).

  FIG. 29 is an explanatory diagram showing an example of a customer waiting demonstration effect. In FIG. 29, (1) to (n) respectively show images of the respective frames constituting the moving image effect. Also, the rectangles in FIGS. 29 (1) to 29 (n) indicate the display screen of the image display device 9. In the example shown in FIG. 29, the last stop-displayed decorative symbol is displayed as it is on the variable display unit as it is, but a moving image is displayed in an area other than the variable display unit on the display screen.

  FIG. 30 is an explanatory diagram showing an example of a method of using the SDRAM 84. As shown in FIG. 30, two areas (areas 0 and 1) corresponding to the screen of the image display device 9 are secured in the SDRAM 84. Areas 0 and 1 are called a virtual area or frame memory 84A. In the areas 0 and 1 in the frame memory 84A, as appropriate (for example, when image data is required), a part image such as a character image is transferred from the CGROM 83 to the image data via an area other than the frame memory 84A in the SDRAM 84. Is expanded. When image data exists in an area other than the frame memory 84A in the SDRAM 84, the image data is expanded from the area to the areas 0 and 1. When the component image is developed in the area 0, an image signal based on the image data of the area 1 is output to the image display device 9, and when the component image is expanded in the area 1, the image based on the image data of the area 0 is output. A signal is output to the image display device 9. When the component image is expanded in the area 0, the area 0 is a drawing area, and when the component image is expanded in the area 1, the area 1 is the drawing area. Further, when image data is read from the area 0 and an image signal based on the image data is output to the image display device 9, the area 0 is a display area, the image data is read from the area 1, and the image When an image signal based on the data is output to the image display device 9, area 1 is the display area. Thus, the areas 0 and 1 are used as a double buffer.

  In an area other than the areas 0 and 1 in the SDRAM 84, a buffer area for a part image (a transfer destination area from the CGROM) is secured. The transfer destination area from the CGROM stores a part image (specifically, source data of the part image) that is highly likely to be used at that time, that is, highly likely to be drawn in the drawing area of the frame memory 84A. Is done. It is also used as a temporary storage area for image data expanded from the CGROM to the frame memory 84A. Hereinafter, an area other than the frame memory 84A in the SDRAM 84 is referred to as a VRAM 84B.

  In this embodiment, the SDRAM 84 used as the frame memory 84A and the VRAM 84B is provided outside the drawing processor 109, but the drawing processor 109 incorporating the frame memory 84A and the VRAM 84B may be used.

  FIG. 31 is an explanatory diagram showing an example of an address map of the frame memory 84A. FIG. 31 illustrates a region 0. In the frame memory 84A, the portion corresponding to the upper left of the display screen of the image display device 9 is assigned to the smallest address, the next address is assigned to the portion corresponding to the right on the display screen, and the portion of the row on the display screen is assigned. The address next to the address of the part corresponding to the right is assigned to the part corresponding to the leftmost of the next line. In the same manner, the address next to the address corresponding to the rightmost part of a certain row is assigned to the part corresponding to the leftmost position of the next line. The address value shown in FIG. 31 is an example.

  FIG. 32 is an explanatory diagram for explaining a method of developing image data from the CGROM 83 to the frame memory 84A. As shown in FIG. 32A, the image data may be transferred from the fixed area of the VRAM 84B to the frame memory 84A. The fixed area is an area in which the image data of the component image is constantly stored. For example, decorative pattern image data is stored in the fixed area. The image data is transferred from the fixed area to the frame memory 84A by the drawing processor 109. The drawing processor 109 reads the image data from the fixed area one word at a time and reads the read image data into the frame memory 84A. Instead of writing, image data is transferred by DMA (Direct Memory Access) transfer. That is, the drawing processor 109 includes a built-in DMA circuit having a DMA transfer function. In the DMA transfer, the read address is output to the VRAM bus, the read signal is output, the write address is output to the VRAM bus, and the write signal is output while the read address and the write address are incremented by one. This is the transfer method.

  In this embodiment, DMA transfer is used as an example. However, the drawing processor 109 may read image data word by word from the fixed area and write the read image data to the frame memory 84A. . In this case, the read image data is temporarily stored, for example, in a register of the drawing processor 109, and written from the register to the frame memory 84A.

  Further, as shown in FIG. 32B, image data is read from the CGROM 83, the read image data is stored in the temporary storage area in the VRAM 84B, and transferred from the temporary storage area to the frame memory 84A. is there. Such image data transfer is also executed by the drawing processor 109. The drawing processor 109 writes the image data read from the CGROM 83 and stored in the temporary storage area into the frame memory 84A by DMA transfer.

  As described above, the image data of the component image is constantly stored in the fixed area. As shown in FIG. 32C, the image data stored in the fixed area is referred to as advance transfer data. Therefore, the image data of the component image other than the pre-transfer data is temporarily stored in the temporary storage area.

  FIG. 33 is an explanatory diagram showing a data bus in the CG bus between the drawing control unit 91 and the CGROM 83 in the drawing processor 109. In FIG. 33, the CG bus I / F 93 (see FIG. 4) is not shown. As shown in FIG. 33, the data bus physically has 64 bits, but a 64-bit mode in which all 64 bits are used as a data bus, and a 32-bit mode in which lower 32 bits are used as a data bus. Can be switched to.

  In this embodiment, when the image data is read from the ROM 83C in which the moving image data is stored, the image data is read from the ROMs 83A and 83B in which the 32-bit mode is set and the still image (sprite image) data is stored. When reading, the 64-bit mode is set. Therefore, the image data of the sprite image is read from the CGROM 83 in 64-bit units, and the moving image data is read from the CGROM 83 in 32-bit units. In FIG. 33, for convenience of drawing, the ROM 83C is described as having a data bus extending from the ROM 83A. However, in reality, the data bus between the drawing control unit 91 and the ROM 83A branches to the ROM 83C. Wired.

  FIG. 34 is an explanatory diagram for explaining an example of each register in the drawing control register 95. In the example shown in FIG. 34, a CGROM start address register for designating the start address of the CGROM 83 when reading image data, image data when storing image data in the temporary storage area of the VRAM 84B, or image data from the temporary storage area of the VRAM 84B. VRAM head address register for designating the top address when reading data, VRAM transfer data size register for designating the size of transfer data when transferring image data to VRAM 84B, and data transfer from CGROM 83 to a fixed area of VRAM 84B There is a VRAM fixed area transfer execution instruction register for instructing data transfer, and a VRAM automatic transfer execution instruction register for instructing data transfer from the CGROM 83 to the fixed area of the VRAM 84B via the temporary storage area of the VRAM 84B.

  Further, a frame memory head address register for designating a head address when image data is expanded in the frame memory 84A, a frame memory transfer data size register for designating the size of transfer data, and a temporary storage area from the CGROM 83 to the VRAM 84B. There is a frame memory transfer execution instruction register for instructing data transfer to the frame memory 84A.

  Further, a fixed area start address register for specifying the start address of the fixed area of the VRAM 84B, a fixed area end address register for specifying the final address of the fixed area of the VRAM 84B, and a fixed area for specifying an arbitrary address of the fixed area of the VRAM 84B There is an arbitrary head address register, a fixed area data transfer execution instruction register for instructing data transfer from the fixed area of the VRAM 84B to the frame memory 84A.

  In addition, a data bus mode register for instructing whether the data bus mode is set to the 32-bit mode or the 64-bit mode, the moving image data in the CGROM 83 is read and temporarily stored in the temporary storage area, and the moving image data is stored in the temporary storage area. There is a decoding execution instruction register for decoding and instructing data transfer to the frame memory 84A, and a display area register indicating the current display area.

  The values set in the VRAM fixed area transfer execution instruction register, VRAM automatic transfer execution instruction register, frame memory transfer execution instruction register, fixed area data transfer execution instruction register, and decoding execution instruction register may each be 1 bit. The values set in these registers are set to predetermined bits in each register, for example.

  Also, the configuration of the drawing control register 95 as shown in FIG. 34 is an example, and the registers constituting the drawing control register 95 may be configured to be different from the configuration shown in FIG. For example, the register classification method for designating the head address may be different from the example shown in FIG.

  FIG. 35 is an explanatory diagram for explaining decorative pattern image data stored in the CGROM 83. As shown in FIG. 35A, the decorative pattern and graphic image data of “7” are stored in the selected image data area in the CGROM 83. The decorative pattern indicating the number “7” combined with the circular figure is used in the production mode # 1. In addition, the decorative pattern indicating the number “7” combined with the approximately rhombus graphic is used in the production mode # 2. The decorative design indicating the number “7” combined with the star-shaped hexagonal figure is used in the production mode # 3. A decorative design corresponding to the image data stored in the selected image data area is the selection identification information.

  In addition, image data of other decorative designs is stored in a common image data area in the CGROM 83 as shown in FIG. Each image data stored in the common image data area is transferred from the CGROM 83 to the fixed area of the VRAM 84B at a predetermined time. Each image data stored in the selected image data area is transferred from the CGROM 83 to the temporary storage area of the VRAM 84B when the effect mode is switched or from the CGROM 83 to the temporary storage area of the VRAM 84B. Transferred to fixed area. A decorative design corresponding to the image data stored in the common image data area is the common identification information.

  In this embodiment, the image data of the decorative design stored in the common image data area is preliminarily transferred to the fixed area of the VRAM 84B as the pretransfer data. The image data is not limited to decorative design image data. For example, it may be image data (moving image data) of a moving image constituting a background symbol.

  FIG. 36 is an explanatory diagram showing the data structure of moving image data among the image data of component images stored in the CGROM 83. The moving image data has a configuration in which a file header is set at the first address, and then a frame header and compressed data of each frame are sequentially set. In the stream, frame headers and compressed data of frames 1 to N (frame images 1 to n) are set in order from image 1. The moving image data is encoded by, for example, MPEG2 (Moving Picture Experts Group phase 2) encoding method. Since the amount of image data before encoding is reduced by encoding, the encoded image data is referred to as compressed data.

  FIG. 36 illustrates two pieces of moving image data (super-reach moving image data and customer waiting demonstration moving image data), but more moving image data may be stored in the CGROM 83. .

  The compressed data is stored in the CGROM 83 in a ROM having 32 bits as one word. When the drawing processor 109 reads compressed data from the CGROM 83, the bus width of the CG bus is set to 32 bits. Therefore, the drawing processor 109 reads compressed data from the CGROM 83 in units of 32 bits.

  Next, a method of decoding moving image data (compressed data) compressed by the moving image decompression unit 89 will be described with reference to the explanatory diagram of FIG. The frame numbers shown in FIG. 37A are the frame serial numbers in the moving image data shown in FIG. 36 (frames 1 to N). In the moving image data, the compressed data of frames 1 to N are configured by I picture, B picture, or P picture defined by the MPEG2 encoding method in the order shown in FIG. For example, frame 1 is an I picture, frames 2, 3, 5, and 6 are B pictures, and frames 4 and 7 are P pictures. The subscripts attached to I, B, and P are serial numbers for each picture type.

  As described above, frames 1 to N (frame images 1 to n) are stored as moving image data in order from frame 1 (image 1) (see FIG. 36). For example, frame 1 (image 1) in the stream is an I picture, frames 2, 3, 5, 6 (images 2, 3, 5, 6) are B pictures, and frames 4, 7 (images 4, 7). Is a P picture.

  Next, the operation of the effect control means will be described. FIG. 38 is a flowchart showing a main process executed by the effect control microcomputer 100 (specifically, the effect control CPU 101) mounted on the effect control board 80. The effect control CPU 101 starts executing the main process when the power is turned on. In the main processing, first, initialization processing is performed for clearing the RAM area, setting various initial values, and initializing a timer for determining the activation control activation interval (for example, 33 ms) (step S701). . Next, initial data transfer processing is performed (step S702). The initial data transfer process is a process for setting a fixed area in the VRAM 84B and transferring the image data (see FIG. 35B) stored in the common image data area of the CGROM 83 to the fixed area of the VRAM 84B. . Next, effect mode # 1 data transfer control processing is performed (step S703). In the effect mode # 1 data transfer control process, the image data of the decorative pattern indicating the number “7” combined with the circular figure stored in the selected image data area (see the upper part of FIG. 35A) is stored in the VRAM 84B. It is a process for transferring to. In this embodiment, even when the game control microcomputer 560 executes the game state recovery process, the effect control microcomputer 100 executes the processes of steps S702 and S703, so that it is combined with the circular figure. The decorative design image data indicating the number “7” is transferred to the VRAM 84B, but the production control microcomputer 100 recovers the power failure when the game control microcomputer 560 executes the game state recovery process. When it is configured to transmit a designated command and an effect control command (for example, a display result specifying command) indicating the restored gaming state, the step is performed when the effect control command indicating the restored gaming state is received. While executing the processing of S702, the received display result specifying command Next, effect mode # 1 data transfer control process, effect mode # 3 data transfer control process or effect mode # 3 data transfer control process is executed, and the number “7” combined with the figure that matches the gaming state It is preferable to control so that the image data of the decorative pattern shown is transferred to the VRAM 84B. In addition, when the production control microcomputer 100 starts to supply power to the gaming machine and the production control microcomputer 100 starts up (becomes an operable state), a moving image that constitutes a background pattern that is frequently used. The drawing processor 109 may be instructed to transfer image data of an image (for example, a customer waiting demonstration screen using a moving image) from the CGROM 83 to a fixed area of the VRAM 84B in advance.

  Thereafter, the effect control CPU 101 proceeds to a loop process for monitoring a timer interrupt flag (step S704). When a timer interrupt occurs, the effect control CPU 101 sets a timer interrupt flag in the timer interrupt process. If the timer interrupt flag is set in the main process, the effect control CPU 101 clears the flag (step S705) and executes the effect control process.

  In the effect control process, the effect control CPU 101 first analyzes the received effect control command and executes a process of setting a flag according to the received effect control command (command analysis process: step S706). Next, the effect control CPU 101 executes effect control process processing (step S707). In the effect control process, a process corresponding to the current control state (effect control process flag) is selected from the processes corresponding to the control state, and display control of the image display device 9 is executed. Further, a random number update process for updating a counter value of a counter for generating a predetermined random number is executed (step S708). Furthermore, when a customer waiting demonstration designation command is received from the game control microcomputer 560, a customer waiting demonstration control process for starting a customer waiting demonstration effect on the image display device 9 and a performance component (direction device) such as a lamp and a speaker 27 is performed. Execute (Step S709). Thereafter, the process proceeds to step S704.

  FIG. 39 is a flowchart showing the effect control process (step S707) in the main process shown in FIG. In the effect control process, the effect control CPU 101 performs any one of steps S800 to S807 according to the value of the effect control process flag. In each process, the following process is executed.

  Fluctuation pattern command reception waiting process (step S800): It is confirmed whether or not a variation pattern command is received from the game control microcomputer 560. Specifically, it is confirmed whether or not a variation pattern command reception flag set in the command analysis process is set. If the variation pattern command has been received, the value of the effect control process flag is changed to a value corresponding to the notice selection process (step S801).

  Prior notice selection process (step S801): When the effect display device 9 decides whether or not to execute the notice effect process for notifying the player of the occurrence of the big hit, and decides to execute the notice effect process Determines the notice type. Then, the value of the effect control process flag is changed to a value corresponding to the decorative symbol variation start process (step S802).

  Decoration symbol variation start processing (step S802): Control is performed so that the variation of the ornament symbol is started. Then, the value of the effect control process flag is updated to a value corresponding to the decorative symbol changing process (step S803).

  Decoration symbol variation processing (step S803): Controls the switching timing of each variation state (variation speed) constituting the variation pattern and monitors the end of the variation time. When the variation time ends, the value of the effect control process flag is updated to a value corresponding to the decorative symbol variation stop process (step S804).

  Decoration symbol variation stop processing (step S804): Based on the reception of the effect control command (design determination designation command) for instructing all symbols to stop, the variation of the ornament symbol is stopped and the display result (stop symbol) is derived and displayed. Take control. Then, the value of the effect control process flag is updated to a value corresponding to the jackpot display process (step S805) or the variation pattern command reception waiting process (step S800).

  Big hit display process (step S805): After the end of the variation time, control is performed to display a screen for notifying the image display device 9 of the occurrence of the big hit. Then, the value of the effect control process flag is updated to a value corresponding to the big hit game processing (step S806).

  Big hit game processing (step S806): Control during the big hit game is performed. For example, when an effect control command for display before opening the big winning opening or display when opening the big winning opening is received, display control of the number of rounds in the image display device 9 is performed. Then, the value of the effect control process flag is updated to a value corresponding to the big hit end process (step S807).

  Big hit end processing (step S807): In the image display device 9, display control is performed to notify the player that the big hit gaming state has ended. Then, the value of the effect control process flag is updated to a value corresponding to the variation pattern command reception waiting process (step S800).

  FIG. 40 is a flowchart showing a variation pattern command reception waiting process (step S800) in the effect control process shown in FIG. In the variation pattern command reception waiting process, the effect control CPU 101 confirms whether or not the variation pattern command reception flag is set (step S811). If the variation pattern command reception flag is set, the variation pattern command reception flag is reset (step S812). The variation pattern command reception flag is set in the command analysis process when a variation pattern command is received. In the command analysis process, the received fluctuation pattern command or data indicating the received fluctuation pattern command is stored in the fluctuation pattern command storage area of the RAM. Then, the value of the effect control process flag is updated to a value corresponding to the notice selection process (step S801) (step S813).

  FIG. 41 is a flowchart showing a decorative symbol variation start process (step S802) in the effect control process shown in FIG. In the decorative symbol variation start process, the effect control CPU 101 reads the variation pattern command or data indicating the received variation pattern command from the variation pattern command storage area (step S840).

  Next, the display result (stop symbol) of the decorative symbol is determined according to the data stored in the display result specifying command storage area of the RAM (that is, the received display result specifying command) (step S841). The effect control CPU 101 stores data indicating the display result of the determined decorative symbol in the decorative symbol display result storage area. The display result specifying command storage area stores the display result specifying command received in the command analysis process.

  In step S841, the effect control CPU 101 extracts a predetermined random number and determines a stop symbol based on the extracted random number. At this time, when a display result specifying command (display result 1 designation command, display result 2 designation command, display result 3 designation command) indicating a deviation is received, a combination of stop symbols (for example, reminiscent of a deviation) (for example, , The left middle right symbol does not match, or the left and right symbols do not match the middle symbol). When the variation pattern command with reach effect or the data indicating the received variation pattern command is stored in the variation pattern command storage area, the combination of the stop symbol that matches the left and right symbols but not the middle symbol is determined. When the variation pattern command not having the reach effect or the data indicating the received variation pattern command is stored in the variation pattern command storage area, the combination of the stop symbols in which the left middle right symbol does not match is determined. In addition, when a display result specifying command (display result 4 designation command, display result 5 designation command) indicating a big hit is received, a combination of stop symbols reminiscent of a big hit (for example, left middle right design matches) ). When a display result specifying command (display result 5 designation command) indicating a probability variation big hit is received, a combination of stop symbols that recalls a probability variation big hit (for example, “7” “7” “7”) May be determined. Note that a combination of decorative symbols that evokes a big hit is sometimes referred to as a big winning symbol, and a combination of decorative symbols that evokes a loss is sometimes referred to as a lost symbol.

  Then, the production control CPU 101 selects a process table corresponding to the variation pattern (step S842). Then, a process timer corresponding to the production execution data 1 in the selected process data is started (step S843). Next, the effect control CPU 101 performs the effect device (the effect display device 9 as the effect component, the effect component as the effect component according to the contents of the process data 1 (display control execution data 1, lamp control execution data 1, sound number data 1). Control of the various lamps and the speaker 27 as a production component is executed (step S844). For example, in order to display an image according to the variation pattern on the effect display device 9, a command is output to the drawing processor 109. In addition, a control signal (lamp control execution data) is output to the lamp driver board 35 in order to perform on / off control of various lamps. In addition, a control signal (sound number data) is output to the sound output board 70 in order to output sound from the speaker 27.

  If the variation pattern is accompanied by a super reach effect, the process table corresponding to the variation pattern includes process data indicating transfer of moving image data. Specifically, the process data display control execution data corresponding to the start time of the “moving image effect” shown in FIG. 28 includes data as exemplified in FIG. Further, in this embodiment, the variation pattern command is an effect control command that designates only the variation pattern, but the variation pattern command that designates the display result together with the variation pattern as a display result reminiscent of a big hit; A variation pattern command for designating that the display result together with the variation pattern is not a display result reminiscent of a big hit may be used.

  In this embodiment, the effect control CPU 101 performs control so that the decorative pattern is variably displayed by the change pattern corresponding to the change pattern command on a one-to-one basis. The variation pattern to be used may be selected from a plurality of types of variation patterns corresponding to.

  Then, the value corresponding to the variation time specified by the variation pattern command is set in the variation time timer (step S845), the process data valid flag is set (step S846), and the value of the effect control process flag is changed to the decorative pattern variation. A value corresponding to the intermediate process (step S803) is set (step S847). In this embodiment, the effect control CPU 101 appropriately outputs a command to the drawing processor 109 on condition that a process data valid flag is set in a V blank interrupt process described later. However, if data that needs to be output to the drawing processor 109 has been set in step S844, the command is output to the drawing processor 109 according to the data.

  FIG. 42A is an explanatory diagram illustrating a configuration example of a process table. The process table is a table in which process data referred to when the effect control CPU 101 executes control of the effect device is set. That is, the effect control CPU 101 controls effect devices (effect components) such as the image display device 9 in accordance with data set in the process table. The process table includes data in which a plurality of combinations of process timer set values, display control execution data, lamp control execution data, and sound number data are collected. The display control execution data includes data indicating each variation mode constituting the variation mode during the variable display time (variation time) of the variable display of the decorative symbols. Specifically, data relating to the change of the display screen of the image display device 9 is described. The process timer set value is set with a change time in the form of the change. In the V blank interrupt process, the effect control CPU 101 refers to the process table, and performs control for displaying the decorative pattern in the variation mode set in the display control execution data for the time set in the process timer set value. Do.

  The process table shown in FIG. 42A is stored in the ROM of the effect control board 80. A process table is prepared for each variation pattern. Furthermore, different process tables are prepared according to the difference in the notice effect mode (notice type) when the notice effect is executed.

  42B and 42C are explanatory diagrams illustrating an example of display control execution data. FIG. 42B illustrates display control execution data related to a still image. The display control execution data related to a still image includes a frame memory head indicating the start address of an area in which image data of a component image is expanded in the frame memory 84A. Address, frame memory final address indicating the final address of the image data of the component image in the frame memory 84A, flag indicating that the image is a still image, component image specifying data specifying the component image (start address and data in the CGROM 83) Length etc.) is set. FIG. 42B illustrates display control execution data related to a moving image, and the display control execution data related to a moving image includes, for example, a frame indicating the start address of an area where the image data of the moving image is expanded in the frame memory 84A. The memory start address, the frame memory end address indicating the final address of the area where the image data of the moving image is expanded in the frame memory 84A, the flag indicating that it is a moving image, and movie data designation data (such as the start address and data length in the CGROM 83) It is set. Further, when combining a plurality of images, data specifying a plurality of images to be combined is also set in the display control execution data.

  FIG. 43 is a flowchart showing the decorative symbol variation process (step S803) in the effect control process. In the decorative symbol variation process, the effect control CPU 101 checks whether or not the variation time timer has timed out (step S851). (Step S853). If the variation time timer has timed out, the value of the effect control process flag is updated to a value corresponding to the decorative symbol variation stop process (step S804) (step S852).

  FIG. 43 shows an example in which the value of the effect control process flag is updated to a value corresponding to the decorative symbol variation stop process (step S804) when the variation time timer times out regardless of the reception of the symbol confirmation designation command. However, on the condition that the flag indicating that the symbol confirmation designation command has been received (set in the command analysis process when the symbol confirmation designation command is received) is set, It is preferable to update the value to a value corresponding to the decorative symbol variation stop process (step S804). That is, it is preferable to end the variation of the decorative symbol on the condition that the symbol confirmation designation command is received. When controlling in such a manner, the fluctuation pattern of the decorative pattern is changed from shaking fluctuation (each decorative pattern is changed up and down, left and right finely) until the symbol confirmation designation command is received after the fluctuation time timer times out. It is preferable to display in a recognizable manner that the variation time has elapsed but has not yet completely stopped, by changing the display mode to a mode) or by repeating the enlarged display and the reduced display of the decorative pattern. Even if the variation time timer has not timed out, the variation of the decorative symbol may be terminated when the symbol determination designation command is received. In the case of such control, for example, even when an incorrect variation pattern command is received by the production control microcomputer 100 and the decoration pattern is varied for a longer time than the original variation time, the regular variation period The change of the decorative pattern can be terminated when the time elapses.

  FIG. 44 is a flowchart showing the decorative symbol variation stopping process (step S804) in the effect control process. In the decorative symbol variation stopping process, the effect control CPU 101 performs control for deriving and displaying the stopped symbol in accordance with the data stored in the decorative symbol display result storage area (data indicating the left middle right stop symbol) (step S861). . Specifically, an address or the like where the stop symbol image data in the fixed area of the VRAM 84B is specified and a command to transfer the stop symbol image data to the frame memory 84A is output to the drawing processor 109. The drawing processor 109 transfers the image data of the stop symbol to the frame memory 84A according to the command. Then, the effect control CPU 101 confirms whether or not it is determined to be a big hit (step S862). Whether or not it is determined to be a big hit is confirmed, for example, by a display result specifying command stored in the display result specifying command storage area.

  If it is determined to be a big hit, the address pointer is set to 0 (step S863) and the fixed area data transfer control process is executed (step S864). The fixed area data transfer control process is a process for transferring the image data (see FIG. 35B) stored in the common image data area of the CGROM 83 to the fixed area of the VRAM 84B, and the initial data in step S702. This process is similar to the process executed in the transfer process. Although it is not essential to execute the fixed area data transfer control process at this stage, for example, by executing the fixed area data transfer control process when it is determined to be a big hit, for example (for example, When the data is garbled in the fixed area of the VRAM 84B due to noise or the like, the image data in the fixed area of the VRAM 84B can be returned to correct data. Thereafter, the value of the effect control process flag is updated to a value corresponding to the jackpot display process (step S805) (step S865).

  If it is decided not to win, if the display result 2 designation command (outgoing designation / time reduction designation) is received, the probability variation state flag is reset and the time reduction state flag is set (steps S871, S872). , S873). Then, an effect mode # 2 data transfer control process (process for effect mode # 2 corresponding to the process shown in FIG. 54) is performed (step S874). That is, since the game mode is determined to be in the short time state, the effect mode # 2 data transfer control process is executed. In this embodiment, the symbol shown in the middle of FIG. 35A is used as the decorative symbol “7” in the short-time state. In the effect mode # 2 data transfer control process, the decorative pattern image data (refer to the middle of FIG. 35A) indicating the number “7” combined with the approximately rhombus figure stored in the selected image data area is used. This is a process for transferring to the VRAM 84B.

  If the display result 3 designation command (outgoing designation / low probability designation) has been received, the time reduction state flag is reset (steps S875, S876). Then, effect mode # 1 data transfer control processing (processing shown in FIG. 54) is performed (step S877). That is, since the game mode is determined to be in the low probability state (normal state), the effect mode # 1 data transfer control process is executed. In this embodiment, in the normal state, the symbol shown in the upper part of FIG. 35A is used as the decorative symbol “7”. In the effect mode # 1 data transfer control process, the image data of the decorative pattern indicating the number “7” combined with the circular figure stored in the selected image data area (see the upper part of FIG. 35A) is stored in the VRAM 84B. It is a process for transferring to.

  Thereafter, the value of the effect control process flag is updated to a value corresponding to the variation pattern command reception waiting process (step S800) (step S878).

  FIG. 45 is a flowchart showing the jackpot display process (step S805) in the effect control process. In the jackpot display process, the effect control CPU 101 determines whether or not a fanfare flag indicating that a jackpot start designation command has been received (set when a jackpot start designation command is received in the command analysis process) is set. Confirmation is made (step S891). If the fanfare flag has been set, the fanfare flag is reset (step S892), and process data corresponding to the big hit gaming effect is selected (step S893). Then, the process timer corresponding to the production execution data 1 in the selected process data is started (step S894). Further, the rendering device is controlled according to the contents of the process data 1 (display control execution data 1, lamp control execution data 1, and sound number data 1) (step S895). Then, a process data valid flag is set (step S896). Thereafter, the value of the effect control process flag is updated to a value corresponding to the big hit game process (step S806) (step S897).

  FIG. 46 is a flowchart showing the big hit end process (step S807) in the effect control process. In the jackpot end process, the effect control CPU 101 sets a jackpot end designation command reception flag (set when a jackpot end designation command is received in the command analysis process) indicating that the jackpot end designation command has been received. It is confirmed whether or not (step S881). When the big hit end designation command reception flag is set, the big hit end designation command reception flag is reset (step S882), and the image display device 9 is controlled to display the big hit end screen (step S888). Specifically, an address or the like where the image data of the big hit end screen is stored in the CGROM 83 and a command to transfer the big hit end screen image data to the frame memory 84A is output to the drawing processor 109. The drawing processor 109 reads the image data of the big hit end screen from the CGROM 83 according to the command, and transfers the read image data to the frame memory 84A via the temporary storage area of the VRAM 84B.

  When the display result 5 designation command (probability change jackpot designation) has been received, the probability change state flag is set. When the time reduction state is set, that is, when the time reduction state flag is set, the time reduction state is set. The flag is reset (steps S884, S885, S886). Then, an effect mode # 3 data transfer control process (a process for effect mode # 3 corresponding to the process shown in FIG. 54) is performed (step S887). That is, since the game mode is determined to be in a probable change state, the effect mode # 3 data transfer control process is executed. In this embodiment, in the probability variation state, the symbol shown in the lower part of FIG. 35A is used as the decorative symbol “7”. In the effect mode # 3 data transfer control process, the decorative pattern image data indicating the number “7” combined with the star-shaped hexagon figure stored in the selected image data area (see the lower part of FIG. 35A) ) Is transferred to the VRAM 84B.

  Thereafter, the value of the effect control process flag is updated to a value corresponding to the variation pattern command reception waiting process (step S800) (step S888).

  FIG. 47 is a flowchart showing the V blank interrupt process executed by the effect control CPU 101 in response to the V blank interrupt from the drawing processor 109. The V blank interrupt is an interrupt generated by the drawing processor 109 in the same cycle as the cycle of the vertical synchronization signal supplied to the image display device 9. For example, when the screen change frequency (frame frequency) of the image display device 9 is 30 Hz, the generation period of the V blank interrupt is 33.3 ms, and when the frame frequency is 60 Hz, the occurrence of the V blank interrupt is generated. The period is 16.7 ms.

  In this embodiment, the production control CPU 101 outputs a command to the drawing processor 109 in the V blank interrupt process, but the process shown in FIG. 47 may be executed in another process.

  In the V blank interruption process, the effect control CPU 101 refers to the data in the display area register (see FIG. 34) to check whether the current display area is the area 0 or the area 1 (step S901). If the current display area is area 0, data indicating area 1 is set in the display area register to set the display area to area 1 (step S902). If the current display area is area 1, data indicating area 0 is set in the display area register to set the display area to area 0 (step S903).

  Next, when the process data valid flag (flag indicating that the effect control based on the process data is being performed) is set (step S904), the effect control CPU 101 decrements the process timer value by -1 ( Step S905). When the value of the process timer becomes 0 (step S906), the process data pointer is incremented by 4 (step S907). Therefore, the process data pointer points to the next process timer set value (see FIG. 42A). The effect control CPU 101 loads the contents of the display control execution data set in the area next to the area pointed to by the process data pointer (area where the process timer set value is set) (step S908). Note that data indicating specific display control contents may be set in the display control execution data area, but an address of a ROM area where data indicating specific display control contents is set is set. It may be.

  When data indicating drawing of a component image, that is, development to the frame memory 84A is set as display control execution data (step S909), a drawing control process is executed (step S910). For example, when a variable display of a decorative symbol is executed such that one decorative symbol moves up and down one frame at a time every 0.1 second (100 ms), the process timer is set to respond out in 100 ms. It is set. If the decorative pattern “5” is displayed before the process timer times out, the decorative pattern “6” is expanded in the frame memory 84A as the display control execution data used when the time-out occurs. Is set. In this case, the effect control CPU 101 determines that drawing of a component image is necessary.

  Then, the process timer set value pointed to by the process data pointer is set in the process timer (step S911). That is, the process timer is started.

  In this embodiment, the frame memory 84A has a double buffer configuration of the areas 0 and 1. However, the frame memory 84A may be configured by a single area. In that case, the drawing processor 109 writes the image data in a single area. The display signal control unit 87 creates an image signal based on the image data developed in the frame memory 84A, and outputs the image signal to the image display device 9. The frame memory 84A is composed of a single area. In the drawing processor 109, the display signal control unit 87 finishes the writing process of the image data to the frame memory 84A so that the writing and reading of the image data to the frame memory 84A do not compete with each other. Then, read processing is executed.

  Next, the operation when the production control CPU 101 outputs a command and the operation of the drawing processor 109 (specifically, the drawing control unit 91 in the drawing processor 109) according to the command will be described. In this embodiment, the instruction output from the rendering control CPU 101 to the drawing processor 109 is performed by setting predetermined data in a predetermined register in the drawing control register 95 of the drawing processor 109.

  FIG. 48 is an explanatory diagram showing an example of a data table stored in the ROM 112. FIG. 48 illustrates a data table used when image data stored in the selected image data area and the common image data area of the CGROM 83 shown in FIG. 35 is transferred to the VRAM 84B.

  The fixed area data table is a data table used when image data stored in the common image data area shown in FIG. 35B is transferred to the VRAM 84B. The effect mode # 1 data table is a data table used when the image data shown in the upper part of FIG. 35A is transferred to the VRAM 84B. The effect mode # 2 data table is a data table used when the image data shown in the middle of FIG. 35A is transferred to the VRAM 84B. The effect mode # 3 data table is a data table used when transferring the image data shown in the lower part of FIG. 35A to the VRAM 84B.

  FIG. 49 is a flowchart showing the initial data transfer process shown in FIG. In the initial data transfer process, the production control CPU 101 sets the start address of the area used as the fixed area in the fixed area start address register (see FIG. 34) in order to secure the fixed area in the VRAM 84B (step S921). . Further, the final address of the area used as the fixed area is set in the fixed area final address register (see FIG. 34) (step S922).

  Next, with reference to the fixed area data table, a command for transferring the image data stored in the selected image data area and the common image data area of the CGROM 83 to the VRAM 84B is given to the drawing processor 109. That is, the production control CPU 101 sets the head address of the fixed area data table in the ROM 112, for example, in an internal register (step S923), and sets 0 in the address pointer (step S924). Then, the fixed area data transfer control process is executed (step S925).

  FIG. 50 is a flowchart showing fixed area data transfer control processing. In the fixed area data transfer control process, the effect control CPU 101 reads data at the address pointed to by the address pointer in the fixed area data table (data storage start address (transfer source start address) in the CGROM 83) (step S931). Since the head address of the fixed area data table in the ROM 112 is not 0000, when reading data from the fixed area data table, the head address of the fixed area data table is added as an offset value to the value of the address pointer. The effect control CPU 101 sets the data read from the fixed area data table in the CGROM head address register (see FIG. 34) (step S932). Then, the value of the address pointer is incremented by 1 (step S933).

  Next, data at the address pointed to by the address pointer in the fixed area data table (stored storage start address (transfer destination start address) of the VRAM 84B) is read (step S934), and the read data is read into the VRAM start address register (see FIG. 34). Setting is made (step S935). Then, the value of the address pointer is incremented by 1 (step S936).

  Next, the data (data length) at the address pointed to by the address pointer in the fixed area data table is read (step S937), and the read data is set in the VRAM transfer data size register (see FIG. 34) (step S938). Then, the corresponding bit of the VRAM fixed area transfer execution instruction register is set (step S939).

  As described above, a command for transferring the image data stored in the common image data area of the CGROM 83 to the VRAM 84B is given to the drawing processor 109 from the effect control CPU 101 to the drawing processor 109. .

  51 shows a process in which the drawing processor 109 (specifically, the drawing control unit 91 in the drawing processor 109) transfers image data from the CGROM 83 to the fixed area of the VRAM 84B in response to a command from the CPU 101 for effect control. It is a flowchart. When the corresponding bit of the VRAM fixed area transfer execution instruction register is set (step S1001), the effect control CPU 101 uses the read source counter (for example, the drawing processor 109) as the transfer source start address set in the CGROM start address register. General-purpose registers and built-in RAM are used) (step S1002). Further, the transfer destination head address set in the VRAM head address register is set in a write address counter (for example, a general-purpose register or a built-in RAM in the drawing processor 109 is used) (step S1003). Further, the data length (transfer data amount) set in the VRAM transfer data size register is set in a transfer data amount storage area (for example, a general-purpose register or built-in RAM in the drawing processor 109 is used) (step). S1004).

  Then, the data transfer process is executed (step S1005). When the data transfer process is completed, the corresponding bit of the VRAM fixed area transfer execution instruction register is reset (step S1006). The effect control CPU 101 can recognize that the transfer of the image data from the CGROM 83 to the fixed area of the VRAM 84B is completed by confirming that the corresponding bit of the VRAM fixed area transfer execution instruction register is reset if necessary. .

  FIG. 52 is a flowchart showing the data transfer process in step S1005. Note that the data transfer process as a subroutine shown in FIG. 52 is also executed in other processes described later.

  In the data transfer process, the drawing processor 109 sets 0 to a processing counter (for example, a general-purpose register or a built-in RAM in the drawing processor 109 is used) (step S1100). That is, the processing counter is initialized.

  Next, data is read from the address indicated by the read address counter (step S1101). In this case, image data is read from the CGROM 83. Then, the read data is written to the address indicated by the write address counter (step S1102). Next, the values of the read address counter, the write address counter, and the processing counter are each incremented by 1 (step S1105). If the value of the processing counter matches the value (transfer data amount) set in the transfer data amount storage area, all the image data has been written in the transfer destination area, and the process is terminated (step S1106). ). If they do not match, the process returns to step S1101.

  In this embodiment, image data of a decorative pattern that is frequently used is transferred in advance from the CGROM 83 to the fixed area of the VRAM 84B. When power supply to the gaming machine is started and the drawing processor 109 becomes operable, the contents of the drawing control register 95 are initialized, but the data bus mode register (see FIG. 34) in the drawing control register 95 is initialized. The value is “0”. Therefore, when the decorative design image data is transferred in advance to the fixed area of the VRAM 84B, the data bus mode register is set to “0”, and the data width of the CG bus is 64 bits. When image data of a moving image that constitutes a frequently used background symbol is transferred in advance from the CGROM 83 to the fixed area of the VRAM 84B, the rendering control CPU 101 performs drawing control to reduce the data width of the CG bus to 32 bits. “1” is set in the data bus mode register (see FIG. 34) in the register 95. Then, for example, the start address of the area where the image data of the moving image is stored is set in the CGROM start address register. Further, the start address of the fixed area of the VRAM 84B is set in the VRAM start address register. Then, the corresponding bit of the decoding execution instruction register is set. Then, the rendering processor 109 operates in the same manner as a moving image decoding process described later, and forwards the decoded moving image image data to the fixed area of the VRAM 84B. Thereafter, the CPU 101 for effect control sets “0” in the data bus mode register (see FIG. 34) in the drawing control register 95 in order to return the data width of the CG bus to 64 bits.

  FIG. 53 shows a modification of the process in which the drawing processor 109 (specifically, the drawing control unit 91 in the drawing processor 109) transfers image data from the CGROM 83 to the fixed area of the VRAM 84B in response to a command from the CPU 101 for effect control. It is a flowchart which shows an example. Here, the drawing processor 109 transfers the image data from the CGROM 83 to the fixed area via the temporary storage area of the VRAM 84B.

  When the corresponding bit of the VRAM fixed area transfer execution instruction register is set (step S1001), the effect control CPU 101 uses the read source counter (for example, the drawing processor 109) as the transfer source start address set in the CGROM start address register. General-purpose registers and built-in RAM are used) (step S1002). Further, the head address of the temporary storage area of the VRAM 84B is set in a write address counter (for example, a general-purpose register or built-in RAM in the drawing processor 109 is used) (step S1003A). Further, the data length (transfer data amount) set in the VRAM transfer data size register is set in a transfer data amount storage area (for example, a general-purpose register or built-in RAM in the drawing processor 109 is used) (step). S1004).

  Then, the data transfer process is executed (step S1005). When the data transfer process is completed, the start address of the transferred data, that is, the start address of the temporary storage area is set as the transfer source start address in the built-in DMA circuit ( In step S1007), the contents of the VRAM head address register are set as the transfer destination head address (step S1008). Further, the data length (transfer data amount) set in the VRAM transfer data size register is set in the built-in DMA circuit (step S1009A), and the built-in DMA circuit is activated (step S1009B).

  The built-in DMA circuit outputs the read address starting from the transfer source start address to the VRAM bus, the read signal output, the output of the write address starting from the transfer destination start address to the VRAM bus, and the write signal output to the read address and the write signal. The data transfer is performed continuously while adding 1 to the embedded address. When the data transfer for the set data length is completed, for example, an internal interrupt is generated. The drawing processor 109 recognizes that all data has been transferred to the selected image data setting area in the VRAM 84B due to the occurrence of the internal interrupt (step S10009C), and resets the corresponding bit in the VRAM fixed area transfer execution instruction register. (Step S1006).

  FIG. 54 is a flowchart showing effect mode # 1 data transfer control processing executed by the effect control CPU 101. The production mode # 1 data transfer control process is executed when the power supply to the gaming machine is started and the production control microcomputer 100 becomes operable (see FIG. 38). Also, it is executed when the effect mode is determined to be effect mode # 1 (see FIG. 38). Note that the execution time of the effect mode # 1 data transfer control process is not limited to when the power supply to the gaming machine is started, and first uses the selected image data of the effect mode # 1 (the upper part of FIG. 35A). It only has to be executed by the time. When the decorative symbol “7” is not used as the so-called initial appearance, the effect mode # 1 data transfer control process may be executed by the time when the decorative symbol variable display is first executed.

  In the effect mode # 1 data transfer control process, the effect control CPU 101 sets the start address of the effect mode # 1 data table (see FIG. 48) in the ROM 112 in, for example, an internal register (step S941), and sets the address pointer to 0. Set (step S942). Then, the data of the address pointed to by the address pointer in the effect mode # 1 data table (data storage head address (transfer source head address) in the CGROM 83) is read (step S943). Since the start address of the effect mode # 1 data table in the ROM 112 is not 0000, when the data is read from the effect mode # 1 data table, the start address of the effect mode # 1 data table is set to the offset value as the address pointer value. Add as The effect control CPU 101 sets the data read from the effect mode # 1 data table in the CGROM head address register (see FIG. 34) (step S944). Then, the value of the address pointer is incremented by 1 (step S945).

  Next, the data at the address pointed to by the address pointer in the effect mode # 1 data table (stored storage start address (transfer destination start address) of the VRAM 84B) is read (step S946), and the read data is stored in the VRAM start address register (see FIG. 34). ) (Step S947). Then, the address pointer value is incremented by 1 (step S948).

  Next, the data (data length) at the address indicated by the address pointer in the effect mode # 1 data table is read (step S949), and the read data is set in the VRAM transfer data size register (see FIG. 34) (step S950). . Then, the corresponding bit of the VRAM automatic transfer execution instruction register is set (step S951).

  As described above, a command for transferring the image data stored in the selected image data area of the CGROM 83 to the VRAM 84B is given to the drawing processor 109 from the effect control CPU 101 to the drawing processor 109. . Here, production mode # 1 data transfer control processing has been described, but production mode # 2 data transfer control processing and production mode # 3 data transfer control processing are configured in the same manner. However, in the effect mode # 2 data transfer control process, the data read target is the effect mode # 2 data table, and in the effect mode # 3 data transfer control process, the data read target is the effect mode # 3 data table.

  FIG. 55 illustrates a process in which the drawing processor 109 (specifically, the drawing control unit 91 in the drawing processor 109) transfers image data from the selected image data area of the CGROM 83 to the VRAM 84B in response to a command from the CPU 101 for effect control. It is a flowchart which shows. When the corresponding bit in the VRAM automatic transfer execution instruction register is set (step S1011), the effect control CPU 101 sets the transfer source head address set in the CGROM head address register in the read address counter (step S1012). . Further, the start address of the temporary storage area of the VRAM 84B is set in the write counter as the transfer destination start address (step S1013). Further, the data length (transfer data amount) set in the VRAM transfer data size register is set in the transfer data amount storage area (step S1014).

  Then, the data transfer process (see FIG. 52) is executed (step S1015). When the data transfer process is completed, the built-in DMA circuit sends to the built-in DMA circuit the start address of the transferred data, that is, the start of the temporary storage area. An address is set (step S1016), and the start address of the selected image data setting area (0000 (H) to 6FFF (H) in the example shown in FIG. 35B) in the VRAM 84B is set as the transfer destination start address. (Step S1017). The start address of the selected image data setting area in the VRAM 84B is the transfer destination start address set in the VRAM start address register by the process in step S947. Further, the data length (transfer data amount) set in the VRAM transfer data size register is set in the built-in DMA circuit (step S1018), and the built-in DMA circuit is activated (step S1019).

  The built-in DMA circuit outputs the read address starting from the transfer source start address to the VRAM bus, the read signal output, the output of the write address starting from the transfer destination start address to the VRAM bus, and the write signal output to the read address and the write signal. The data transfer is performed continuously while adding 1 to the embedded address. When the data transfer for the set data length is completed, for example, an internal interrupt is generated. The drawing processor 109 recognizes that all data has been transferred to the selected image data setting area in the VRAM 84B due to the occurrence of the internal interrupt (step S1020), and resets the corresponding bit in the VRAM automatic transfer execution instruction register. (Step S1021). If necessary, the effect control CPU 101 can recognize that the transfer of the image data from the CGROM 83 to the VRAM 84B is completed by confirming that the corresponding bit of the VRAM automatic transfer execution instruction register has been reset.

  In this embodiment, the selected image data is transferred to a fixed area in the VRAM 84B. However, the selected image data may be transferred to an area other than the fixed area in the VRAM 84B and stored in that area.

  FIG. 56 shows a process in which the drawing processor 109 (specifically, the drawing control unit 91 in the drawing processor 109) transfers image data from the selected image data area of the CGROM 83 to the VRAM 84B in response to a command from the effect control CPU 101. It is a flowchart which shows the modification of. In this example, the drawing processor 109 transfers the image data in the CGROM 83 directly from the CGROM 83 to the VRAM 84B without going through the temporary storage area.

  When the corresponding bit of the VRAM automatic transfer execution instruction register is set (step S1011), the drawing processor 109 sets the transfer source start address set in the CGROM start address register in the read address counter (step S1012). Also, the transfer destination head address set in the VRAM head address register (the head address of the selected image data setting area in the VRAM 84B) is set in the write address counter (step S1013A). Further, the data length (transfer data amount) set in the VRAM transfer data size register is set in the transfer data amount storage area (step S1004). Then, a data transfer process (see FIG. 52) is executed (step S1015).

  FIG. 57 is a flowchart showing the drawing control process in the V blank interrupt process (see FIG. 47). The effect control CPU 101 first specifies a component image to be updated (step S961). For example, when a variable display of a decorative symbol is executed such that one decorative symbol moves up and down one frame at a time every 0.1 second (100 ms), the process timer is set to respond out in 100 ms. It is set. If the decorative pattern “5” is displayed before the process timer times out, the decorative pattern “6” is expanded in the frame memory 84A as the display control execution data used when the time-out occurs. Is set. In that case, the CPU 101 for effect control determines that drawing of a component image is necessary in the process of step S909 in the V blank interrupt process. In step S961, the part image to be updated is identified as a decorative symbol “6”.

  Next, the effect control CPU 101 determines whether or not to switch to the moving image on the condition that the moving image mode flag is not set (step S962). Whether or not to switch to a moving image is determined based on the contents of process data set in the process table. That is, the determination is made based on whether or not a flag indicating a moving image is set in the display control execution data (see FIG. 42C). When it is determined that switching to a moving image should be performed, “1” is set in the data bus mode register (see FIG. 34) in the drawing control register 95 (step S963). Then, the moving image mode flag is set (step S964).

  Further, the effect control CPU 101 determines whether or not to switch to the still image on the condition that the moving image mode flag is set (step S965). Whether or not to switch to a still image is determined based on the contents of process data set in the process table. That is, it is determined by whether or not a flag indicating a still image is set in the display control execution data (see FIG. 42B). If it is determined that the still image should be switched, “0” is set in the data bus mode register (see FIG. 34) in the drawing control register 95 (step S966). Then, the moving image mode flag is reset (step S967).

  By the processing in step S963, the effect control CPU 101 instructs the bus width of the CG bus between the CGROM 83 and the rendering processor 109 to be 32 bits when moving image display is performed on the image display device 9. Become. In addition, when no moving image display is performed in the image display device 9, a command is given to set the bus width of the CG bus between the CGROM 83 and the drawing processor 109 to 64 bits.

  As described above, moving image data (compressed data) is stored in the CGROM 83 in a ROM capable of data input / output of 32 bits. Therefore, even if the bus width of the CG bus is 32 bits, the drawing processor 109 can read image data from the CGROM 83 without error.

  In this embodiment, the bus width of the CG bus is automatically set to 32 bits when “1” is set in the data bus mode register, and automatically when “0” is set in the data bus mode register. In particular, the rendering processor 109 is used to set the bus width of the CG bus to 64 bits. However, the drawing processor 109 (specifically, the drawing control unit 91) validates the upper 32 bits of the 64-bit data bus according to the value set in the data bus mode register (the bus width is set to 64 bits). A rendering processor 109 configured to perform control or invalidate control (set the bus width to 32 bits) may be used. When such a drawing processor 109 is used, when the value set in the data bus mode register changes, the drawing control unit 91 performs processing for setting the bus width of the CG bus according to the changed value. Do.

  In this embodiment, the rendering processor 109 sets the bus width to 32 bits and then returns the bus width to 64 bits when the still image data is read from the CGROM 83 next time, but reads the moving image data from the CGROM 83. When the processing is completed, the bus width may be returned to 64 bits.

  Next, the effect control CPU 101 determines whether or not there is a part image to be updated (step S971). The process in step S971 is a process that takes into account that there may be a plurality of component images to be updated. If there is a part image to be updated, it is determined whether or not the part image exists in the fixed area of the VRAM 84B (step S972). In this embodiment, each decorative design is a component image existing in a fixed area of the VRAM 84B.

  If the component image exists in the fixed area, the start address of the area where the image data of the component image in the fixed area exists is set in the fixed area arbitrary address register (see FIG. 34) (step S973). Also, the head address of the area where the image data of the component image is expanded in the frame memory 84A is set in the frame memory head address register (see FIG. 34) (step S974). Further, the transfer data amount (data length) of the image data to be transferred is set in the frame memory transfer data size register (see FIG. 34) (step S975). Then, the corresponding bit of the fixed area data transfer execution instruction register (see FIG. 34) is set (step S976).

  If the component image does not exist in the fixed area, the effect control CPU 101 determines whether or not the component image is a moving image (step S980). If it is not a moving image, the head address of the image data of the component image (still image) in the CGROM 83 is set in the CGROM head address register (see FIG. 34) (step S981). In addition, the head address of the area where the image data of the component image is expanded in the frame memory 84A is set in the frame memory head address register (step S982). Further, the transfer data amount (data length) of the transferred image data is set in the frame memory transfer data size register (step S983). Then, the corresponding bit of the frame memory data transfer execution instruction register (see FIG. 34) is set (step S984).

  If the component image is a moving image, the start address of the image data (movie data) of the component image (moving image) in the CGROM 83 is set in the CGROM start address register (step S985). Further, the head address of the area where the image data of the moving image is expanded in the frame memory 84A is set in the frame memory head address register (step S986). Further, the transfer data amount (data length) of the movie data is set in the frame memory transfer data size register (step S987). Then, the corresponding bit of the decoding execution instruction register (see FIG. 34) is set (step S988).

  58 shows a process in which the drawing processor 109 (specifically, the drawing control unit 91 in the drawing processor 109) transfers image data from the fixed area of the VRAM 84B to the frame memory 84A in response to a command from the CPU 101 for effect control. It is a flowchart which shows. The drawing processor 109 transfers the image data using the area 1 as the drawing area when the area 0 in the frame memory 84A is set as the display area, and sets the area 0 as the area 1 when the area 1 is set as the display area. Image data is transferred as a drawing area. In order to enable such control, for example, the effect control CPU 101 always instructs the address of the area 0 when instructing the address of the frame memory 84A. Then, when transferring the image data with the area 1 as the drawing area, the drawing processor 109 adds the difference between the address of the area 1 and the address of the area 0 to the commanded address to obtain the transfer destination address. To do.

  When the corresponding bit of the fixed area transfer execution instruction register is set (step S1025), the effect control CPU 101 sets the transfer source head address set in the arbitrary head address register in the fixed area in the process of step S973 as the read address counter. (Step S1026). Further, the transfer destination start address set in the frame memory start address register is set in the write counter as the transfer destination start address (step S1027). Further, the data length (transfer data amount) set in the frame memory transfer data size register is set in the transfer data amount storage area (step S1028).

  Then, the data transfer process (see FIG. 52) is executed (step S1029). When the data transfer process is completed, the corresponding bit in the fixed area transfer execution instruction register is reset (step S1030). The production control CPU 101 recognizes that the transfer of the image data from the fixed area of the VRAM 84B to the frame memory 84A is completed by confirming that the corresponding bit of the fixed area transfer execution instruction register has been reset, if necessary. it can.

  FIG. 59 is a flowchart showing processing in which the drawing processor 109 (specifically, the drawing control unit 91 in the drawing processor 109) transfers image data from the CGROM 83 to the frame memory 84A in response to a command from the CPU 101 for effect control. It is.

  When the corresponding bit of the frame memory transfer execution instruction register is set (step S1031), the drawing processor 109 sets the transfer source start address set in the CGROM start address register in the read address counter (step S1032). Further, the start address of the temporary storage area of the VRAM 84B is set in the write counter as the transfer destination start address (step S1033). Further, the data length (transfer data amount) set in the frame memory transfer data size register is set in the transfer data amount storage area (step S1034).

  Then, the data transfer process (see FIG. 52) is executed (step S1035). When the data transfer process is completed, the built-in DMA circuit sends the transferred data start address as the transfer source start address, that is, the start of the temporary storage area. The address is set (step S1036), the transfer destination start address set in the frame memory start address register is set as the transfer destination start address, and the data length (transfer data amount) set in the frame memory transfer data size register is set. ) Is set (step S1037), and the built-in DMA circuit is activated (step S1038).

  The built-in DMA circuit outputs the read address starting from the transfer source start address to the VRAM bus, the read signal output, the output of the write address starting from the transfer destination start address to the VRAM bus, and the write signal output to the read address and the write signal. The data transfer is performed continuously while adding 1 to the embedded address. When the data transfer for the set data length is completed, for example, an internal interrupt is generated. The drawing processor 109 recognizes that all data has been transferred to the frame memory 84A due to the occurrence of the internal interrupt (step S1039), and resets the corresponding bit of the frame memory transfer execution instruction register (step S1040). . If necessary, the effect control CPU 101 can recognize that the transfer of the image data from the CGROM 83 to the frame memory 84A has been completed by confirming that the corresponding bit of the frame memory transfer execution instruction register has been reset.

  When it is necessary to transfer the image data from the CGROM 83 to the frame memory 84A, the presentation control CPU 101 simply designates the start address in the CGROM 83 and the start address in the frame memory 84A with respect to the addresses (see steps S981 and S982). The drawing processor 109 reads the image data from the frame memory 84A, and expands the image data to the frame memory 84A via the temporary storage area of the VRAM 84B (see steps S1032 to S1039). Therefore, even if the drawing processor 109 that transfers image data from the frame memory 84A to the frame memory 84A via the temporary storage area is used, the effect control CPU 101 does not need to specify an address in the temporary storage area, and the frame is transferred from the CGROM 83. The control burden related to the transfer of image data to the memory 84A does not increase.

  60 and 61, the drawing processor 109 (specifically, the drawing control unit 91 in the drawing processor 109) transfers the image data of the moving image from the CGROM 83 to the frame memory 84A in response to a command from the effect control CPU 101. It is a flowchart which shows the moving image decoding process to transfer. In the moving image decoding process, when the corresponding bit of the decoding execution instruction register is set (step S1041), the effect control CPU 101 sets the transfer source head address set in the CGROM head address register in the read address counter. (Step S1042). Further, the start address of the temporary storage area of the VRAM 84B is set in the write counter as the transfer destination start address (step S1043). Further, the data length (transfer data amount) set in the frame memory transfer data size register is set in the transfer data amount storage area (step S1044).

  Then, a data transfer process (see FIG. 52) is executed (step S1045). When the data transfer process ends, the moving image decompression unit 89 in the rendering processor 109 transfers the moving image data (compressed data) transferred to the temporary storage area of the VRAM 84B. ) For example in units of 32 bits (step S1047).

  In this case, in the data transfer process, the image data is read from the CGROM 83 in units of 32 bits, and the image data is written in the temporary storage area in units of 32 bits. When the VRAM 84B is configured to have 64 bits as one word, when the image data is read twice from the CGROM 83 in units of 32 bits, the two image data are written in the temporary storage area.

  Next, the decoded image data is stored in another area in the temporary storage area. If the moving image data is an I picture, decoding can be performed using only the moving image data transferred to the temporary storage area in step S1045. However, if the moving image data is a B picture or a P picture, it cannot be decoded using only the moving image data transferred to the temporary storage area in the process of step S1045. It is also necessary to use image data of frames that are decoded thereafter. Therefore, the drawing processor 109 stores image data of previously decoded frames necessary for decoding the P picture in the temporary storage area of the VRAM 84B. Further, when decoding a B picture, the compressed data of the B picture is stored in the temporary storage area until the image data of the frame necessary for decoding the B picture is decoded, and is necessary for decoding the B picture. When the frame image data is decoded, the B picture image data is decoded.

  In this embodiment, the frame memory 84A and the VRAM 84B are provided outside the drawing processor 109. However, when the frame memory 84A and the VRAM 84B are built in the drawing processor 109, moving image data (compressed) Data) is transferred from the CGROM 83 to a temporary storage area in the built-in RAM of the drawing processor 109, and the compressed data transferred to the built-in RAM is decoded.

  Next, the rendering processor 109 sets, in the built-in DMA circuit, the start address of the temporary storage area where the decoded image data is stored as the transfer source start address (step S1048), and the frame memory as the transfer destination start address. The transfer destination head address set in the head address register is set, the data length (transfer data amount) of the decoded image data is set (step S1049), and the built-in DMA circuit is activated (step S1050).

  The built-in DMA circuit outputs the read address starting from the transfer source start address to the VRAM bus, the read signal output, the output of the write address starting from the transfer destination start address to the VRAM bus, and the write signal output to the read address and the write signal. The data transfer is performed continuously while adding 1 to the embedded address. When the data transfer for the set data length is completed, for example, an internal interrupt is generated. The drawing processor 109 recognizes that all data has been transferred to the frame memory 84A due to the occurrence of the internal interrupt (step S1051), and resets the corresponding bit in the decoding execution instruction register (step S1052). If necessary, the effect control CPU 101 can recognize that the transfer of the image data from the CGROM 83 to the frame memory 84A has been completed by confirming that the corresponding bit of the decoding execution instruction register has been reset.

  In this embodiment, the drawing processor 109 stores the moving image data (compressed data) of the CGROM 83 in the temporary storage area of the VRAM 84B, and the moving image decompression unit 89 targets the compressed data stored in the temporary storage area. Decryption processing is performed. However, the drawing processor 109 may read the compressed data from the CGROM 83 in units of 32 bits, and the moving image decompression unit 89 may perform the decoding process on the read compressed data. Then, the decoded image data is sequentially stored in the temporary storage area.

  As described above, the drawing control to the frame memory 84A based on the display control execution data set in the process data is executed. The display signal control unit 87 creates an image signal based on the image data developed in the frame memory 84A, outputs the image signal to the image display device 9, and realizes image display on the image display device 9. The display signal control unit 87 outputs an image signal based on the image data developed in the area 0 or the area 1 of the frame memory 84A during a V blank interruption occurrence interval (for example, 33.3 ms). The image is output to the image display device 9 in synchronization with the clock signal. The display signal control unit 87 displays an image signal based on the image data developed in the region 1 as the display region when the drawing control unit 91 develops the image data in the region 0 as the drawing region. 9, when the drawing control unit 91 develops image data for the area 1 as the drawing area, an image signal based on the image data developed in the area 0 as the display area is sent to the image display device 9. Output.

  In this embodiment, the moving image data stored in the CGROM 83 is transferred to the frame memory 84A after being decoded. However, before actual display based on moving image data is performed, the moving image data stored in advance in the CGROM 83 may be decoded and stored, for example, in a temporary storage area of the VRAM 84B. In that case, for example, the first display control execution data in the process table stores a command (for the drawing processor 109) that decodes the moving image data and expands it in the temporary storage area. In this case, a command for transferring image data from the temporary storage area of the VRAM 84B to the frame memory 84A may be set.

  FIG. 62 is a flowchart showing the customer waiting demonstration control process in the effect control main process (see FIG. 38). The game control microcomputer 560 transmits a customer-waiting demo designation command when, for example, the variable display of the special symbol or the big hit game is finished and the number of reserved memories is zero. In the command analysis process, the production control CPU 101 sets a customer waiting demo designation command reception flag when receiving a customer waiting demonstration designation command.

  In the customer waiting demonstration control process, the effect control CPU 101 confirms whether or not the customer waiting demonstration effect is being executed (step S601), and if not, whether or not the customer waiting demonstration designation command reception flag is set. (Step S602). If the customer waiting demonstration designation command reception flag is set, the customer waiting demonstration designation command reception flag is reset (step S603). Then, 0 is set in the address pointer (step S604), and fixed area data transfer control processing is executed (step S605). The fixed area data transfer control process is a process for transferring the image data (see FIG. 35B) stored in the common image data area of the CGROM 83 to the fixed area of the VRAM 84B, and the initial data in step S702. Although it is not essential to execute the fixed area data transfer control process at this stage, which is the same process as the process executed in the transfer process, for example, when the customer waiting demonstration demonstration is started, the fixed area data transfer control is performed. By executing the process, when data is garbled in the fixed area of the VRAM 84B due to some reason (for example, noise or the like), the image data in the fixed area of the VRAM 84B may be returned to correct data. it can.

  Next, the effect control CPU 101 sets “1” in the data bus mode register (see FIG. 34) in the drawing control register 95 (step S606). Then, the moving image mode flag is set (step S607). Next, process data corresponding to the demonstration of waiting for a customer is selected (step S608). Then, a process timer corresponding to the effect execution data 1 in the selected process data is started (step S609). Further, the control of the effect device is executed in accordance with the contents of the process data 1 (display control execution data 1, lamp control execution data 1, sound number data 1) (step S610). Then, a process data valid flag is set (step S611). When data related to moving image data is set in the display control execution data 1, the effect control CPU 101 executes the same control as steps S985 to S988 shown in FIG. Then, the moving image data is developed in the frame memory 84A. The drawing processor 109 executes a moving picture decoding process to be described later (see FIG. 60) in response to the corresponding bit in the decoding execution instruction register being set, and decodes the moving image data and expands it in the frame memory 84A.

  If the image data pre-transferred to the fixed area of the VRAM 84B is the image data of the demonstration screen for waiting for a moving image, the effect control CPU 101 also sets the data width of the CG bus to 32 in the process of step S605. In order to make bits, “1” is set in the data bus mode register (see FIG. 34) in the drawing control register 95. In addition, when the image data preliminarily transferred to the fixed area of the VRAM 84B is decorative pattern image data that is a still image, “0” is set in the data bus mode register, and the data width of the CG bus is 64 bits. It is.

  FIG. 63 is a flowchart showing a jackpot display process when a moving image is displayed on the image display device 9 during a jackpot game. In this case, the effect control CPU 101 sets “1” in the data bus mode register (see FIG. 34) in the drawing control register 95 before executing the process of step S893 (step S892A). Then, the moving image mode flag is set (step S892B). Other processes are the same as those shown in FIG. However, in this case, data related to a moving image is set in the display control execution data in the process table corresponding to the big hit game effect.

  FIG. 64 is an explanatory diagram showing a data bus in the CG bus between the drawing control unit 91 and the CGROM 83 in the drawing processor 109. In FIG. 64, the CG bus I / F 93 (see FIG. 4) is not shown. As shown in FIG. 64A, the data bus physically has 64 bits.

  FIG. 64A shows a case where two ROMs 83A and 83B are provided. However, when an additional ROM is added, as shown in FIG. It is necessary to provide ROMs 83C and 83D or a ROM capable of inputting and outputting 64-bit data. In FIG. 64B, for convenience of drawing, the ROM 83C and 83D are described such that the data bus extends from the ROM 83A and 83B. However, in actuality, between the drawing control unit 91 and the ROM 83A and 83B. The data bus is branched and wired to the ROMs 83C and 83D. As shown in FIG. 64B, when the bus width is 64 bits, the drawing control unit 91 inputs data 64 bits at a time. In that case, if one ROM 83C is provided when the ROM is added, the drawing control unit 91 masks (forcibly sets to 0) the upper 32 bits of the input 64-bit data, or sets two 64-bit data. It is necessary to perform processing such as creating 64-bit data from the lower 32 bits of each data.

  In the first embodiment (Embodiment 1), the CG bus mode is divided into a 64-bit mode in which all 64 bits are used as a data bus and a 32-bit mode in which lower 32 bits are used as a data bus. Switching is possible. Therefore, as shown in FIG. 64C, when reading image data from the ROM 83C in which moving image data is stored, the 32-bit mode is set and images are read from the ROM 83A and 83B in which still image data is stored. When reading data, if the 64-bit mode is set, the ROM 83C to be added can be made one. In FIG. 64C, the data bus is described as extending from the ROM 83A to the ROM 83C for the sake of drawing, but actually, the data bus between the drawing control unit 91 and the ROM 83A is branched. Wired to the ROM 83C. When configured as shown in FIG. 64C, when the bus width is 32 bits, that is, when the lower 32 bits are set to the 32-bit mode used as the data bus, the drawing control is performed. The unit 91 can input data by 32 bits. Therefore, the drawing control unit 91 can handle 32-bit data as it is by providing only one ROM 83C.

  Further, in the case where the ROM expansion is not performed and the CGROM 83 can be formed by the three ROMs 83A, 83B, and 83C as shown in FIG. 64C, when the present invention is not applied, the case shown in FIG. As shown, it is necessary to form the CGROM 83 with four ROMs 83A, 83B, 83C, 83D. That is, the number of ROMs used increases.

  The moving image data is stored in the ROM 83C in a compressed state. Therefore, the data amount is compressed as compared with the sprite images stored in the ROMs 83A and 83B. Then, the amount of data transfer processing from the CGROM 83 is small compared to the decoding processing by the drawing processor 109. Therefore, even if the bus width when reading moving image data (compressed data) from the CGROM 83 is narrowed to reduce the data transfer speed, the overall processing performance of the rendering processor 109 is not significantly reduced.

  Further, when the drawing processor 109 can execute the decoding process of the compressed data and the data reading process from the CGROM 83 at the same time, the moving image data (compressed data) is read from the CGROM 83 during the decoding process. Can do. Even in that case, since only 32 bits can be decoded at a time, the decoding process takes time. Therefore, the bus width when reading moving image data (compressed data) from the CGROM 83 is narrowed to reduce the data transfer speed. It can be said that there is no problem.

  The image data stored in the ROM 83C is not limited to moving image data. Still image data may also be stored in the ROM 83C used when the bus width is set to 32 bits. Conversely, moving image data may also be stored in the ROMs 83A and 84B used when the bus width is set to 64 bits.

Embodiment 2. FIG.
FIG. 65 shows a second embodiment in which a sound / lamp control board 80b and a symbol control board 80a are provided in place of the production control board 80, lamp driver board 35 and audio output board 70 shown in FIG. It is a block diagram which shows the structural example of Embodiment 2). As shown in FIG. 65, the sound / lamp control board 80b is mounted with a sound / lamp control microcomputer 100b including a sound / lamp control CPU 101b and a RAM. In the sound / lamp control board 80b, the sound / lamp control microcomputer 100b operates according to a program stored in a built-in or external ROM (not shown), and is input via the relay board 77. In response to the strobe signal (effect control INT signal) from, an effect control command is received via the input driver 102 and the input port 103.

  The sound / lamp control microcomputer 100 b outputs a signal for driving the lamp to the lamp driver 352. The lamp driver 352 amplifies a signal for driving the lamp and supplies the amplified signal to each lamp provided on the frame side such as the top frame lamp 28a, the left frame lamp 28b, the right frame lamp 28c, and the button lamp 130. Further, it is supplied to a decorative lamp 25 provided on the frame side. In addition, the sound / lamp control microcomputer 100b outputs sound number data to the speech synthesis IC 703. The voice synthesizing IC 703 generates voice and sound effects corresponding to the sound number data and outputs them to the amplifier circuit 175. The amplification circuit 705 outputs an audio signal obtained by amplifying the output level of the speech synthesis IC 703 to a level corresponding to the volume set by the volume 706 to the speaker 27. The voice data ROM 704 stores control data corresponding to the sound number data.

  The sound / lamp control microcomputer 100b transfers the received effect control command to the symbol control board 80a via the output port 104, and generates a command based on the received effect control command. The data is transmitted to the symbol control board 80a via the output port 104.

  As shown in FIG. 65, a symbol control microcomputer 100a including a symbol control CPU 101a and a RAM (not shown) is mounted on the symbol control board 80a. In the symbol control board 80a, the symbol control microcomputer 100a operates according to a program stored in a built-in or external ROM (not shown) and receives a command from the sound / lamp control board 80b via the input port 108. To do. Then, the symbol control microcomputer 100a causes the drawing processor 109 to perform display control of the image display device 9 using the LCD based on the received command.

  The symbol control microcomputer 100a operates in the same manner as the effect control microcomputer 100 in the first embodiment. Therefore, the command transmitted from the sound / lamp control microcomputer 100b to the symbol control microcomputer 100a is the same as the effect control command (see FIG. 14) in the first embodiment. The command received by the sound / lamp control microcomputer 100b from the game control microcomputer 560 is directly transferred to the symbol control microcomputer 100a, or the symbol control microcomputer 100a receives the command received from the game control microcomputer 560. By transmitting the command generated based on the symbol control microcomputer 100a, a command similar to the effect control command (see FIG. 14) in the first embodiment can be given to the symbol control microcomputer 100a.

  In each of the above embodiments, the drawing processor 109 realizes image synthesis by developing a plurality of component images in the frame memory 84A. For example, the moving image data of the background image is developed in the frame memory 84A by the moving image decoding process (see FIGS. 60 and 61) executed by the drawing processor 109 based on the processing of steps S985 to S988 by the effect control CPU 101. In the state, the decoration as a component image is performed by the processing shown in FIG. 58 or the processing shown in FIG. 59 executed by the drawing processor 109 based on the processing in steps S973 to S976 or the processing in steps S981 to S984. When the image data of the design or character image is developed in the frame memory 84A, the background image is combined with the decorative design or character image in the frame memory 84A. However, when the drawing processor 109 can create data constituting one screen by combining the data of a plurality of sprite screens, the plurality of sprite images are developed on different sprite screens, and then the plurality of sprite screens are displayed. Image composition can be realized by composition. For example, when data for specifying a moving image and data for specifying a decorative design are set as data for specifying a plurality of images to be combined in the display control execution data, the moving image decoding process is performed in step S1048. End with. At that time, moving image data is stored in a temporary storage area (corresponding to the first sprite screen). Next, when executing a process (see FIG. 58) for transferring decorative design image data from the fixed area of the VRAM 84B to the frame memory 84A, the drawing processor 109 converts the image data of the fixed area of the VRAM 84B to the second sprite screen. And the image data of the area corresponding to the first sprite screen is combined with the image data of the area corresponding to the second sprite screen. And transferred to the frame memory 84A.

  In each of the first embodiments, as shown in FIG. 66, the image data stored in the common image data area (see FIG. 35) of the CGROM 83 is transferred in advance to the fixed area of the VRAM 84B, and the effect mode is determined. (For example, when the production mode is changed), the image data stored in the selected image data area of the CGROM 83 (see FIGS. 35 and 66A) is transferred to a predetermined area in the fixed area of the VRAM 84B. However, as shown in FIG. 67, the image data stored in the common image data area of the CGROM 83 is transferred in advance to the fixed area of the VRAM 84B, and the image data stored in the selected image data area of the CGROM 83 is transferred to the VRAM 84B. It is preferable to forward to the temporary area. In such a configuration, the effect control CPU 101 uses the temporary area of the VRAM 84B instead of the instruction to transfer the image data from the selected image data area of the CGROM 83 to the fixed area of the VRAM 84B when the effect mode is determined. A command to transfer the image data to the fixed area of the VRAM 84B is output to the drawing processor 109.

  Further, in the first embodiment, the image data of the decorative pattern and figure “7” is stored in the selected image data area of the CGROM 83 (see FIG. 35). However, as shown in FIG. These images may be stored in the common image data area of the CGROM 83, and graphic image data may be stored in the selected image data area of the CGROM 83.

  When the transfer of the image data of the component image to the fixed area of the VRAM 84B is completed, the drawing processor 109 or the effect control CPU 101 stores the component image in the fixed area of the VRAM 84B in the index register provided in the drawing processor 109. Data indicating that the image data is stored may be set. FIG. 69 is an explanatory diagram of a configuration example of the index register. In the example shown in FIG. 69, 128 index areas are prepared in the index register. When the transfer to the fixed area of the VRAM 84B is completed, the start address and size (data amount) of the image data of the component image are set, and “1” is set in the flag area indicating that the transfer is completed. . An area of an index name indicating the type of image data of a component image is not essential but is preferably provided.

  For example, in the process of step S972 (see FIG. 57), the effect control CPU 101 determines that the component image existing in the index whose flag area is set to “1” exists in the fixed area of the VRAM 84B. can do.

  Further, instead of instructing the start address of the image data of the component image existing in the fixed area of the VRAM 84B by the arbitrary start address register in the fixed area (see step S973), an index number may be instructed.

  The present invention is suitably applied to a gaming machine that includes an image display device and can display still images and moving images for production on the image display device.

It is the front view which looked at the pachinko game machine from the front. It is a block diagram which shows the circuit structural example of a game control board (main board). It is a block diagram showing an example of circuit configuration of an effect control board, a lamp driver board and an audio output board. It is a block diagram which shows the circuit structural example of a drawing processor. It is a flowchart which shows the main process which CPU in a main board | substrate performs. It is a flowchart which shows a 2 ms timer interruption process. It is explanatory drawing which shows each random number. It is explanatory drawing which shows an example of a big hit determination value. It is explanatory drawing which shows an example of the multiple types of decoration symbol variably displayed in an image display apparatus. It is explanatory drawing which shows an example of a fluctuation pattern. It is explanatory drawing which shows an example of a fluctuation pattern table. FIG. 38E illustrates an effect control command signal line. It is a timing chart showing the relationship between an 8-bit control signal and an INT signal constituting a control command. It is explanatory drawing which shows an example of the content of an effect control command. It is explanatory drawing which shows an example of the transmission timing of an effect control command. It is a flowchart which shows a special symbol process process. It is a flowchart which shows a starting port switch passage process. It is a flowchart which shows a special symbol normal process. It is a flowchart which shows a special symbol stop symbol setting process. It is a flowchart which shows a fluctuation pattern setting process. It is a flowchart which shows a display result specific command transmission process. It is a flowchart which shows pending storage number designation command transmission processing. It is a flowchart which shows the special symbol change process. It is a flowchart which shows a special symbol stop process. It is a flowchart which shows a big hit end process. It is explanatory drawing which shows the display state of an image display apparatus when the reach effect by super reach is performed. It is explanatory drawing which shows the display state of an image display apparatus when the reach effect by super reach is performed. It is explanatory drawing which shows the example of the production | presentation aspect of reach production used in a normal state. It is explanatory drawing which shows an example of a customer waiting demonstration production. It is explanatory drawing which shows an example of the usage method of SDRAM. It is explanatory drawing which shows an example of the address map of a frame memory. It is explanatory drawing for demonstrating the method of expansion | deployment of the image data from CGROM to a frame memory. It is explanatory drawing which shows the data bus in the CG bus between the drawing control part and CGROM in a drawing processor. It is explanatory drawing for demonstrating an example of each register in a drawing control register. It is explanatory drawing for demonstrating the image data of the design symbol memorize | stored in CGROM. It is explanatory drawing which shows the data structure of moving image data among the image data of the components image memorize | stored in CGROM. It is explanatory drawing which shows the decoding method of the moving image data (compressed data) by which data compression was carried out. It is a flowchart which shows the presentation control main process which CPU for presentation control performs. It is a flowchart which shows production control process processing. It is a flowchart which shows a fluctuation pattern command reception waiting process. It is a flowchart which shows a decoration design change start process. It is explanatory drawing which shows the structural example of process data. It is a flowchart which shows a process during decoration design change. It is a flowchart which shows a decoration design change stop process. It is a flowchart which shows a big hit display process. It is a flowchart which shows a big hit end process. It is a flowchart which shows V blank interruption processing. It is explanatory drawing which shows the example of the data table stored in ROM. It is a flowchart which shows an initial data transfer process. It is a flowchart which shows a fixed area | region data transfer control process. It is a flowchart which shows the process which transfers image data from CGROM to the fixed area | region of VRAM. It is a flowchart which shows a data transfer process. It is a flowchart which shows the modification of the process which transfers image data from CGROM to the fixed area | region of VRAM. It is a flowchart which shows production mode # 1 data transfer control processing. It is a flowchart which shows the process which transfers image data from the selection image data area of CGROM to VRAM. It is a flowchart which shows the modification of the process which transfers image data to VRAM from the selection image data area of CGROM. It is a flowchart which shows a drawing control process. It is a flowchart which shows the process which transfers image data from the fixed area | region of VRAM to a frame memory. It is a flowchart which shows the process which transfers image data from CGROM to a frame memory. It is a flowchart which shows the moving image decoding process which transfers the image data of a moving image from CGROM to a frame memory. It is a flowchart which shows the moving image decoding process which transfers the image data of a moving image from CGROM to a frame memory. It is a flowchart which shows a customer waiting demonstration control process. It is a flowchart which shows a big hit display process. It is explanatory drawing which shows the data bus in the CG bus between a drawing control part and CGROM. It is a block diagram which shows the structural example provided with the sound / lamp control board and the symbol control board. It is explanatory drawing which shows an example of the transfer method of the image data to the fixed area | region of VRAM84B. It is explanatory drawing which shows the transfer method of the image data to the fixed area | region of VRAM84B. It is explanatory drawing for demonstrating the other example of the image data of the decorative design memorize | stored in CGROM. It is explanatory drawing which shows the structural example of an index register.

Explanation of symbols

1 Pachinko machine 8 Special symbol display 9 Production display 14 Start prize opening 31 Game control board (main board)
56 CPU
83 CGROM
84A VRAM
84B frame memory 87 display signal control unit 91 drawing control unit 95 drawing control register 560 game control microcomputer 80 effect control board 100 effect control microcomputer 101 effect control CPU
109 Drawing processor

Claims (6)

A game machine that can perform variable display of a plurality of types of identification information that can be identified by each image display device, and can control to a specific gaming state advantageous to the player when the display result of the identification information becomes a specific display result. There,
An effect control microcomputer for giving a command for controlling the display state of the image display device;
Image data storage means for storing a plurality of image data including image data of each identification information;
The image data stored in the image data storage means is connected to the image data storage means through a data bus so as to be readable, and stored in the image data storage means in response to a command from the effect control microcomputer. A drawing processor for performing processing for displaying an image on the image display device based on the image data being
The image data storage means includes a first ROM from which image data is read when the bus width of the data bus is set to the first bus width, and the bus width of the data bus is greater than the first bus width. And a second ROM from which image data is read when the second bus width is set to be narrow,
Moving image data is stored in the second ROM,
The drawing processor changes the bus width setting of the data bus from the first bus width to the second bus width when reading image data from the second ROM. Gaming machine. The second ROM stores moving image data in a compressed state,
The gaming machine according to claim 1, wherein the drawing processor includes decoding means for decoding the compressed data. The effect control microcomputer includes display effect selection means for selecting a display effect to be executed in the image display device when variable display of the identification information is performed from a plurality of types of display effects,
The plurality of types of display effects include a predetermined display effect that is more easily selected than when the display result of the identification information in the image display device is the specific display result compared to when the specific display result is not used.
The drawing processor changes the setting of the bus width of the data bus to the second bus width when the display effect selecting means selects the predetermined display effect as the display effect, and reads the image data from the second ROM. The gaming machine according to claim 1 or 2. The gaming machine according to any one of claims 1 to 3, wherein a sprite image used to display identification information as image data is stored in the first ROM. The drawing processor
Storage means for storing image data read from the image data storage means;
Frame storage means for setting image data;
Image display means for displaying an image on the image display device based on the image data set in the frame storage means;
A transfer unit that reads out image data having a frequency of use higher than predetermined image data from the image data storage unit and transfers it to a fixed storage area in the storage unit when power supply to the gaming machine is started;
When setting image data in the frame storage means, if the image data to be set in the frame storage means is transferred to the fixed storage area, the image data is read from the fixed storage area and the frame storage means Set to
When setting image data in the frame storage means, if the target image data to be set in the frame storage means is not transferred to the fixed storage area, the image data is read from the image data storage means, and the read image The game machine according to any one of claims 1 to 4, wherein data is set in the frame storage unit via a temporary storage area in the storage unit. The plurality of types of identification information includes common identification information used in any of the plurality of game modes, and each selected identification information used in each of the plurality of game modes,
The transfer means is
When power supply to the gaming machine is started, the image data of the common identification information is read from the image data storage means, transferred to the fixed storage area in the storage means,
The gaming machine according to claim 5, wherein when the game mode is determined, image data of selection identification information used in the game mode is read from the image data storage means and transferred to the storage means.

Images