JP2010049556A - Image processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image processor for reducing a memory capacity to be required for performing a program in each processor concerning an image processor with a plurality of processors. <P>SOLUTION: A ROM loader 2 reads programs for performing CPU cores 4A, 4B from a program ROM 1, and stores the programs in dual port memories 3A, 3B. The CPU cores 4A, 4B perform the programs stored in the dual port memories 3A, 3B. A plotting engine 6 directly reads image data, which is stored in the program ROM 1, and performs extension processing. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an image processing apparatus including a processor specialized for image processing and a processor for performing other processing.

  2. Description of the Related Art Conventionally, in a semiconductor integrated device having a plurality of processors, proposals have been made for a program download method executed by each processor. As a conventional technique in a circuit having a plurality of DSPs (Digital Signal Processors), “a DSP program download system for downloading a program to each of a plurality of digital signal processors used as a speech encoding / decoding circuit, Proposed with a program download memory for storing a program to be downloaded to each of the plurality of digital signal processors and a control means for controlling direct memory access from each of the plurality of digital signal processors to the program download memory " (For example, refer to Patent Document 1).

JP 2002-73341 A

  According to the technique described in Patent Document 1, a program is downloaded to a plurality of DSPs via a program download memory. However, a lot of memory is required to store the program. That is, a memory for storing a program in advance, a memory for downloading a program, and a built-in memory necessary for the DSP to execute the program are required, and each DSP executes as the entire semiconductor integrated device. A memory capacity three times the total program capacity is required.

  The present invention has been made to solve the above-described problems, and provides an image processing apparatus capable of reducing the memory capacity required for program execution of each processor in an image processing apparatus having a plurality of processors. To do.

An image processing apparatus according to the present invention includes:
A drawing processing logic circuit for performing image expansion processing;
A first CPU core for controlling the drawing processing logic circuit;
One or more second CPU cores;
First storage means for storing image data processed by the drawing processing logic circuit, a program executed by the first CPU core, and a program executed by the second CPU core;
A plurality of second storage means respectively connected to the first CPU core and the second CPU core;
Load means for reading out the program executed by the first CPU core and the program executed by the second CPU core from the first storage means and storing them in the second storage means;
The loading means reads a program executed by each of the first CPU core and the second CPU core at the time of initialization from the first storage means and stores the programs in the second storage means,
The first CPU core and the second CPU core execute a program stored in the second storage unit,
The drawing processing logic circuit reads image data from the first storage unit and performs image expansion processing when performing image expansion processing.

  According to the image processing apparatus having a plurality of CPU cores according to the present invention, the program stored in the first storage means is read and stored in the second storage means connected to each CPU core, Since the program stored in the second storage unit is directly executed, it is possible to reduce the memory capacity required for executing the program of each CPU core.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing a configuration of an image processing apparatus according to Embodiment 1 of the present invention. In FIG. 1, the image processing apparatus 20 includes a semiconductor integrated device 10 composed of an ASIC, an FPGA, or the like, and a program ROM 1.

  The semiconductor integrated device 10 includes a ROM loader 2, a dual port memory (denoted as DPMEM in the figure) 3A and 3B, CPU cores 4A and 4B, RAMs 5A and 5B, a drawing engine 6, a VRAM (Video Random-Access Memory) 7, an LCD It has a controller (referred to as LCDC in the figure) 8 and an LCD (Liquid Crystal Display) 9. The ROM loader 2 corresponds to the loading means of the present invention, and the dual port memories 3A and 3B correspond to the second storage means of the present invention.

  The semiconductor integrated device 10 is connected to a program ROM 1 which is a nonvolatile memory such as a flash memory. The program ROM 1 stores programs executed by the CPU cores 4A and 4B and drawing data such as compressed image data and font data. The program ROM 1 corresponds to the first storage unit of the present invention.

  The CPU core 4 </ b> A is a processor that performs display control, and controls the drawing engine 6. The CPU core 4B is a processor that performs communication control, and is connected to a communication interface (denoted as a communication I / F in the figure) 12. The CPU core 4A and the CPU core 4B are connected to each other and exchange processing results and processing instructions. The first CPU core of the present invention corresponds to the CPU core 4A of the first embodiment, and the second CPU core corresponds to the CPU core 4B. In the first embodiment, an example in which the number of CPU cores 4B is one will be described. However, a configuration in which a plurality of CPU cores 4B are provided according to functions to be executed may be employed.

  Dual port memories 3A and 3B are connected to the CPU cores 4A and 4B, respectively. The dual port memories 3A and 3B store programs executed by the CPU cores 4A and 4B. The RAMs 5A and 5B are working memories when the CPU cores 4A and 4B perform processing.

  The drawing engine 6 is a circuit that performs drawing data display processing such as decompression processing of compressed image data, expansion of font data, line drawing, circle drawing, rectangle drawing, and figure filling. The drawing engine 6 writes the data designated by the CPU core 4A into the VRAM 7. The VRAM 7 is a buffer memory for developing image data. The LCD controller 8 outputs the data written in the VRAM 7 to the LCD 9. The drawing engine 6 corresponds to the drawing processing logic circuit of the present invention. In the present invention, the term “image decompression processing” includes decompression processing of compressed images and expansion of font data. The image data of the present invention includes compressed image data and font data.

  FIG. 2 shows an example of data storage in the program ROM 1. In FIG. 2, “stored contents” and a “stored address” corresponding to the “stored content” are stored at the head of the data, and the start address and the end point address are stored. An execution program for the CPU core 4A, an execution program for the CPU core 4B, compressed image data, and font data are stored.

The operation of the semiconductor integrated device 10 having the above configuration will be described.
When the reset of the semiconductor integrated device 10 is released, the ROM loader 2 reads data from the head address of the program ROM 1 and confirms “stored contents” and “stored address”. Then, the start address and the end point address where the programs of the CPU cores 4A and 4B are stored are acquired, and the program stored at the acquired storage address is read and stored in the dual port memories 3A and 3B, respectively. At this time, the compressed image data and font data stored in the program ROM 1 are not read / stored.

  When loading of the program to the dual port memories 3A and 3B is completed, the ROM loader 2 releases the reset of the CPU cores 4A and 4B. When the reset is released, the CPU cores 4A and 4B directly read the program stored in the dual port memories 3A and 3B and start execution.

  For example, when an input to an input interface such as a touch panel or a switch (not shown) is performed, the CPU core 4B acquires this information via the communication interface 12, and performs necessary control processing according to a program stored in the dual port memory 3B. I do. When the display update of the LCD 9 is necessary, the CPU core 4B requests the CPU core 4A to update the display.

The CPU core 4A performs display control in response to a request from the CPU core 4B.
When displaying the compressed image data, the CPU core 4A designates the image data to be displayed and requests the drawing engine 6 to decompress the compressed image data. The drawing engine 6 directly reads the designated compressed image data from the program ROM 1, decompresses this image data, and writes it in the VRAM 7. When displaying the font data, the CPU core 4A specifies the font data to be drawn and requests the drawing engine 6 to expand the font data. The drawing engine 6 directly reads the designated font data from the program ROM 1 and writes this font data into the VRAM 7. The image data and font data written in the VRAM 7 are displayed on the LCD 9 by the LCD controller 8.

  As described above, according to the first embodiment, the ROM loader 2 reads the execution program of the CPU cores 4A and 4B from the program ROM 1 and stores them in the dual port memories 3A and 3B. The CPU cores 4A and 4B Since the programs stored in the memories 3A and 4B are executed, the memory capacity mounted on the semiconductor integrated device 10 can be reduced. In addition, drawing data such as compressed image data and font data is stored in the program ROM 1, and the drawing engine 6 directly reads out from the program ROM 1 to perform decompression processing and expansion processing. The memory capacity to be provided can be reduced.

  Note that the program ROM 1 can use a memory having a low access speed, such as a serial flash memory. By doing so, it is possible to configure the image processing apparatus 20 at a low cost and in a small size. Since the CPU cores 4A and 4B execute programs loaded in the dual port memories 3A and 3B, the processing speed of the CPU cores 4A and 4B does not decrease.

Embodiment 2. FIG.
FIG. 3 is a block diagram showing the configuration of the image processing apparatus according to Embodiment 2 of the present invention. The difference between the second embodiment and the first embodiment described above is that the ROM arbiter 11 is provided and the CPU core 4A is not provided with a dual port memory for program execution. Hereinafter, the difference will be mainly described.

  In FIG. 3, the program ROM 1 is connected to the CPU core 4 </ b> A and the drawing engine 6 via the ROM arbiter 11. The ROM arbiter 11 switches the priority of access from the CPU core 4 </ b> A to the program ROM 1 and access from the drawing engine 6. Here, the ROM arbiter 11 corresponds to the arbitrating means of the present invention.

  Unlike the CPU core 4B, the CPU core 4A does not have a dual port memory for program execution. When the CPU core 4A executes the program, the program is directly read from the program ROM 1 via the ROM arbiter 11 and executed. The ROM arbiter 11 controls the CPU core 4A to always give priority to access from the CPU core 4A while the program is being executed.

Next, the operation when displaying on the LCD 9 will be described taking the case of displaying compressed image data as an example.
The CPU core 4A designates image data to be drawn and requests the drawing engine 6 to decompress the compressed image data. Then, the ROM arbiter 11 temporarily stops the CPU core 4A and controls the drawing engine 6 to be connected to the program ROM 1. When the drawing engine 6 confirms that the CPU core 4A is stopped, the drawing engine 6 takes out the designated compressed image data from the program ROM 1 and performs expansion processing. When the decompression process is completed, the ROM arbiter 11 is notified of the completion of the decompression process. When the ROM arbiter 11 confirms that the drawing engine 6 has finished using the program ROM 1, the ROM arbiter 11 resumes the operation of the CPU core 4A from the address of the program counter value when the CPU core 4A is stopped.

  As described above, according to the second embodiment, the CPU core 4A that controls the drawing engine 6 directly reads and executes the program from the program ROM 1, so that the dual-port memory for executing the program of the CPU core 4A is used. The memory capacity mounted on the semiconductor integrated device 10 can be reduced. Further, since the drawing data is stored in the program ROM 1 and the drawing engine 6 is directly read from the program ROM 1, the semiconductor integrated device 10 does not have to be equipped with a memory for storing the drawing data. Since the ROM arbiter 11 controls the access to the program ROM 1 from the CPU core 4A and the drawing engine 6, both the CPU core 4A and the drawing engine 6 can access the program ROM 1 at a necessary timing. it can.

Embodiment 3 FIG.
FIG. 4 is a block diagram showing a configuration of an image processing apparatus according to Embodiment 3 of the present invention. The difference between the third embodiment and the first embodiment described above is that a dual port memory 3A for executing a program of the CPU core 4A is connected to the CPU core 4B-1, and the control of the CPU core 4B-1 In motion. Hereinafter, the difference will be mainly described.

  In FIG. 4, a CPU core 4B-1 is connected to a program ROM 1 via a ROM arbiter 11. The program ROM 1 stores programs executed by the CPU cores 4A and 4B, compressed image data, font data, and the like. Drawing data is stored. The ROM arbiter 11 has a function of arbitrating the bus of the program ROM 1.

  When the reset of the semiconductor integrated device 10 is released, the CPU core 4B-1 reads and executes the execution program for the CPU core 4B-1 from the program ROM 1 via the ROM arbiter 11. The execution program for the CPU core 4B-1 includes a program for reading the execution program for the CPU core 4A stored in the program ROM 1 and storing it in the dual port memory 3A. Therefore, when the CPU core 4B-1 executes its own execution program, the execution program for the CPU core 4A is read from the program ROM 1 via the ROM arbiter 11 and stored in the dual port memory 3A. . At this time, the CPU core 4B-1 holds the reset state for the CPU core 4A until the loading of the program to the dual port memory 3A is completed. When the loading of the program to the dual port memory 3A is completed, the CPU core 4B-1 releases the reset state of the CPU core 4A and activates the CPU core 4A.

  The CPU core 4A directly reads and executes the program loaded in the dual port memory 3A. When displaying on the LCD 9, as in the first embodiment, the drawing engine 6 that has received an instruction from the CPU core 4A reads compressed image data and the like from the program ROM 1 via the ROM arbiter 11, decompresses, and the like. Is written in the VRAM 7. The image data and font data written in the VRAM 7 are displayed on the LCD 9 by the LCD controller 8.

As described above, according to the third embodiment, the load processing of the execution program of the CPU core 4A to the dual port memory 3A is performed by the execution program of the CPU core 4B-1. There is no need to provide it. For this reason, the volume of the logic circuit of ASIC and FPGA which constitutes the semiconductor integrated device 10 can be reduced.
Further, since the CPU core 4B-1 reads the program ROM1 via the ROM arbiter 11 and executes the program, there is no need to provide a dual port memory for the CPU core 4B-1, and the semiconductor integrated device 10 The installed memory capacity can be reduced. Since the drawing data is stored in the program ROM 1 and the drawing engine 6 is read from the program ROM 1 via the ROM arbiter 11, the drawing data is stored in the semiconductor integrated device 10 as in the first embodiment. It is not necessary to install a memory for storing.

  In the third embodiment, the CPU core 4B-1 is configured to read and execute the execution program from the program ROM 1 via the ROM arbiter 11, but as in the second embodiment, the CPU core 4B-1 −1 program execution dual port memory and ROM loader may be provided in the semiconductor integrated device 10.

Embodiment 4 FIG.
In the fourth embodiment, an example will be described in which the execution program of the CPU core 4A is divided and stored in the program ROM 1 in the same basic configuration as in the third embodiment. The fourth embodiment will be described with a focus on differences from the third embodiment described above with reference to FIG.

  The execution program for the CPU core 4A stored in the program ROM 1 is divided and stored for each function. That is, the execution program for the CPU core 4A divided for each function is stored in a separate storage address.

  When the reset of the semiconductor integrated device 10 is released, the CPU core 4B-1 reads the execution program for the CPU core 4B from the program ROM 1 via the ROM arbiter 11, and executes it. Then, the CPU core 4B-1 acquires only the program of the function executed by the CPU core 4A from the program ROM 1, and loads it into the dual port memory 3A. When the reset of the CPU core 4A is released, the CPU core 4A directly reads from the dual port memory 3A and executes the program.

  When switching the function of the CPU core 4A, the CPU core 4B-1 temporarily stops the operation of the CPU core 4A and puts it in the reset state. Then, a program having another function of the CPU core 4A is loaded from the program ROM 1 into the dual port memory 3A. When the loading is completed, the CPU core 4B-1 releases the reset of the CPU core 4A, and the CPU core 4A executes the program loaded in the dual port memory 3A. As a result, the CPU core 4A can execute another function.

  When displaying on the LCD 9, as in the first embodiment, the drawing engine 6 that has received an instruction from the CPU core 4A reads the compressed image data from the program ROM 1 and performs processing such as decompression. Write to VRAM7. The image data and font data written in the VRAM 7 are displayed on the LCD 9 by the LCD controller 8.

  As described above, according to the fourth embodiment, the execution program of the CPU core 4A is divided for each function, and only the program to be executed at that time is loaded into the dual port memory 3A. Less memory capacity is required. Therefore, the capacity of the dual port memory 3A provided in the semiconductor integrated device 10 can be reduced. Further, the effect obtained in the above-described third embodiment can be obtained in the same manner.

Embodiment 5 FIG.
In the fifth embodiment, an example in which the CPU core 4A is a CPU core that executes microcode in the same basic configuration as that of the third embodiment will be described. A CPU core that executes microcode refers to a CPU that directly executes an execution program described in microcode. The fifth embodiment will be described with a focus on differences from the third embodiment described above with reference to FIG.

  The program ROM 1 stores a program written in microcode as an execution program for the CPU core 4A. In addition, the program executed by the CPU core 4B-1 and drawing data such as compressed image data and font data are stored in the same manner as in the third embodiment.

  When the reset of the semiconductor integrated device 10 is released, the CPU core 4B-1 reads the execution program for the CPU core 4B from the program ROM 1 via the ROM arbiter 11, and executes it. When the display update of the LCD 9 is necessary, for example, when the CPU core 4B-1 wants to change the screen display of the LCD 9 in accordance with the communication processing by the CPU core 4B-1, the display update to the CPU core 4A is performed. Request. At this time, requests to the CPU core 4A are sequentially transmitted to the dual port memory 3A sequentially as microcode. The CPU core 4A sequentially reads and executes the microcode stored in the dual port memory 3A.

  The microcode transmitted to the dual port memory 3A is only a program to be executed by the CPU core 4A when the CPU core 4B-1 executes the process. Therefore, the memory capacity of the dual port memory 3A may be small. More specifically, when a similar process is performed, a processing program such as a conditional branch is required when using a fixed program to compare the use of microcode with the use of a fixed program. As a result, the size of the execution program to be stored in the dual port memory 3A increases. For example, when the CPU core 4A performs processing according to the processing of the CPU core 4B-1, the execution program for the CPU core 4A, which is a fixed program, includes a conditional branch program corresponding to the processing content of the CPU core 4B-1. Will be included. On the other hand, when microcode is used, the CPU core 4A needs only microcode to be executed in accordance with the processing execution of the CPU core 4B-1. That is, since conditional branch processing in the fixed program is performed by the CPU core 4B-1, conditional branch processing is not necessary for the program executed by the CPU core 4A, and the program size required for execution of the CPU core 4A is reduced. .

  As described above, according to the fifth embodiment, when the CPU core 4A that executes microcode is used, only the microcode corresponding to the processing content of the CPU core 4B-1 is stored in the dual port memory 3A. Therefore, the memory capacity required for the dual port memory 3A may be small. Therefore, the capacity of the dual port memory 3A provided in the semiconductor integrated device 10 can be reduced. Further, the effect obtained in the above-described third embodiment can be obtained in the same manner.

  In the first to fifth embodiments described above, the example in which the program ROM 1 is used as the first storage unit has been described. However, other storage units having the same function may be used. Further, although an example in which a dual port memory is provided as the second storage means has been described, a single port read / write SRAM or other storage means having similar functions may be used.

1 is a block diagram illustrating a circuit configuration of an image processing apparatus according to Embodiment 1. FIG. 1 shows a configuration of a program ROM of an image processing apparatus according to a first embodiment. 6 is a block diagram illustrating a circuit configuration of an image processing apparatus according to Embodiment 2. FIG. 6 is a block diagram illustrating a circuit configuration of an image processing apparatus according to Embodiments 3 to 5. FIG.

Explanation of symbols

  1 program ROM, 2 ROM loader, 3A dual port memory (DPMEM), 3B dual port memory (DPMEM), 4A CPU core, 4B, 4B-1 CPU core, 6 drawing engine, 7 VRAM, 8 LCD controller (LCDC), 9 LCD, 10 image processing device, 11 ROM arbiter, 12 communication interface (communication I / F), 20 image processing device.

Claims (6)

A drawing processing logic circuit for performing image expansion processing;
A first CPU core for controlling the drawing processing logic circuit;
One or more second CPU cores;
First storage means for storing image data processed by the drawing processing logic circuit, a program executed by the first CPU core, and a program executed by the second CPU core;
A plurality of second storage means respectively connected to the first CPU core and the second CPU core;
Load means for reading out the program executed by the first CPU core and the program executed by the second CPU core from the first storage means and storing them in the second storage means;
The loading means reads a program executed by each of the first CPU core and the second CPU core at the time of initialization from the first storage means and stores the programs in the second storage means,
The first CPU core and the second CPU core execute a program stored in the second storage unit,
The image processing apparatus, wherein the drawing processing logic circuit reads image data from the first storage unit and performs image expansion processing when performing image expansion processing. The image processing apparatus according to claim 1, wherein the first storage unit is a serial access nonvolatile memory. A drawing processing logic circuit for performing image expansion processing;
A first CPU core for controlling the drawing processing logic circuit;
One or more second CPU cores;
First storage means for storing image data processed by the drawing processing logic circuit and a program executed by the first CPU core;
Arbitrating means for arbitrating bus access to the first storage means;
The arbitration unit performs arbitration between bus access to the first storage unit by the first CPU core and bus access to the first storage unit by the drawing processing logic circuit;
The first CPU core executes a program stored in the first storage means,
The image processing apparatus, wherein the drawing processing logic circuit reads image data from the first storage unit and performs image expansion processing when performing image expansion processing. A drawing processing logic circuit for performing image expansion processing;
A first CPU core for controlling the drawing processing logic circuit;
One or more second CPU cores;
First storage means for storing image data processed by the drawing processing logic circuit and a program executed by the first CPU core;
Second storage means connected to the first CPU core,
One of the second CPU cores reads a program executed by the first CPU core from the first storage unit and stores the program in the second storage unit,
The first CPU core executes a program stored in the second storage means,
The image processing apparatus, wherein the drawing processing logic circuit reads image data from the first storage unit and performs image expansion processing when performing image expansion processing. 5. The CPU core according to claim 4, wherein one of the second CPU cores switches a program to be read from the first storage unit in accordance with a processing content to be executed by the first CPU core. Image processing apparatus. The first CPU core is in a form of executing microcode;
5. The image processing apparatus according to claim 4, wherein one of the second CPU cores stores microcode corresponding to its processing result in the second storage unit.

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