JP2014016892A - Semiconductor memory device and method of controlling the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a ROM value from being corrupted even when the stability of a clock being used is not secured.SOLUTION: A semiconductor memory device comprises: first storage means from which data is read according to a read address corresponding to a first clock; second storage means to which the data read from the first storage means according to a write address corresponding to the first clock is written and from which the data written according to a read address corresponding to a second clock is read; and address generation means that confirms the stabilization of the first clock, fixes the read address of the first storage means to a fixed value when the first clock is not stabilized, generates the read address corresponding to the first clock to the first storage means when the first clock is stabilized, and generates the write address corresponding to the first clock to the second storage means.

Description

  The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device used for an FPGA or the like and a control method thereof.

  On-chip read only memory (hereinafter referred to as ROM) is widely used in field programmable gate arrays (hereinafter referred to as FPGA) and various large scale integrated circuits. Such a configuration is disclosed in, for example, Japanese Patent Laid-Open No. 2000-151388. Programs and data stored in the ROM (hereinafter referred to as ROM values) are referred to by a user circuit having a desired function and are necessary for realizing the desired function, and the ROM value is destroyed for some reason. There is a problem that the device malfunctions.

  In the latest FPGA, a random access memory (hereinafter referred to as RAM) block is generally mounted in large quantities. Also, it is common that an initial value can be given to the RAM when configuring the FPGA. Therefore, when a large-scale ROM is realized in the FPGA using this feature, the ROM function is often realized by giving an initial value to the RAM.

  By using such a method, it is possible to prevent a lookup table (Look Up Table, hereinafter referred to as LUT) from being consumed for realizing the ROM function, and to allocate the LUT for realizing the user circuit. In the FPGA, it is common to realize a large-scale circuit by effectively utilizing the LUT in this way. In particular, the larger the ROM size, the more effective the LUT can be used.

JP 2000-151388 A

  When a RAM with an initial value is used to realize a ROM, there are the following problems. That is, since the memory cell for storing the ROM value is composed of the RAM, when the ROM read clock (Clock) becomes unstable, the setup time / hold time of the address signal cannot be satisfied (hereinafter, referred to as “the read time”). As a result, a multi-address access state occurs in the RAM, and the retained value of the memory cell that has become the multi-address may be destroyed. Therefore, it is necessary to supply a stable clock as a read clock of the ROM using the RAM with the initial value. However, in communication devices, the clock is often not stable especially when the apparatus is started up for various reasons. In such a case, the ROM value is destroyed.

  It should be noted that the ROM value is destroyed not only in address racing at the time of writing to the RAM, but also in the memory cell holding value may be destroyed by address racing at the time of reading. That is. Therefore, the ROM value may be destroyed even by the read-only operation.

  Specific cases where the clock is not stable include the following cases. In other words, when a phase locked loop (PLL) is used for the clock line, the device is turned on and the time until the PLL is locked after that, or when the PLL is unlocked for some reason, is locked again. It is the time between. Further, in a circuit (Clock Data Recovery, hereinafter referred to as CDR) that extracts a clock from received data (Data), a time until a clock is extracted from received data and the clock extraction PLL is locked, or a clock extraction PLL Is the time between when the lock is released for some reason and then locked again.

  Also, in an apparatus having a specification in which the clock line is switched according to the mode of the apparatus, it is the moment when the clock line is switched. Furthermore, it is the moment when a strong surge noise is received from the outside due to lightning.

  A configuration of a known semiconductor memory device is shown in FIG. The ROM is composed of a RAM with an initial value, operates with a user circuit clock, and is directly referenced from the user circuit. A time chart at this time is shown in FIG. In FIG. 12, it is assumed as an example that a glitch is placed on the clock line due to surge noise or the like. When the rising edge of the glitch almost coincides with the address change point and the Setup Time / Hold Time defined in the address line is not satisfied, address racing occurs, and the operation may be as if multiple addresses are specified. .

  Next, FIG. 13 shows the internal structure of the RAM of the RAM with an initial value constituting the ROM of FIG. The RAM is an example of a general FPGA static RAM (Static RAM). When a plurality of address lines (in this example, address 0 (Add_0) and address 16 (Add_16)) become valid, a collision occurs between the memory cells arranged at the valid address, and the memory cells hold the memory cells. Information may be destroyed.

  Actually, various protection circuits are mounted so that the clock does not become unstable in any case. However, in practice, it is difficult to realize simple and complete protection, and as a result, the evaluation is performed for grasping the ability value over a sufficiently long time when evaluating the apparatus. That is, there is a problem that it takes a lot of time to evaluate the apparatus.

  In addition, in order to avoid the problem of ROM instability, there is a method of realizing the ROM by a combinational circuit using an LUT. However, in this case, since the LUT in the FPGA is consumed for realizing the ROM function, there is a problem that the number of LUTs that can be used for the user circuit is limited.

  Another problem when using a RAM with an initial value to realize the ROM function is that the memory cell is composed of RAM, so the value held in the memory cell due to soft error due to the influence of α rays and cosmic rays May be destroyed. That is, in this case, the ROM value is destroyed.

  Actually, in the case of a 1-bit error, the error can be corrected by an Error Check and Correct (hereinafter referred to as ECC) circuit, and the actual problem is when a 2-bit error occurs in the same Word line. In the ECC circuit, a 2-bit error can recognize whether or not an error has occurred, but cannot correct the error. Therefore, there is a problem that the error correction technique is not perfect.

  As described above, in the known FPGA ROM, the ROM value may be destroyed by address racing unless the stability of the clock to be used is ensured, and recovery is impossible. is there. In addition, in order to confirm the stability of the clock to be used, a long time aging in a bad environment is required at the time of evaluation, and there is a problem that the development period becomes long. Further, when the ROM is realized by the LUT, there is a problem that a large amount of FPGA LUT resources are consumed and the number of LUTs that can be allocated to the user circuit is reduced. Furthermore, when a 2-bit error occurs due to a soft error or the like, there is a problem that correction cannot be performed even if an ECC circuit is used.

  The present invention has been made in view of the above problems, and its purpose is to prevent the ROM value from being broken even when the stability of the clock to be used is not ensured and to confirm the stability of the clock to be used. To eliminate the need for long-term aging in an adverse environment during evaluation, eliminate the need to implement a ROM with a LUT, prevent a decrease in the LUT allocated to the user circuit, and develop into a 2-bit error due to a software error, etc. An object of the present invention is to provide a semiconductor memory device and a control method therefor, which can correct a bit error using an ECC circuit by preventing the error.

  First storage means for reading data corresponding to a read address corresponding to a first clock, and the first storage means read corresponding to a write address corresponding to the first clock Data is written, and the written data is read corresponding to a read address corresponding to a second clock. The second storage means and the stabilization of the first clock are confirmed, and the first clock is checked. When the first clock is not stabilized, the read address of the first storage unit is fixed to a fixed value, and when the first clock is stabilized, the first storage unit stores the first address in the first storage unit. Address generating means for generating the read address corresponding to the first clock and generating the write address corresponding to the first clock in the second storage means; A semiconductor memory device having a.

  In addition, the data stored in the first storage means is written to the second storage means by the first clock, and the data is transferred from the second storage means to a circuit that performs a desired operation by the second clock. A semiconductor memory device control method for reading, wherein the first clock stabilization is confirmed, and when the first clock is not stabilized, the read address of the first storage means Is fixed to a fixed value, and when the first clock is stabilized, a read address in the first storage means and a write address in the second storage means in correspondence with the first clock. Generating the data, reading the data stored in the first storage means by the read address, and reading the data by the write address A method for controlling a semiconductor memory device, comprising: a writing process for writing to the second storage means; and a reading process for reading the data written in the second storage means to the circuit by the second clock. .

  Even if the stability of the clock to be used is not ensured by the semiconductor memory device and the control method thereof according to the present invention, the ROM value of the ROM as the first memory means is prevented from being broken, resulting in a device failure. Can be prevented. In addition, since the stability of the clock to be used is confirmed, there is no need for long-term aging in a bad environment at the time of evaluation, and the development period can be shortened. Furthermore, it is not necessary to implement a ROM with an LUT, and an FPGA LUT resource can be allocated to a user circuit, thereby preventing a decrease in the LUT allocated to the user circuit.

1 is a diagram showing a configuration of a semiconductor memory device according to a first embodiment of the present invention. It is a figure which shows operation | movement of the semiconductor memory device of the 1st Embodiment of this invention. It is a figure which shows operation | movement of the semiconductor memory device of the 1st Embodiment of this invention. It is a figure which shows operation | movement of the semiconductor memory device of the 1st Embodiment of this invention. It is a figure which shows operation | movement of the semiconductor memory device of the 1st Embodiment of this invention. It is a figure which shows the structure of the semiconductor memory device of the 2nd Embodiment of this invention. It is a figure which shows the structure of the semiconductor memory device of the 2nd Embodiment of this invention. It is a figure which shows the structure of the semiconductor memory device of the 2nd Embodiment of this invention. It is a figure which shows operation | movement of the semiconductor memory device of the 2nd Embodiment of this invention. It is a figure which shows the structure of the semiconductor memory device of the 2nd Embodiment of this invention. It is a figure which shows the structure of a known semiconductor memory device. It is a figure which shows operation | movement of a known semiconductor memory device. It is a figure which shows the internal structure of RAM with an initial value which comprises ROM.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the preferred embodiments described below are technically preferable for carrying out the present invention, but the scope of the invention is not limited to the following.
(First embodiment)
With reference to FIG. 1, a semiconductor memory device and a control method thereof according to a first embodiment of the present invention will be described.

The ROM 1 is a RAM with an initial value. The clock generated by the PLL 2 which is the clock generating means in the FPGA 10 is supplied to the clock of the ROM 1 and the address of the ROM 1 is fixed to a fixed value until the PLL 2 becomes stable. Even if it becomes, address racing is prevented by the fixed address. Further, the ROM value of the ROM 1 is temporarily copied to the RAM 4 which is the second storage means using the clock of the PLL 2, and the user circuit 6 accesses the RAM 4 by the user circuit Clock. Thereby, even when the clock of the user circuit 6 becomes unstable, the ROM value of the ROM 1 main body is not destroyed.
(Description of configuration)
In FIG. 1, a ROM 1 as a first storage means is a RAM with an initial value, a PLL 2 as a clock generation means generates and supplies a stable clock, and an address counter 3 as an address generation means uses a ROM value of the ROM 1. Addresses are given to the ROM 1 and the RAM 4 for copying to the RAM 4 as the second storage means, the RAM 4 passes the ROM value to the user circuit 6, and the address arbitration circuit 5 as the address arbitration means sets the write address and the read address of the RAM 4 Arbitration to prevent competition. The user circuit 6 receives a ROM value from the RAM 4 and executes a desired function.

  Further, details of the semiconductor memory device and its control method according to the first embodiment of FIG. 1 will be described. On the side of the PLL Clock domain in FIG. 1, ROM values that are programs and data are written in the ROM 1. The ROM 1 is composed of a RAM with an initial value. An SRAM can be used as the RAM. The initial value is obtained by preparing an initial value file (not shown in FIG. 1) stored in a separate ROM and loading this value.

  The PLL 2 receives the reference clock (Ref_Clock) and starts operation after the configuration of the FPGA 10 is completed. The Ref_Clock can be generated and supplied by an internal circuit of the FPGA 10 (not shown in FIG. 1). The PLL 2 starts operating, stabilizes the transmission frequency, and generates and supplies a stable clock when the lock (PLL_Lock) is applied.

  The PLL 2 supplies a PLL_Lock signal to the address counter 3, and supplies Clock as Read_Clock to the ROM 1, Write_Clock to the RAM 4, and Clock to the address counter 3 and the address arbitration unit 5.

  The address counter 3 fixes the address value to 0, for example, before confirming the PLL_Lock signal from the PLL 2. Accordingly, the address (Read_Add) of the ROM 1 is fixed to a similar fixed value such as 0, for example. Therefore, when PLL2 is unlocked and Clock is unstable, the address of ROM1 is fixed, so that address racing can be prevented and the ROM value of ROM1 is not destroyed.

  The address counter 3 confirms the supply of the PLL_Lock signal from the PLL 2, and starts the generation of Address when a Count_EN signal (described later) is supplied from the address arbitration unit 5. That is, the address counter 3 confirms the stabilization of the clock by confirming the PLL_Lock signal.

  The address counter 3 generates an address corresponding to the clock supplied from the PLL 2 by a PLL_Lock signal and a Count_EN signal (described later). Then, the same address is supplied as a read address (Read_Add) to the ROM 1, a write address (Write_Add) to the RAM 4, and an address (Address) to the address arbitration unit. In response to this address, the ROM value (Data_Out) of the ROM 1 is read, and the read ROM value is written to the RAM 4 (Data_In).

  On the other hand, on the user clock domain side, the user circuit Clock is supplied as Read_Clock to the RAM 4 and to the address arbitration unit 5 and the user circuit 6 as Clock. This user circuit Clock can be generated and supplied by an internal circuit (not shown in FIG. 1) of the FPGA 10, for example. The user circuit Clock can also be given from the outside.

  Corresponding to the supplied user circuit Clock, the user circuit 6 generates an address (Read_Add) and gives this address to the RAM 4 as Read_Add. Corresponding to this address, the ROM value (Data_Out) written in the RAM 4 is read out to the user circuit 6 (Data_In).

  On the other hand, the user circuit 6 supplies the address (Read_Add) to the address arbitration unit 5 as an address. The address arbitration unit 5 receives the supply of Address from the user circuit 6 and detects whether or not Write_Add and Read_Add in the RAM 4 are competing. The contention here means a state in which Write_Add and Read_Add in the RAM 4 are the same and set at the same time. When the address arbitration unit 5 detects this conflict, the address arbitration unit 5 stops supplying the Count_EN signal to the address counter 3.

In response to the stop of the Count_EN signal, the address counter 3 stops the generation of Address. The address arbitration unit 5 performs monitoring every clock, and when it detects that there is no conflict, it starts supplying the Count_EN signal to the address counter 3 again. The address counter 3 receives the Count_EN signal and restarts the generation of Address. In response to this address, the ROM value (Data_Out) of the ROM 1 is read, and the read ROM value is written to the RAM 4 (Data_In).
(Description of operation)
FIG. 2 shows a time chart of the first embodiment shown in FIG. The operation of the semiconductor memory device according to the first embodiment will be described with reference to FIG.

  First, when the configuration of the FPGA 10 is completed and the operation of the internal circuit (not shown in FIG. 1) becomes valid, the Config_Done signal becomes valid and the PLL 2 starts to operate. That is, PLL_Clock becomes valid and generation of Clock starts.

  Second, when the oscillation frequency of PLL2 is stabilized, PLL2 is locked and PLL_Lock becomes valid. As a result, a stabilized clock is generated and supplied by the PLL 2. Upon detecting that the PLL_Lock has become valid, the address counter 3 starts generating an address. This address is supplied as Read_Address in ROM 1 and Write_Address in RAM 4. The ROM value of the ROM 1 is read by the Read_Address of the ROM 1 and the Write_Address of the RAM 4, and the read ROM value is written to the RAM 4.

  Third, when the transfer is completed, the write completion signal becomes valid, and the operation of the user circuit becomes possible. Confirmation of the completion of writing is performed by an internal circuit of the FPGA 10 (not shown in FIG. 1). Furthermore, the internal circuit supplies the write completion signal to the user circuit (not shown in FIG. 1). The user circuit receives the validity of the write completion signal, reads the ROM value from the RAM 4 by Read_Address corresponding to the user circuit Clock that has been validated before the completion of the write, and is generated by the user circuit and supplied to the RAM 4. Start the operation.

  This user circuit Clock can be generated and supplied by an internal circuit (not shown in FIG. 1) of the FPGA 10, for example. The user circuit Clock can also be given from the outside.

  Fourth, the ROM value of the ROM 1 is repeatedly written into the RAM 4 at a time when the user circuit is set not to access the RAM 4. By repeatedly writing the ROM value of ROM1 to RAM4, even if the ROM value written to RAM4 is destroyed due to instability of the user circuit clock, the device operates normally from the time it is rewritten. You can return to

  FIG. 3 shows another embodiment of the time chart of FIG. In the second and subsequent writings from the ROM 1 to the RAM 4, it is not always necessary to write the entire contents of the ROM 1 at once, and writing may be performed in multiple times such as 1, 2, and 3 as shown in FIG. Depending on the degree of access from the user circuit, the writing schedule may be changed as appropriate. Thus, there is an effect that the operation of the user circuit can be prevented from being hindered.

  FIG. 4 shows still another embodiment of the time chart of FIG. As long as the conflict between the write address and the read address of the RAM 4 does not occur, the writing and reading of the RAM 4 may be performed simultaneously. Thus, there is an effect that the operation of the user circuit can be prevented from being hindered.

FIG. 5 shows still another embodiment of the time chart of FIG. The write operation need not always be performed, and the write interval may be determined in consideration of the stability of the user circuit Clock. By doing so, it is possible to suppress the number of reading operations of the ROM 1 and the writing operation of the RAM 4, and as a result, power consumption can be reduced.
(Explanation of effect)
As described above, by using a stable clock for the ROM 1, even if the clock of the user circuit becomes unstable, the value of the RAM 4 is broken at that moment and the device malfunctions for a moment, but the ROM value of the ROM 1 is broken. Therefore, the apparatus can operate stably when writing is again performed from the ROM 1 to the RAM 4.

As described above, in the semiconductor memory device according to the first embodiment of the present invention, even when the stability of the clock to be used is not ensured, the ROM value is prevented from being broken, and as a result, it is prevented from developing into a device failure. be able to. In addition, since the stability of the clock to be used is confirmed, there is no need for long-term aging in a bad environment at the time of evaluation, and the development period can be shortened. Furthermore, it is not necessary to implement a ROM with an LUT, and an FPGA LUT resource can be allocated to a user circuit, thereby preventing a decrease in the LUT allocated to the user circuit.
(Second Embodiment)
A semiconductor memory device according to the second embodiment of the present invention will be described with reference to FIGS. The configuration of the second embodiment is the same as that of the first embodiment except that an ECC circuit as an error correction unit is added.

  FIG. 6 shows an example in which an ECC circuit (Decoder) 7 capable of correcting a 1-bit signal error for each word line is added to the output side of the ROM 1. This measure enables error correction even if a 1-bit error occurs in the ROM 1 value due to a soft error or the like. In this case, it is necessary to provide error correction bits (corresponding to ECC bits, ECC_Out of ROM1 and ECC_In of ECC circuit 7) as initial values when configuring the FPGA. Since the ECC circuit 7 is a known technique, detailed operation is not described here.

  FIG. 7 shows an example in which an ECC circuit (Decoder) 7 capable of correcting a 1-bit signal error for each word line is added to the output side of the RAM 4. In this case, 1-bit error correction of the RAM 4 becomes possible.

  FIG. 8 shows an example in which when the 1-bit correction is performed by the ECC circuit (Decoder) 7 as the error correction means, the corrected value is written again into the ROM 1 by the ECC circuit (Encoder) 8 as the correction value writing means. When a 1-bit error occurs due to a soft error, etc., if the error is left as it is, another 1-bit error may occur on the same Word line. In this case, a 2-bit error occurs in total, and the ECC circuit cannot be corrected. As a result, the device malfunctions. This measure can avoid such a problem.

  FIG. 9 is a time chart for explaining the operation of FIG. The description will be made assuming that a 1-bit error has occurred in Data_No = 4. Since the error No. 4 is corrected in the ECC circuit (Decoder) 7, the error-free value is obtained at the stage of output from the ECC circuit (Decoder) 7. Using the corrected value, the ECC circuit (Encoder) 8 calculates the ECC code again and writes it in the ROM 1 (it can be written because it is composed of a RAM with an initial value).

  Next, a case where it is assumed that a 1-bit error has occurred in ECC_No = 7 will be described. The error of ECC_No = 7 does not affect the data output of the ECC circuit (Decoder) 7, but is not output from the ECC circuit 7, so the ECC circuit (Encoder) 8 calculates the ECC code again and ROM1 (with initial value) It is possible to set to a state in which no error exists in both the Data and the ECC code.

  FIG. 10 shows another embodiment of FIG. An ECC circuit (Decoder) 7 is added with a function of writing a correction value of an ECC bit. Compared with FIG. 8, an ECC circuit (Encoder) 8 is not required separately, so that the circuit is simplified.

  As described above, in the second embodiment of the present invention, even when the stability of the clock to be used is not ensured, the ROM value can be prevented from being broken, and as a result, it can be prevented from developing into a device failure. In addition, since the stability of the clock to be used is confirmed, there is no need for long-term aging in a bad environment at the time of evaluation, and the development period can be shortened. Furthermore, it is not necessary to implement a ROM with an LUT, and an FPGA LUT resource can be allocated to a user circuit, thereby preventing a decrease in the LUT allocated to the user circuit. Furthermore, by using an ECC circuit, it is possible to prevent a 2-bit error from being developed due to a soft error or the like and to correct the bit error.

  Moreover, although a part or all of said embodiment can be described also as the following additional remarks, it is not restricted to the following.

Appendix (Appendix 1)
First storage means for reading data corresponding to a read address corresponding to the first clock;
The data read from the first storage means corresponding to the write address corresponding to the first clock is written, and the written data corresponding to the read address corresponding to the second clock Second storage means from which are read,
Confirm stabilization of the first clock,
When the first clock is not stabilized, the read address of the first storage means is fixed to a fixed value,
When the first clock is stabilized, the read address corresponding to the first clock is generated in the first storage means, and the first clock is corresponding to the first clock. Generating the write address;
And an address generation means.
(Appendix 2)
The write address of the second storage means and the read address of the second storage means are the same, and the write address write operation and the read address read operation have the same time The semiconductor memory device according to appendix 1, further comprising: an address arbitration unit that stops the generation of the address by the address generation unit when it is set to operate.
(Appendix 3)
Generating the first clock, supplying the first clock to the first storage means, the second storage means, the address generation means, and the address arbitration means; 3. The semiconductor memory device according to claim 1, further comprising clock generation means for supplying a signal for the address generation means to confirm the stabilization of the clock of 1.
(Appendix 4)
4. The semiconductor memory device according to any one of appendices 1 to 3, wherein the first storage unit includes a RAM with an initial value.
(Appendix 5)
The semiconductor storage device according to any one of appendices 1 to 4, wherein the second storage unit is a RAM.
(Appendix 6)
6. The semiconductor memory device according to any one of appendices 1 to 5, wherein the clock generation means is a phase locked loop (PLL).
(Appendix 7)
Any one of appendices 1 to 6, further comprising error correction means for correcting an error of the data read from the first storage means or the data read from the second storage means. The semiconductor memory device described.
(Appendix 8)
The semiconductor memory device according to appendix 7, further comprising correction value writing means for writing the error-corrected data to the first storage means.
(Appendix 9)
9. The semiconductor memory device according to any one of appendices 1 to 8, further comprising a circuit that reads out the data written in the second storage means by the second clock and performs a desired operation.
(Appendix 10)
The data stored in the first storage means is written to the second storage means by the first clock, and the data is read from the second storage means to the circuit that performs a desired operation by the second clock. A method for controlling a semiconductor memory device, comprising:
A confirmation step for confirming stabilization of the first clock;
When the first clock is not stabilized, the read address of the first storage means is fixed to a fixed value, and when the first clock is stabilized, it corresponds to the first clock. Generating a read address in the first storage means and a write address in the second storage means;
A write step of reading the data stored in the first storage means by the read address and writing the read data to the second storage means by the write address;
A method of controlling a semiconductor memory device, comprising: a reading step of reading the data written in the second memory means to the circuit by the second clock.
(Appendix 11)
The write address of the second storage unit and the read address of the second storage unit are the same, and the write address write operation and the read address read operation are the same time operation 11. The method of controlling a semiconductor memory device according to appendix 10, further comprising an arbitration step of stopping the generation step when set to be.
(Appendix 12)
12. The method of controlling a semiconductor memory device according to any one of appendices 10 to 11, wherein the writing step is performed when the reading step is not performed.
(Appendix 13)
Any one of appendices 10 to 11, wherein when the reading step is being performed, the writing step is performed at the write address of the second storage unit different from the read address of the second storage unit. A method of controlling the semiconductor memory device according to claim.
(Appendix 14)
14. The method of controlling a semiconductor memory device according to any one of appendices 10 to 13, wherein the writing step writes the data all at once.
(Appendix 15)
14. The method of controlling a semiconductor memory device according to any one of appendices 10 to 13, wherein the writing step writes the data divided into a plurality of times.
(Appendix 16)
16. The supplementary note 11 to 15, further comprising a correction step of correcting an error of the data read from the first storage means or the data read from the second storage means. Semiconductor memory device.
(Appendix 17)
The semiconductor memory device according to appendix 16, further comprising a correction value writing step of writing the data with the error corrected to the first storage means.

1 ROM
2 PLL
3 Address counter 4 RAM
5 Address Arbitration Unit 6 User Circuit 7 ECC Circuit (Decoder)
8 ECC circuit (Encoder)
10 FPGA

Claims (10)

First storage means for reading data corresponding to a read address corresponding to the first clock;
The data read from the first storage means corresponding to the write address corresponding to the first clock is written, and the written data corresponding to the read address corresponding to the second clock Second storage means from which are read,
Confirm stabilization of the first clock,
When the first clock is not stabilized, the read address of the first storage means is fixed to a fixed value,
When the first clock is stabilized, the read address corresponding to the first clock is generated in the first storage means, and the first clock is corresponding to the first clock. Generating the write address;
And an address generation means.   The write address of the second storage means and the read address of the second storage means are the same, and the write address write operation and the read address read operation have the same time 2. The semiconductor memory device according to claim 1, further comprising address arbitration means for stopping generation of said address by said address generation means when set to be operated.   Generating the first clock, supplying the first clock to the first storage means, the second storage means, the address generation means, and the address arbitration means; 3. The semiconductor memory device according to claim 1, further comprising clock generation means for supplying a signal for the address generation means to confirm the stabilization of one clock.   4. The semiconductor memory device according to claim 1, wherein the first storage means is a RAM with an initial value. 5.   5. The semiconductor memory device according to claim 1, wherein the clock generation means is formed of a phase locked loop (PLL). 6.   6. The apparatus according to claim 1, further comprising an error correction unit that corrects an error of the data read from the first storage unit or the data read from the second storage unit. A semiconductor memory device according to item. The data stored in the first storage means is written to the second storage means by the first clock, and the data is read from the second storage means to the circuit that performs a desired operation by the second clock. A method for controlling a semiconductor memory device, comprising:
A confirmation step for confirming stabilization of the first clock;
When the first clock is not stabilized, the read address of the first storage means is fixed to a fixed value, and when the first clock is stabilized, it corresponds to the first clock. Generating a read address in the first storage means and a write address in the second storage means;
A write step of reading the data stored in the first storage means by the read address and writing the read data to the second storage means by the write address;
A method of controlling a semiconductor memory device, comprising: a reading step of reading the data written in the second memory means to the circuit by the second clock.   The write address of the second storage unit and the read address of the second storage unit are the same, and the write address write operation and the read address read operation are the same time operation The method of controlling a semiconductor memory device according to claim 7, further comprising an arbitration step of stopping the generation step when set to be.   The method of controlling a semiconductor memory device according to claim 7, wherein the writing step is performed when the reading step is not performed.   9. The write process according to claim 7, wherein the write process is performed at the write address of the second storage unit different from the read address of the second storage unit when the read process is being performed. A method for controlling a semiconductor memory device according to the item.

Images