JP2003050748A - Buffer memory circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a buffer memory circuit, capable of minimizing malfunction time due to temporary noise, etc., and being automatically restored so as not to exert adverse effects on communications afterwards. SOLUTION: Data quantity in a dual port memory 1 is detected with an address difference detecting part 60 and a buffer capacity monitoring part 61, and the malfunctions of a write address and a read address are detected by comparing the pieces of data quantity with an address control operation comparing part 7. In addition, the malfunctions of the write address and the read address which cannot be detected with an address control part 6 are detected using a parity generating part 3, by adding a parity shifted by one address from write data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a buffer memory circuit used in a communication system or the like.

[0002]

2. Description of the Related Art FIG. 10 is a block diagram showing a conventional buffer memory circuit. The buffer memory circuit 701 once writes the transmission data to the dual port memory 702, notifies the transmission control unit 703 of the written data size by the transmission data size notification, and requests the transmission. The transmission control unit 703 sends a transmission timing signal to the read side address counter 704 after controlling the transmission line. The read side address counter 704 performs data transmission by reading the data of the requested transmission data size from the dual port memory 702 according to this transmission timing signal and passing it to the transmission control unit 703. 70
Reference numeral 5 is a write side address counter, 706 is a data size counter & holding circuit, and 707 is a transmission data generator.

[0003]

In the conventional buffer memory circuit, when the read side address counter of the dual port memory malfunctions due to temporary noise from the outside, the write side notifies the read side only of the read data size. Therefore, the address where the data is written and the address where the data is read do not match. When this malfunction occurs, the malfunction continues endlessly. As a result, using this transmission buffer circuit, DHL
Even if a block of data such as C is transmitted, data at an address different from the address written in the dual port memory is read, so that all packets will be in error on the receiving side after the transmission buffer circuit. There was a flaw. Further, since the malfunction cannot be self-recovered, there is a problem that the malfunction due to the temporary noise causes all the communication to be an error although there is no noise thereafter.

The present invention has been made in view of the above conventional problems, and an object thereof is to minimize a malfunction time due to a temporary noise or the like so as not to adversely affect communication thereafter. Another object of the present invention is to provide a buffer memory circuit capable of self-recovery.

[0005]

In order to achieve the above object, the present invention writes write data in a dual port memory in synchronization with a write clock, and synchronizes in a dual port memory with a read clock different from the write clock. In a buffer memory circuit for reading data from a memory, a means for performing a parity operation on the write data and adding the obtained vertical parity to the write data, and a parity operation for the data shifted by one address from the write data, The write data includes a means for adding a parity shifted by one address to the write data, a vertical parity created from the data read from the dual port memory, and the created parity and the vertical parity included in the read data. Means for comparing and the reading A means for creating a parity shifted by one address from data and comparing the created parity with a parity shifted by one address included in the read data is the same as the vertical parity, and the parity shifted by one address does not match. And a means for detecting a malfunction of the write address and the read address.

To achieve the above object, the present invention writes write data to a dual port in synchronization with a write clock, and reads data from the dual port memory in synchronization with a read clock different from the write clock. In the buffer memory circuit,
The dual port memory includes means for calculating a data amount of the dual port memory from a difference between a write address and a read address, and means for outputting a write address value when the write address changes, based on the write address value and the read address value. Means for monitoring the data amount of the port memory, and means for detecting a malfunction of the write address and the read address by comparing the data amount obtained by the data amount calculating means with the data amount obtained by the monitoring means. It is characterized by having.

[0007]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(First Embodiment) FIG. 1 is a block diagram showing a configuration of a buffer memory circuit according to a first embodiment of the present invention. In FIG. 1, reference numeral 1 is a dual port memory 1 for storing data, 2 is a write control unit for generating a write address 14 by a write clock 12, and 3 is a parity generation for generating a parity to be added to write data to the dual port memory 1. Reference numeral 4 denotes a parity collating unit that collates the parity of data read from the dual port memory 1, and 5 a read control unit that generates a read address 16 for the dual port memory 1 by a read clock 18.

Further, 61 is a buffer storage capacity monitoring unit for monitoring the data storage amount in the dual port memory 1 based on the write address 14 and the read address 16 as will be described later, and 60 is the difference between the write address 14 and the read address 16. Is an address difference detection unit that calculates the data storage amount in the dual port memory 1.

Further, 7 is a memory calculated by the address difference detection unit 60 in order to generate a reset signal for detecting a malfunction of the write control unit 2, the read control unit 5, and the address control unit 6 or performing a recovery operation. An address control operation comparison unit that compares the data storage amount 19 in 1 with the data storage amount 20 in the memory 1 monitored by the buffer storage capacity monitoring unit 61. Reference numeral 8 indicates a parity error when this comparison result does not match or a malfunction error monitoring parity error. 22 is a malfunction recovery unit that generates a reset signal when 22 occurs.

Next, the operation of this embodiment will be described with reference to FIGS. FIG. 2 is a block diagram showing a configuration example of the parity adding unit 3. The parity adding unit 3 generates a parity so that a malfunction of a write address and a read address that cannot be detected by the address control unit 6 can be detected. FIG. 3 shows an example of writing data to the dual port memory 1. If the data to be written in the dual port memory 1 is, for example, 8 bits (7th to 0th bits), vertical parity (8th bit) for monitoring for each address of the dual port memory 1 is created by the parity generation unit 300, and noise etc. The parity (9th bit) shifted by one address from the data to be written for malfunction monitoring is generated by the register 301 and written in the dual port memory 1.

Specifically, for example, as shown in FIG.
Taking the data of the +1 address as an example, a parity operation is performed on the 0 + 1 to 7-bit data of the n + 1 address, and the result is written in the 8th bit as vertical parity. In addition, a parity operation is performed on the 0 to 8 bit data of the n address immediately before the n + 1 address, and the result is 9
Write in the bit. This is parity to which data to be written is shifted by one address.

In such a method, for example, when a malfunction occurs such that the read address 16 jumps from "5" to "6" due to noise or the like to "7", the parity check unit 4 uses the dual port. As a result of the parity collation for the data 15 read from the memory 1, the vertical parity written in the 8th bit of the dual port memory 1 cannot detect the error. However, since the parity shifted by one address from the data is written at the 9th bit of the dual port memory 1, an error can be detected even with respect to an address jump malfunction.

FIG. 4 is a block diagram showing an example of the configuration of the parity collation unit 4. The parity generation unit 4 generates the parity 400 from the data 15 read from the dual port memory 1. This performs a parity operation on 0 to 7 bits of data 15 and outputs the result as parity 400. The coincidence detection unit 41 compares the parity 400 with the vertical parity included in the data 15 read from the dual port memory 1 to perform coincidence detection.

On the other hand, the register 43 generates the parity 403 which is shifted by one address from the data. The parity error detection unit 44 compares the parity 403 with the parity included in the read data 15 (the parity of the 9th bit in the example of FIG. 3) to perform coincidence detection. If the two parities do not match, a parity error alarm is output to the malfunction recovery unit 22. However, the parity error detection unit 44 uses the register 42 indicating the vertical parity error.
When the parity error is detected when the output 402 of “1” is “1”, the counter does not malfunction due to noise or the like, and therefore the malfunction monitoring parity error alarm 22 is not output.

FIG. 5 is a block diagram showing a configuration example of the address difference detection unit 60. This example shows write clock 1
This makes it possible to detect the address difference even when 2 and the read clock 18 are asynchronous. Since the write clock 12 and the read clock 18 are asynchronous, it is necessary to convert the write address 14 into a signal synchronized with the read clock 18 in order to detect the address difference in the address difference detection unit 605.

At this time, the write address 14 is changed to the gray code 100 by the binary → gray code conversion unit 600.
And the gray code 101 hit with the write clock 12 in the register 601 is hit with the register 602 (hit in the opposite phase of the read clock 18 to obtain the output 102), and hit with the read clock 18 in the register 603 to obtain the read clock 18. The Gray code 103 of the synchronized write side address 14 is obtained. The gray → binary code conversion unit 604 outputs the binary data 104, and the address difference detection unit 605 outputs the data accumulation amount 19 in the dual port memory 1 from the binary data 104 and the read address 16.

FIG. 6 shows a binary in the case of 4-bit data.
A configuration example of the Gray code conversion unit 600 and the Gray-> binary code conversion unit 604 is shown. FIG. 6B is a circuit diagram showing an example of the binary-> Gray code conversion unit 600, and FIG. 6C is an example of a Gray-> Binary code conversion unit 604, each of which is configured using an exclusive OR circuit. Note that FIG.
(A) shows correspondence between a decimal number, a binary number, and a Gray code.

FIG. 7 is a block diagram showing an example of the structure of the buffer storage capacity monitor 61. The register 610 holds the write address 14 at the rising edge of the read clock 18 and outputs it as output data 200 to the address conversion unit 611 and the register 612. The address conversion unit 611 outputs a value obtained by subtracting “−1” from the output data 200 of the register 610 (however, when the output data 200 is “0”, the maximum accumulated value of the dual port memory 1 is taken) to the address match detection unit 613. To do.

The address match detection unit 613 detects the match between the output data 201 of the address conversion unit 611 and the output data 202 of the register 612. When the match is detected, the output data 203 outputs "1", and when there is no match, "1" is output. 0 "is output. When the output data 203 of the address coincidence detection unit 613 is “1”, the register 612 holds the output data 200 of the register 610 at the read clock 18 and outputs the register output 202 to the address difference detection unit 614.
When the output data 203 is "0", the previous value is held. The address difference detection unit 614 reads the read counter value 1
6 and the register output 202, the difference value 204 is output to the register 615. The register 615 synchronizes the output data 204 of the address difference detection unit 614 with the read clock 18 and stores the data storage amount 2 in the dual port memory 1.
Outputs 0.

The address control operation comparison unit 7 compares the two data amounts detected in the blocks of the address difference detection unit 60 and the buffer storage capacity monitoring unit 61, and when they do not match, the write control unit 2 and the read control unit 5 Also, the malfunction of the buffer storage capacity monitoring unit 61 is detected, and the address malfunction alarm 21 is output to the malfunction recovery unit 8. When the malfunction recovery unit 8 detects the address malfunction alarm 21 and the parity error alarm 22 from the parity collation unit 4, it inputs the reset signal 23 to the write control unit 2, the read control unit 5 and the address control unit 6. Perform recovery operation.

Here, the writing of data is controlled by the valid data control signal 11, and when the writing of data is instructed by the valid data control signal 11, the write data 10 is written.
As described with reference to FIG. 3, parity is added by the parity adding unit 3 and written in the dual port memory 1. At this time, the write controller 2 generates a write address from the write clock 12, and the write data is sequentially written to the write address generated in synchronization with the write clock 12.

On the other hand, when reading data, a read request signal is input to the read control unit 5, and the read control unit 5
Then, the read address is generated by the read clock. Data is read from the dual port memory 1 according to the read address in synchronization with the read clock. When writing data or reading data, the parity collation unit 4 collates the parity as described above, and outputs a parity error alarm to the malfunction recovery unit 22 when a mismatch of the parity is detected. Further, the address control operation comparison unit 7 compares the data amounts detected by the address difference detection unit 60 and the buffer storage capacity monitoring unit 61,
When the two data amounts do not match, an address malfunction alarm is output to the malfunction recovery unit 22. When the malfunction recovery unit 22 receives a parity error warning or an address malfunction warning, the malfunction recovery unit 22 writes a reset signal to the write control unit 2, the read unit 5,
The address is input to the address control unit 6 to restore it.

(Second Embodiment) FIG. 8 is a block diagram showing the configuration of a second embodiment of the buffer memory circuit of the present invention. In FIG. 8, the same parts as those in FIG. In the present embodiment, ATM (Asyn
ATM cell demultiplexing processing and CLA used for chronous transfer mode transmission
D (Cell Assembly And Disas)
It shows a buffer memory circuit suitable for ATM transmission used for de-cellization processing of "sembly)".

In the ATM transmission device, the HEC byte normally contained in the ATM cell header is subjected to cell synchronization processing with respect to the ATM cell received at the input / output end of the device to terminate the HEC byte. In addition, a cyclic redundancy (CRC) operation is performed on the first 4 bytes of the header of the output ATM cell, and the result is added as an HEC byte. Therefore, in the ATM device, A
It is possible to freely use the HEC byte area of the TM cell.

Referring to FIG. 8, in order to monitor the operation of the dual port memory 1 at the input stage to the parity addition unit 3,
SN (Sequence Number) in EHC byte
The HEC overwrite unit 500 having a function of embedding r) is provided, the parity is added to the output data 501 of the HEC overwrite unit 500 by the parity adding unit 3, and the dual port memory 1 is written.

On the read side of the dual port memory 1, the HE for detecting an SN number error (error in which the SN order is out of order) is read from the read ATM cell data.
A C matching unit 502 is provided. HEC matching unit 502
Detects an SN number error, SN number error warning 5
03 is input to the malfunction recovery unit 22, and the write control unit 2,
The recovery operation of the read control unit 5 and the buffer storage capacity monitoring unit 61 is performed. Other configurations are the same as those in FIG.

FIG. 9 shows an ATM cell format input to the ATM transmission buffer memory. This ATM cell is composed of a 5-byte head and a 48-byte payload information field. The first byte of the header is a VPI (Virtual Path Id).
2nd byte is VPI and VCI
(Virtual Channel Identity
er) 3rd byte is VCI, 4th byte is VCI, P
T (Payload Type) and CLP (Cel
l Loss Priority) The 5th byte is HE
C is assigned.

[0029]

As described above, according to the present invention, by adding the parity shifted by one address to the write data, it is possible to detect the malfunction of the write address and the read address which cannot be detected by the address controller. Further, by detecting the data amount of the dual port memory in two blocks and comparing the data amounts of the two blocks, it is possible to detect the malfunction of the write control unit and the read control unit. Therefore, even if the write clock and the read clock are asynchronous, the malfunction time due to a temporary noise or the like can be minimized, and the self-recovery can be performed without adversely affecting the communication thereafter. .

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a buffer memory circuit of the present invention.

FIG. 2 is a block diagram showing an example of a parity addition unit in FIG.

FIG. 3 is a diagram illustrating an example of writing data to the dual port memory in FIG.

FIG. 4 is a block diagram showing an example of a parity matching unit in FIG.

5 is a block diagram showing an example of an address difference detection unit in FIG.

6 is a circuit diagram showing an example of a binary → gray conversion unit and a gray → binary conversion unit of FIG. 5;

FIG. 7 is a block diagram showing an example of a buffer storage capacity monitoring unit in FIG.

FIG. 8 is a block diagram showing a second embodiment of the present invention.

FIG. 9 is an AT input to an ATM transmission buffer memory
It is a figure which shows an M cell format.

FIG. 10 is a block diagram showing a conventional buffer memory circuit.

[Explanation of symbols]

1 dual port memory 2 Write control unit 3 Parity adder 4 Parity check unit 5 Read controller 6 Address control section 7 Address control operation comparison unit 8 Malfunction recovery section 60 Address difference detector 61 Buffer storage capacity monitor 500 HEC overwrite section 502 HEC collator

Claims (8)

[Claims] 1. A buffer memory circuit for writing write data to a dual-port memory in synchronization with a write clock and reading data from the dual-port memory in synchronization with a read clock different from the write clock. A means for performing a parity operation and adding the obtained vertical parity to the write data, and a parity operation are performed on the data that is one address away from the write data, and the write data is 1
Means for adding parity shifted in address to write data, means for creating vertical parity from the data read from the dual port memory, and means for comparing the created parity with the vertical parity included in the read data, A parity that shifts one address from the read data, compares the generated parity with a parity that is shifted by one address included in the read data, and the parity that matches the vertical parity and shifts one address. And a means for detecting an erroneous operation of a write address and a read address when the two do not match. 2. The buffer memory circuit according to claim 1, wherein the detection unit resets a write control unit that creates a write address and a read control unit that creates a read address when a malfunction is detected. . 3. An HEC overwrite unit for writing SN in an HEC byte included in an ATM cell header, and means for detecting an SN number error from ATM cell data read from the dual port memory. The buffer memory circuit according to claim 1, wherein the buffer memory circuit is a buffer memory circuit. 4. The SN number error detection means resets a write control unit that creates a write address and a read control that creates a read address when an SN number error is detected. Buffer memory circuit. 5. A buffer memory circuit for writing write data to a dual port in synchronism with a write clock and reading data from the dual port memory in synchronism with a read clock different from the write clock. The data amount of the dual port memory is calculated based on the write address value and the read address value, including means for calculating the data amount of the dual port memory from the difference and means for outputting the write address value when the write address changes. And a means for detecting a malfunction of the write address and the read address by comparing the data amount obtained by the data amount calculating means with the data amount obtained by the monitoring means. Buffalo Mori circuit. 6. The detection unit resets a write control unit that creates a write address and a read control unit that creates a read address when a malfunction of a write address and a read address is detected. The buffer memory circuit described in 1. 7. An HEC overwrite unit for writing SN in an HEC byte included in an ATM cell header, and means for detecting an SN number error from ATM cell data read from the dual port memory. The buffer memory circuit according to claim 5, wherein the buffer memory circuit is a buffer memory circuit. 8. The SN number error detection means resets a write control unit for creating a write address and a read control for creating a read address when an SN number error is detected. Buffer memory circuit.