CN101145117B - Method and apparatus for treating error detection - Google Patents
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Abstract
The implementation of the invention discloses a detecting processing method which includes the steps as follows: the detecting information of the sampling information is to be acquired; having acquired through sampling the transmitted information, the sampling information can produce the detecting information of the sampling information; the acquired detecting information can be compared with the produced detecting information to see whether the acquired detecting information is equal to the produced detecting information; otherwise, the sampling information is judged to be wrong. Correspondingly, the implementation of the invention also provides a detecting processing device, and is characterized in that the device comprises a detecting information unit which is used to acquire the detecting information of the sampling information, a sampling processing unit which is used to sample the transmitted information to acquire the sampling information, and then to produce the detecting information of the sampling information, and a comparison unit which can be used to compare the acquired detecting information with the produced detecting information to see whether the acquired detecting information is equal to the produced detecting information; otherwise, the sampling information is judged to be wrong. The technical proposal of the implementation of the invention can detect whether the sampling information is wrong.
Description
Technical field
The present invention relates to technical field of data processing, be specifically related to a kind of error detection disposal route and device.
Background technology
In present chip design, have a plurality of clock zone coexistences in the same chip, in this case, the situation that data message switches between different clock-domains usually appears.At present, utilize pushup storage FIFO to handle usually.
FIFO is a kind of general memory buffer, and it writes and read the cardinal rule of following first-in first-out.Seeing also Fig. 1, is that prior art utilizes FIFO to carry out the synoptic diagram of processing data information.As shown in Figure 1, FIFO links to each other with two clock zones respectively, and one for writing clock zone (wr_clk), and one for reading clock zone (rd_clk), and both are asynchronous clock domain.Writing clock zone, write data bits (wr_data) whenever writes data, and the write address of write address position (wr_addr) adds 1; Reading clock zone, read data bit (rd_data) is whenever read data, reads address bit (rd_addr) and reads the address and add 1.When the address to going up in limited time, the address returns zero.All be provided with address comparator at two clock zones, judge that by comparing read/write address the sky of FIFO is full, when reading to be sky, the empty sign of generation when the address catch up with write address; When write address catch up with when reading the address to full, produce full scale will.If FIFO is empty, next read operation will be read in invalid data, if FIFO is for full, next write operation will cover useful data.Therefore, after producing empty full scale will, FIFO controls read-write operation according to empty full scale will by controller, can not carry out read operation when being sky, can not carry out write operation when full, makes mistakes to prevent to read and write data.
Relatively need therefore the address transfer of a clock zone need being compared to the another one clock zone of general read/write address at same clock zone.When clock zone switches, for reducing owing to set up the retention time and do not satisfy the sampling error in address that the metastable state that causes may cause and finally cause the address relatively to obtain judging by accident result's risk, usually adopt in a clock zone and to be transferred to another clock zone again after converting binary address to the Gray code address, after the Gray code address sampling of another clock zone to transmission, convert the method that the address of binary address and this clock zone compares again to.Because the Gray code address behind the employing gray encoding has the advantages that to have only one digit number to change according to line between the neighbor address, even address sample error so also only can make one of error in address skew, thereby reduce the erroneous judgement risk of address comparison.For example: the address is that 3 and 4 Gray code is respectively 010 and 110.If the address is 4 o'clock sample error, the form of mistake can only be 010 (promptly still original address is 3), and can not be other addresses.
In research and practice process to prior art, the inventor finds that there is following problem in prior art:
Though adopting the Gray code address to compare, prior art can reduce address erroneous judgement risk relatively, but when the sampling address when making a mistake because can not detect, therefore still exist because the erroneous judgement result that the sampling error in address causes might cause the mistake that reads and writes data and judge the result by accident.For example original read/write address should take place empty full when equating, but because sample error erroneous judgement in address is unequal for read/write address, and then was judged as and takes place empty fullly, caused empty full signal not produce, and made mistakes thereby make to read and write data.For example, suppose that read/write address is being coincidence in 4 o'clock, and empty full alarm will take place, 4 Gray code is 110, but because the address sample error, the sampling address is 3, and corresponding Gray code is 010, with the address of this clock zone is 4 to compare that to be judged as the address unequal, empty full alarm does not then take place this moment, and next clock period is read the address or write address changes into 5 temporarily by the time,, corresponding Gray code is 111.At this moment, because read/write address is no longer equal, can not produce empty full alarm, therefore can not trigger the FIFO controlling mechanism and need to wait for the arrival of correct empty full address next time, the data that write so and during this period of time can cover the data of not reading as yet or read the data of already reading, and cause the sense data mistake.
Summary of the invention
The technical matters that the embodiment of the invention will solve provides a kind of error detection disposal route, can detect whether mistake of sample information.
For solving the problems of the technologies described above, embodiment provided by the present invention is achieved through the following technical solutions:
The embodiment of the invention provides a kind of error detection disposal route, comprising: after finishing initial verification and being provided with, corresponding check information is obtained the check information of this sample information when receiving end B clock zone was sampled according to last time; Described initial verification setting comprises: at transmitting terminal A clock zone the data message that a preparation is transferred to the B clock zone is set, generate the data message corresponding check information that described preparation is transmitted at the B clock zone according to the data message of described preparation transmission and according to selected redundancy encoding technology, this check information is initial check information; Information transmitted is sampled, obtain generating after the sample information check information of described sample information; Described information transmitted is sampled, the check information that obtains generating after the sample information described sample information comprises: at the B clock zone data message of transmission is sampled, obtain generating according to described redundancy encoding technology after the sample information check information of described sample information; Described information transmitted is the information after encoding, and the rule of described coding is that adjacent data has only a bit to change; The check information of described check information that obtains and described generation is compared,, then judge the sample information mistake if unequal.
The embodiment of the invention provides a kind of error detection treating apparatus, comprising: the check information unit, be used for after finishing initial verification and being provided with, and corresponding check information is obtained the check information of this sample information when receiving end B clock zone was sampled according to last time; Described initial verification setting comprises: at transmitting terminal A clock zone the data message that a preparation is transferred to the B clock zone is set, generate the data message corresponding check information that described preparation is transmitted at the B clock zone according to the data message of described preparation transmission and according to selected redundancy encoding technology, this check information is initial check information; Sample processing unit is used for information transmitted is sampled, and obtains generating after the sample information check information of described sample information; Described information transmitted is sampled, the check information that obtains generating after the sample information described sample information comprises: at the B clock zone data message of transmission is sampled, obtain generating according to described redundancy encoding technology after the sample information check information of described sample information; Described information transmitted is the information after encoding, and the rule of described coding is that adjacent data has only a bit to change; Comparing unit is used for the check information that check information that described check information unit is obtained and described sample processing unit generate and compares, if unequal, then judges the sample information mistake.
As shown from the above technical solution, the embodiment of the invention is by obtaining the check information of this sample information in advance, the sample information that sampling is obtained generates check information again, check information according to described check information that obtains and described generation compares, just judge the sample information mistake when comparing when unequal, thereby can detect whether mistake of sample information.
Description of drawings
Fig. 1 is that prior art utilizes FIFO to carry out the synoptic diagram of processing data information;
Fig. 2 is embodiment of the invention error detection process flow figure;
Fig. 3 is first embodiment of the invention error detection process flow figure;
Fig. 4 is second embodiment of the invention error detection process flow figure;
Fig. 5 is an embodiment of the invention error detection treating apparatus structural representation.
Embodiment
The embodiment of the invention provides a kind of error detection disposal route, and whether be used to detect sample information correct.
Mentioned in the prior art and adopted the Gray code address, for example the Gray code of address 0～7 corresponds to respectively: 000; 001; 011; 010; 110; 111; 101; 100.Can find that the Changing Pattern of Gray code address is that a next address and a last address have only a bit to change.For example change to 011 from 001,, when asynchronous clock is sampled, set up the retention time can access absolute assurance because other bits can not change, thus can sample error, unique possible mistake be exactly that intermediate bit changes to 1 from 0.Because there is the factor of not stationary state to exist, the value that intermediate bit samples out may be 0, also may be 1, but only may be both of these case.When middle bit sample is 0, finally be 001, the address value mistake when middle bit sample is 1, is 011 finally, address value is correct, in addition can not be other sampled values.As for other address change also is the same.Therefore can find: 1) when the information that adopts Gray code to carry out asynchronous clock domain is switched, the total correctness of information in the time of can't guaranteeing to switch; 2) when intelligence sample is made mistakes, show as information with last time information identical, can not change, for example the last time is 001, should be 011 specifically, but because sample error, remains 001, and is the same with last information.
According to above-mentioned analysis, if when carrying out the information switching of asynchronous clock domain, clock zone after switching obtains a check information in advance, can carry out error detection to the information after switching according to this check information, when information after finding switching and expection were not inconsistent, the information that just can detect made a mistake when asynchronous clock domain switches.
Therefore, the embodiment of the invention is obtained the check information of the information that is about to sampling in advance, the information that the transmits back of sampling is generated the check information of this sample information according to identical redundancy encoding technology, check information that obtains in advance and the check information that generates according to sample information are compared, if result relatively is unequal, think that then sampling makes mistakes report and alarm, and can further revising, thereby the information of realization EDC error detection and correction to sampled result.
Seeing also Fig. 2, is embodiment of the invention error detection process flow figure, comprises step:
Step 201, obtain the check information of this sample information;
When system is carried out initial setting up, can carry out the initialization of check information, for example the data message that a preparation is transferred to the B clock zone is set at A clock zone (read clock zone or write clock zone), generate its corresponding check information at the B clock zone according to the data message of described preparation transmission and according to selected redundancy encoding technology, this check information is initial check information.Because redundancy encoding has specific rule, therefore can infer according to this initial check information next check information, promptly infer the data message of next time sampling should corresponding check information, by that analogy.Here said redundancy encoding technology for example can be but is not limited to parity checking or CRC check (cyclic redundancy check (CRC)) etc.
With the B clock zone data message that the A clock zone transmits is sampled as example, when this sampling is about to take place, the check information when corresponding check information obtains this sampling when sampling according to last time.
Step 202, information transmitted is sampled, obtain generating after the sample information check information of described sample information;
The A clock zone, is sampled to the data message of transmission at the B clock zone to B clock zone transmitting data information.In FIFO, the data message after the data message of described transmission is generally and encodes, in order to reduce misfeed, described encoding law is generally adjacent data and has only a bit to change.For example adopt gray encoding.
After obtaining sample information when sampling, generate the check information of described sample information according to selected redundancy encoding technology, the redundancy encoding technology for example can be but be not limited to parity checking or CRC check (cyclic redundancy check (CRC)) etc., but should adopt same coding techniques with the check information in the above-mentioned steps.
Need to prove that information transmitted described here can be the data of data bit input among the FIFO, also can be the address of address bit input.
Step 203, the check information of described check information that obtains and described generation is compared,, then judge the sample information mistake if unequal;
After obtaining sample information and generating the check information of described sample information according to selected redundancy encoding technology, the check information of described check information that obtains and described generation is compared, the described check information that obtains is that the information of this sampling of prediction should corresponding check information, so, if comparative result is inequality for both, the information of then judging this sampling is wrong information, and transmission information sends misfeed, can be according to this judged result, report and alarm; If comparative result is identical for both, then sampling is correct.
Step 204, the sample information of mistake is made amendment.
After judging sample error, can utilize existing information to carry out error correction.When for example transmission information adopts gray encoding, sample information is added 1 be correct transmission information.If adopt other coding techniquess, also be to have only a bit to change but encoding law is an adjacent data, then also may be sample information is subtracted 1.In a word, according to the rule of the coding that is adopted, after checking out sample error, just can realize error correction.
Better understand embodiment of the invention technical scheme for convenient, below describe in detail further combined with concrete Application Example.
Seeing also Fig. 3, is first embodiment of the invention error detection process flow figure.Among this embodiment, suppose that transmission information is the address, gray encoding is adopted in the address, and check information is the even parity check sign indicating number.
After finishing initial verification and being provided with, the even parity check sign indicating number when the even parity check sign indicating number of correspondence obtained this sampling when the B clock zone was sampled according to last time.
Generally in Asynchronous Transfer Mode adopt even parity check, illustrate, the Gray code of address 0～7 is carried out even parity check respectively, can obtain check code and be respectively: 0 with address 0～7; 1; 0; 1; 0; 1; 0; 1.Can know that from check code the check code of next address is a last check code negate.So, on obtaining in the check code of a Gray code address, the precognition of negate at once obtains the prediction check code of next address, adopt this prediction check code when sampling in next Gray code address like this, because this prediction check code just generates during the Gray code address last once the sampling, therefore set up fully enough assurances of retention time.
Suppose that last time, the address was at 3 o'clock, Gray code is 010, and its check code is 1, and the prediction check code that then obtains next address after the negate and be the address of this sampling is 0.
The A clock zone is 4 to be Gray code address 110 to the address of B clock zone transmission, at the B clock zone is sampled in the transport address, generates the even parity check sign indicating number of described sampling address according to selected odd even coding techniques.
If the sampling address is 110, then the check code that this address is generated is 0, equates with the prediction check code 0 that obtains, and can judge the sampling address right thus; If the sampling address is for being 010, then the check code that this address is generated is 1, and is unequal with the prediction check code 0 that obtains, and can judge the sampling error in address thus.
After judging sample error, according to the Changing Pattern of Gray code address, the Gray code address that samples is added 1, be correct address.If adopt other coding techniquess, also be to have only a bit to change but encoding law is an adjacent data, then also may be sample information is subtracted 1.In a word, according to the rule of the coding that is adopted, after checking out sample error, can realize error correction.
After the sampling address of mistake is revised as correct address, just can carry out the address relatively by existing process.Because can guarantee that by above-mentioned steps only this address relatively is correct, therefore can overcome the erroneous judgement result who causes because of the sampling error in address, thereby can guarantee that follow-up reading and writing data do not make a mistake.
Seeing also Fig. 4, is second embodiment of the invention error detection process flow figure.The key distinction of this second embodiment and first embodiment is that check information adopts CRC check.
After finishing initial verification and being provided with, the CRC check sign indicating number when the CRC check sign indicating number of correspondence obtained this sampling when the B clock zone was sampled according to last time.
Illustrate with address 0～7, the Gray code of address 0～7 is carried out CRC check respectively, can obtain the CRC check sign indicating number of each address correspondence and store, for example store in the mode of table.So, can predict the prediction check code that obtains next address by tabling look-up, adopt this prediction check code when sampling in next Gray code address like this,, therefore set up fully enough assurances of retention time because this prediction check code just generates during the Gray code address last once the sampling.
Suppose that last time, the address was at 3 o'clock, Gray code is 010, carries out CRC check and obtains a check code, represents with alphabetical X, and can obtain next address after then tabling look-up is the prediction check code of the address of this sampling, represents with alphabetical Y.
The A clock zone is 4 to be Gray code address 110 to the address of B clock zone transmission, at the B clock zone is sampled in the transport address, generates the CRC check sign indicating number of described sampling address according to selected CRC coding techniques.
If the sampling address is 110, then the check code that this address is generated is Y, equates with the prediction check code Y that obtains, and can judge the sampling address right thus; If the sampling address is 010, then the check code that this address is generated is X, and is unequal with the prediction check code Y that obtains, and can judge the sampling error in address thus.
After judging sample error, according to the Changing Pattern of Gray code address, the Gray code address that samples is added 1, be correct address.If adopt other coding techniquess, also be to have only a bit to change but encoding law is an adjacent data, then also may be sample information is subtracted 1.In a word, according to the rule of the coding that is adopted, after checking out sample error, can realize error correction.
After the sampling address of mistake is revised as correct address, just can carry out the address relatively by existing process.Because can guarantee that by above-mentioned steps the address that compares is correct, therefore can overcome the erroneous judgement result who causes because of the sampling error in address, thereby can guarantee that follow-up reading and writing data do not make a mistake.
The above-mentioned error detection disposal route that describes the embodiment of the invention in detail, corresponding, the embodiment of the invention provides a kind of error detection treating apparatus.
Seeing also Fig. 5, is embodiment of the invention error detection treating apparatus structural representation.
As shown in Figure 5, the error detection treating apparatus comprises: check information unit 501, sample processing unit 502 and comparing unit 503.
Check information unit 501 is used to obtain the check information of this sample information.Described check information unit 501 after finishing initial verification and being provided with, the check information when corresponding check information obtains this sampling when sampling according to last time.
If the A clock zone is to B clock zone transmitting data information, at the B clock zone, the data message of 502 pairs of transmission of sample processing unit is sampled.In FIFO, the data message after the data message of described transmission is generally and encodes, in order to reduce misfeed, described encoding law is generally adjacent data and has only a bit to change.For example adopt gray encoding.After obtaining sample information when sampling, sample processing unit 502 generates the check information of described sample information according to selected redundancy encoding technology, the redundancy encoding technology for example can be but be not limited to parity checking or CRC check (cyclic redundancy check (CRC)) etc., but should adopt same coding techniques with the check information in the check information unit 501.Need to prove that information transmitted described here can be the data of data bit input among the FIFO, also can be the address etc. of address bit input.
Comparing unit 503 is used for the check information that check information that described check information unit 501 is obtained and described sample processing unit 502 generate and compares, if unequal, then judges the sample information mistake.For example transmission information is the Gray code address, and the check code that obtains is 0, if the sampling address is 110, then the check code that this address is generated is 0, equates with the check code 0 that obtains, and can judge the sampling address right thus; If the sampling address is 010, then the check code that this address is generated is 1, and is unequal with the check code 0 that obtains, and can judge the sampling error in address thus.
Describedly declare the error detection treating apparatus and further comprise: error correction unit 504 is used for after comparing unit 503 is judged the sample information mistake described sample information being made amendment.For example transmission information is the Gray code address, after judging sample error, according to the Changing Pattern of Gray code address, the Gray code address that samples is added 1, is correct address.If adopt other coding techniquess, also be to have only a bit to change but encoding law is an adjacent data, then also may be sample information is subtracted 1.In a word, according to the rule of the coding that is adopted, after checking out sample error, can realize error correction.
Because the error correction by error correction unit 504 can guarantee that the address of comparison is correct, therefore can overcome the erroneous judgement result that prior art causes because of the sampling error in address, thereby can guarantee that follow-up reading and writing data do not make a mistake.
In sum, the embodiment of the invention is by obtaining the check information of this sample information in advance, the sample information that sampling is obtained generates check information again, check information according to described check information that obtains and described generation compares, just judge the sample information mistake when comparing when unequal, thereby whether can detect sample information correct.
Further, embodiment of the invention technical scheme can be carried out error correction according to the Changing Pattern of sample information after judging the sample information mistake, thereby guarantees that sample information finally is correct.
Further, embodiment of the invention technical scheme can adopt different redundancy encoding technology to obtain check information, for example odd-even check and CRC check.In addition, sample information can be the address of address bit input, also can be other information, for example the data of data bit input etc.
More than a kind of error detection disposal route and device that the embodiment of the invention provided are described in detail, for one of ordinary skill in the art, thought according to the embodiment of the invention, part in specific embodiments and applications all can change, in sum, this description should not be construed as limitation of the present invention.
Claims (10)
1. an error detection disposal route is characterized in that, comprising:
After finishing initial verification and being provided with, corresponding check information is obtained the check information of this sample information when receiving end B clock zone was sampled according to last time; Described initial verification setting comprises: at transmitting terminal A clock zone the data message that a preparation is transferred to the B clock zone is set, generate the data message corresponding check information that described preparation is transmitted at the B clock zone according to the data message of described preparation transmission and according to selected redundancy encoding technology, this check information is initial check information;
Information transmitted is sampled, obtain generating after the sample information check information of described sample information; Described information transmitted is sampled, the check information that obtains generating after the sample information described sample information comprises: at the B clock zone data message of transmission is sampled, obtain generating according to described redundancy encoding technology after the sample information check information of described sample information; Described information transmitted is the information after encoding, and the rule of described coding is that adjacent data has only a bit to change;
The check information of described check information that obtains and described generation is compared,, then judge the sample information mistake if unequal.
2. error detection disposal route according to claim 1 is characterized in that, further comprises after the described judgement sample information mistake:
Described sample information is made amendment.
3. error detection disposal route according to claim 1 is characterized in that:
The described employing gray encoding that is encoded to.
4. error detection disposal route according to claim 1 and 2 is characterized in that:
Described information transmitted is the address of asynchronous clock domain.
5. error detection disposal route according to claim 1 and 2 is characterized in that:
Described check information generates according to parity checking or cyclic redundancy check (CRC).
6. error detection disposal route according to claim 2 is characterized in that, described described sample information is made amendment is specially:
When information transmitted adopts gray encoding, described sample information is added 1.
7. an error detection treating apparatus is characterized in that, comprising:
The check information unit is used for after finishing initial verification and being provided with, and corresponding check information is obtained the check information of this sample information when receiving end B clock zone was sampled according to last time; Described initial verification setting comprises: at transmitting terminal A clock zone the data message that a preparation is transferred to the B clock zone is set, generate the data message corresponding check information that described preparation is transmitted at the B clock zone according to the data message of described preparation transmission and according to selected redundancy encoding technology, this check information is initial check information;
Sample processing unit is used for information transmitted is sampled, and obtains generating after the sample information check information of described sample information; Described information transmitted is sampled, the check information that obtains generating after the sample information described sample information comprises: at the B clock zone data message of transmission is sampled, obtain generating according to described redundancy encoding technology after the sample information check information of described sample information; Described information transmitted is the information after encoding, and the rule of described coding is that adjacent data has only a bit to change;
Comparing unit is used for the check information that check information that described check information unit is obtained and described sample processing unit generate and compares, if unequal, then judges the sample information mistake.
8. error detection treating apparatus according to claim 7 is characterized in that, described error detection treating apparatus further comprises:
Error correction unit is used for after comparing unit is judged the sample information mistake described sample information being made amendment.
9. error detection treating apparatus according to claim 7 is characterized in that:
Described sample processing unit is sampled to the information of the employing gray encoding of transmission; Accordingly,
Described error correction unit adds 1 with described sample information after comparing unit is judged the sample information mistake.
10. according to claim 7 or 8 described error detection treating apparatus, it is characterized in that:
Described sample processing unit obtains after the sample information generating according to parity checking or cyclic redundancy check (CRC) the check information of described sample information.
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| CN101345606B (en) * | 2008-08-21 | 2011-03-09 | 炬力集成电路设计有限公司 | Method and apparatus for confirming Hamming error correcting code check bit |
| CN103618655A (en) * | 2013-11-27 | 2014-03-05 | 广州御银科技股份有限公司 | Unified networking management system and method for sorters |
| CN104077373B (en) * | 2014-06-24 | 2018-12-04 | 北京京东尚科信息技术有限公司 | A kind of data consistency verification method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1155950A (en) * | 1995-04-03 | 1997-07-30 | 松下电器产业株式会社 | Data transmission system, data recording and reproducing apparatus and recording medium each having data structure of error correcting code |
| CN1318738A (en) * | 2001-02-18 | 2001-10-24 | 华立集团股份有限公司 | Misread preventing A/D conversion method and device for multiple-place mechanical counter |
| CN1408155A (en) * | 1999-12-03 | 2003-04-02 | 艾利森电话股份有限公司 | Method and arrangement for performing analysis of data network |
| CN1787370A (en) * | 2004-12-09 | 2006-06-14 | 华为技术有限公司 | Apparatus and method for determining clock domain changing abnormal |
-
2007
- 2007-10-30 CN CN2007101660403A patent/CN101145117B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1155950A (en) * | 1995-04-03 | 1997-07-30 | 松下电器产业株式会社 | Data transmission system, data recording and reproducing apparatus and recording medium each having data structure of error correcting code |
| CN1408155A (en) * | 1999-12-03 | 2003-04-02 | 艾利森电话股份有限公司 | Method and arrangement for performing analysis of data network |
| CN1318738A (en) * | 2001-02-18 | 2001-10-24 | 华立集团股份有限公司 | Misread preventing A/D conversion method and device for multiple-place mechanical counter |
| CN1787370A (en) * | 2004-12-09 | 2006-06-14 | 华为技术有限公司 | Apparatus and method for determining clock domain changing abnormal |
Non-Patent Citations (4)
| Title |
|---|
| 周术诚,黄祖泰.异步通讯中错误检测与纠正技术.计算机应用研究 2.1996,(2),83-84. |
| 周术诚,黄祖泰.异步通讯中错误检测与纠正技术.计算机应用研究 2.1996,(2),83-84. * |
| 王永云.信息代码的校验方法与程序设计.计算技术与自动化18 3.1999,18(3),155-157. |
| 王永云.信息代码的校验方法与程序设计.计算技术与自动化18 3.1999,18(3),155-157. * |
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