CN108462655B - FC link elastic buffer circuit - Google Patents
FC link elastic buffer circuit Download PDFInfo
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- CN108462655B CN108462655B CN201611139615.8A CN201611139615A CN108462655B CN 108462655 B CN108462655 B CN 108462655B CN 201611139615 A CN201611139615 A CN 201611139615A CN 108462655 B CN108462655 B CN 108462655B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/35—Switches specially adapted for specific applications
- H04L49/356—Switches specially adapted for specific applications for storage area networks
- H04L49/357—Fibre channel switches
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/40—Constructional details, e.g. power supply, mechanical construction or backplane
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/90—Buffering arrangements
- H04L49/901—Buffering arrangements using storage descriptor, e.g. read or write pointers
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Abstract
The invention provides a FC link elastic buffer circuit, comprising: the device comprises a data writing interface (1), an IDLE detection circuit (2), a writing pointer control circuit (3), a Gray code conversion electric interface (4), an IDLE mark memory circuit (5), a data memory circuit (6), a reading and writing pointer comparison circuit (7), a current data IDLE detection circuit (8), a next data IDLE detection circuit (9), a reading pointer adding 3 circuit (10), a reading pointer control circuit (11) and a reading data interface (12). The invention automatically detects the empty and full states of the FC link receiving data buffer area through a hardware circuit, manages the continuous writing and elastic reading operation of the FC port receiving end data, corrects the clock frequency accumulated deviation between the reading and writing clocks of the receiving buffer area, completes the accurate matching of the sending and receiving port data transmission rate, prevents the data damage caused by the overflow and underflow of the receiving buffer area, ensures the integrity of the receiving data, and realizes the high-speed and high-reliability transmission of the FC link data.
Description
Technical Field
The invention belongs to the technical field of computers, and particularly relates to an FC link elastic buffer circuit.
Background
With the development and the growing maturity of FC technology, it is possible to use the FC network as a backbone network in an onboard environment. In the process of building the FC network, a large number of devices such as FC node machines and FC switches are used, and although all communication devices must work at the same frequency, due to the difference of clock phases and factors of processes in the crystal oscillator production and manufacturing process, certain errors are allowed in two clock frequencies.
Error of clock prescribed by FC network protocol is + -100 × 10-6I.e., a deviation of 100 clock cycles is allowed in the time range of every million and ideal clock cycles. In the worst case, the maximum error that may exist between two different crystal oscillators is 200 × 10-6Cumulative 10-6/2A clock cycle offset of one occurs at 00-5000 clock cycles.
For a continuous data stream transmitted at a high speed, a buffer for buffering received data, a write clock of the data is derived from a sending end clock recovered from the received data, and a read clock is derived from a clock generated by a local crystal oscillator at a receiving end, if accumulated clock period offset between the write clock and the read clock cannot be correctly processed, overflow of the data receiving buffer will be caused, the received data is damaged or data loss is generated, and the function and performance of system communication are seriously affected.
Disclosure of Invention
The purpose of the invention is as follows: the invention aims to provide an FC link elastic buffer area circuit, which corrects the frequency accumulation difference of a write clock and a read clock of a buffer area at a data receiving end by controlling the write operation and the read operation of the buffer area, and solves the problem of data damage or data loss caused by frequency accumulation deviation in the design process of an FC port.
The technical scheme is as follows: the invention provides an FC link elastic buffer circuit, which comprises a data writing interface 1, an IDLE detection circuit 2, a writing pointer control circuit 3, a first Gray code conversion circuit 4-1, a first Gray code conversion circuit 4-2, a first Gray code conversion circuit 4-3, an IDLE mark memory circuit 5, a data memory circuit 6, a reading and writing pointer comparison circuit 7, a current data IDLE detection circuit 8, a next data IDLE detection circuit 9, a reading pointer adding 3 circuit 10, a reading pointer control circuit 11 and a data reading interface 12,
the data writing method comprises the following steps that a data writing interface 1, an IDLE detection circuit 2, a writing pointer control circuit 3, a first Gray code conversion circuit 4-1, an IDLE mark memory circuit 5 and a data memory circuit 6 are used for completing the writing operation of data input into the IDLE mark memory circuit 5 and the data memory circuit 6 by the data writing interface 1 under a writing clock domain;
the circuit comprises a second Gray code conversion circuit 4-2, a third Gray code conversion circuit 4-3, an IDLE mark memory circuit 5, a data memory circuit 6, a read-write pointer comparison circuit 7, an IDLE detection circuit 8 for current data, an IDLE detection circuit 9 for next data, a read pointer adding 3 circuit 10, a read pointer control circuit 11 and a read data interface 12, wherein effective data are output from the read data interface 12 under a read clock domain, the read data pointer is controlled only in the read clock domain, elastic control of data buffering of a receiving port is realized, and data loss caused by overflow and underflow of a buffer area is prevented.
The write data interface 1 outputs a write data signal d _ in to the IDLE detection circuit 2; the write data interface 1 outputs a write clock signal w _ clk, a reset signal w _ rst of a write clock domain and a write enable signal w _ en to the write pointer control circuit 3 to control the change of a write pointer wprtb; the write data interface 1 outputs a write clock signal w _ clk, a reset signal w _ rst of a write clock domain, and a write data signal d _ in data memory circuit 6;
the IDLE detection circuit 2 outputs the detected IDLE flag bit to the IDLE flag memory circuit 5;
the write pointer control circuit 3 outputs a write pointer wprtb to the first gray code conversion circuit 4-1;
the first gray code conversion circuit 4-1 outputs the converted gray code pointer wprt to the IDLE mark memory circuit 5, the data memory circuit 6 and the read-write pointer comparison circuit 7;
the IDLE tag memory circuit 5 outputs data to the IDLE detection circuit 8 for the current number and the IDLE detection circuit 9 for the next number under the control of the read pointer rprt signal output by the second gray code conversion circuit 4-2 and the read pointer rprt _ pre signal output by the second gray code conversion circuit 4-3;
the data memory circuit 6 outputs read data to a read data interface 12;
the read-write pointer comparison circuit 7 outputs a full signal a _ full to empty signal a _ empty to the read pointer control circuit 11;
the current data is that the IDLE detection circuit 8 outputs a doultiidle signal to the read pointer control circuit 11;
the next data is that the IDLE detection circuit 9 outputs a DoutNextIsIdle signal to the read pointer control circuit 11;
the read pointer adding 3 circuit 10 outputs rprtb +3 signals to the second gray code conversion circuit 4-2;
the third gray code conversion circuit 4-3 outputs the converted read pointer to the IDLE mark memory circuit 5, the data memory circuit 6 and the read-write pointer comparison circuit 7;
the read pointer control circuit 11 outputs a 2-system read pointer to the read pointer adding 3 circuit 10 and the third gray code conversion circuit 4-3;
the read data interface 12 outputs a read clock signal r _ clk, a reset signal r _ rst of a read clock domain, and a read enable signal r _ en to the read pointer control circuit 11; the read clock signal w _ clk is output to the data memory circuit 6.
The write data interface 1 includes: elastic buffer data input: d _ in; elastic buffer write clock: w _ clk; elastic buffer write reset signal: w _ rst; elastic buffer write enable signal: w _ en;
the IDLE detection circuit 2 is configured to detect data input by the data writing interface 1d _ in, and determine that two consecutive data input from d _ in form a complete IDLE primitive signal, where a 16-ary value of the complete IDLE primitive signal is 0xBC95B5B5, and a maximum eight-bit character 0xBC is a K character;
the write pointer control circuit 3 is used for controlling the write pointer wptrb to add 1 in each write clock cycle when the write enable signal is valid, and the initial value after the write pointer is reset should be located in the middle of the elastic buffer area;
the first gray code converting circuit 4-1, the second gray code converting circuit 4-2 and the third gray code converting circuit 4-3 are used for converting the values of the binary write pointer wptrb output by the write pointer control circuit 3, the read pointer rptrb output by the read pointer control circuit 11 and the read pointer rptrb +3 output by the read pointer plus 3 circuit into gray codes respectively. Taking the case of converting the binary write pointer wptrb into the gray code wptr, the processing method of the conversion circuit is as follows: and wptr is (wptrb > >1) ^ wptrb, and the conversion methods of the binary read pointer rptrb and the read pointer rptrb +3 are the same.
The IDLE mark memory circuit 5 is used for storing the result output by the IDLE detection circuit, 1 is written when an IDLE primitive signal is detected, otherwise 0 is written, and the written address is the same as the address written by the data in the data memory circuit; the depth of the IDLE mark memory circuit is required to be the same as that of the data memory circuit, and the data bit width is 1 bit;
the data memory circuit 6 is configured to store data input by the d _ in interface to a storage location corresponding to the write pointer wptr in each write clock cycle, and output received data at the storage location corresponding to the read pointer rptr to the d _ out interface in each read clock cycle; the memory depth of the data memory circuit can be determined according to the clock phase and frequency deviation of a write clock and a read clock, and the data memory bit width is the same as the widths of input data d _ in and output data d _ out;
the read-write pointer comparison circuit 7 compares the read pointer converted into the gray code with the upper two bits of the write pointer, and the used comparison method is as follows:
a_full＝(wptr[N]^rptr[N-1])&～(wptr[N-1]^rptr[N])；
a_empty＝(～wptr[N]^rptr[N-1])&(wptr[N-1]^rptr[N])；
an a _ full of 1 indicates that the write pointer will catch up with the read pointer and the elastic buffer will be full, an a _ empty of 1 indicates that the read pointer will catch up with the write pointer and the elastic buffer will be empty.
The current data is an IDLE detection circuit 8, the working principle of the IDLE detection circuit is the same as that of the IDLE detection circuit 2, a current read pointer rptr converted into a gray code is detected, whether the data stored in a corresponding data storage circuit is an IDLE primitive signal or not is judged, if yes, a DoutIsIdle signal is 1, and if not, the DoutIsIdle signal is 0;
the next data is an IDLE detection circuit 9, and the operation principle of the IDLE detection circuit is the same as that of the IDLE detection circuit, and the next position rprt _ pre of the current read pointer converted into the gray code is detected, whether the data stored in the corresponding data storage circuit is an IDLE primitive signal is detected, if yes, the doutnext primitive signal is 1, and if not, the doutnext primitive signal is 0.
The read pointer plus 3 circuit 10 is used for adding 3 to the current read pointer and is used for pre-reading the flag bit stored in the IDLE flag memory circuit;
the read pointer control circuit 11 is configured to, when the read enable signal r _ en is asserted: under normal conditions, the circuit controls the read pointer rptrb to add 1 to each read clock cycle, and data in the data memory circuit are read sequentially; detecting that the a _ full signal is valid, the DoutIsIdle signal and the DoutNextIsIdle signal are valid, adding 3 to the read pointer rptrb, skipping an address space for storing a complete IDLE primitive signal, reducing two read operations, starting the read operation from the next valid data address, accelerating the read operation of the elastic buffer area and preventing the elastic buffer area from overflowing; detecting that the a _ empty signal is valid and the DoutIsIdle signal is valid, subtracting 1 from the value of the read pointer rptrb, reading out a complete IDLE primitive signal stored in the current two addresses again, repeating the reading operation for two times, slowing down the reading operation of the elastic buffer area and preventing the underflow of the elastic buffer area; the initial value of the reset read pointer is located at the initial position of the elastic buffer area.
The read data interface 12 includes: elastic buffer data input interface: d _ out; elastic buffer write clock: r _ clk; elastic buffer write reset signal: r _ rst; elastic buffer write enable signal: r _ en.
Has the advantages that:
the FC link elastic buffer circuit provided by the invention controls the read pointer only in the read clock domain, is simple in design, and is easy to implement and small in resource occupancy rate compared with the elastic buffer design for controlling the read pointer and the write pointer; the design of the elastic buffer area can keep the difference value of the write pointer and the read pointer in the space of a half elastic buffer area, and can tolerate larger read-write clock deviation; the circuit is realized by adopting full hardware, software intervention is not needed, the circuit can be quickly integrated into the development of FC port equipment, and the popularization and the application of an FC network in the airborne field are accelerated.
Drawings
FIG. 1 is a schematic diagram of a circuit structure of an FC link elastic buffer according to the present invention.
The specific implementation mode is as follows:
the technical solution of the present invention is further described below with reference to the accompanying drawings and specific embodiments, please refer to fig. 1.
The invention provides an FC link elastic buffer circuit, which comprises a data writing interface 1, an IDLE detection circuit 2, a writing pointer control circuit 3, a first Gray code conversion circuit 4-1, a first Gray code conversion circuit 4-2, a first Gray code conversion circuit 4-3, an IDLE mark memory circuit 5, a data memory circuit 6, a reading and writing pointer comparison circuit 7, a current data IDLE detection circuit 8, a next data IDLE detection circuit 9, a reading pointer adding 3 circuit 10, a reading pointer control circuit 11 and a data reading interface 12,
the data writing method comprises the following steps that a data writing interface 1, an IDLE detection circuit 2, a writing pointer control circuit 3, a first Gray code conversion circuit 4-1, an IDLE mark memory circuit 5 and a data memory circuit 6 are used for completing the writing operation of data input into the IDLE mark memory circuit 5 and the data memory circuit 6 by the data writing interface 1 under a writing clock domain;
the circuit comprises a second Gray code conversion circuit 4-2, a third Gray code conversion circuit 4-3, an IDLE mark memory circuit 5, a data memory circuit 6, a read-write pointer comparison circuit 7, an IDLE detection circuit 8 for current data, an IDLE detection circuit 9 for next data, a read pointer adding 3 circuit 10, a read pointer control circuit 11 and a read data interface 12, wherein effective data are output from the read data interface 12 under a read clock domain, the read data pointer is controlled only in the read clock domain, elastic control of data buffering of a receiving port is realized, and data loss caused by overflow and underflow of a buffer area is prevented.
The write data interface 1 outputs a write data signal d _ in to the IDLE detection circuit 2; the write data interface 1 outputs a write clock signal w _ clk, a reset signal w _ rst of a write clock domain and a write enable signal w _ en to the write pointer control circuit 3 to control the change of a write pointer wprtb; the write data interface 1 outputs a write clock signal w _ clk, a reset signal w _ rst of a write clock domain, and a write data signal d _ in data memory circuit 6;
the IDLE detection circuit 2 outputs the detected IDLE flag bit to the IDLE flag memory circuit 5;
the write pointer control circuit 3 outputs a write pointer wprtb to the first gray code conversion circuit 4-1;
the first gray code conversion circuit 4-1 outputs the converted gray code pointer wprt to the IDLE mark memory circuit 5, the data memory circuit 6 and the read-write pointer comparison circuit 7;
the IDLE tag memory circuit 5 outputs data to the IDLE detection circuit 8 for the current number and the IDLE detection circuit 9 for the next number under the control of the read pointer rprt signal output by the second gray code conversion circuit 4-2 and the read pointer rprt _ pre signal output by the second gray code conversion circuit 4-3;
the data memory circuit 6 outputs read data to a read data interface 12;
the read-write pointer comparison circuit 7 outputs a full signal a _ full to empty signal a _ empty to the read pointer control circuit 11;
the current data is that the IDLE detection circuit 8 outputs a doultiidle signal to the read pointer control circuit 11;
the next data is that the IDLE detection circuit 9 outputs a DoutNextIsIdle signal to the read pointer control circuit 11;
the read pointer adding 3 circuit 10 outputs rprtb +3 signals to the second gray code conversion circuit 4-2;
the third gray code conversion circuit 4-3 outputs the converted read pointer to the IDLE mark memory circuit 5, the data memory circuit 6 and the read-write pointer comparison circuit 7;
the read pointer control circuit 11 outputs a 2-system read pointer to the read pointer adding 3 circuit 10 and the third gray code conversion circuit 4-3;
the read data interface 12 outputs a read clock signal r _ clk, a reset signal r _ rst of a read clock domain, and a read enable signal r _ en to the read pointer control circuit 11; the read clock signal w _ clk is output to the data memory circuit 6.
The write data interface 1 includes: elastic buffer data input: d _ in; elastic buffer write clock: w _ clk; elastic buffer write reset signal: w _ rst; elastic buffer write enable signal: w _ en;
the IDLE detection circuit 2 is configured to detect data input by the data writing interface 1d _ in, and determine that two consecutive data input from d _ in form a complete IDLE primitive signal, where a 16-ary value of the complete IDLE primitive signal is 0xBC95B5B5, and a maximum eight-bit character 0xBC is a K character;
the write pointer control circuit 3 is used for controlling the write pointer wptrb to add 1 in each write clock cycle when the write enable signal is valid, and the initial value after the write pointer is reset should be located in the middle of the elastic buffer area;
the first gray code converting circuit 4-1, the second gray code converting circuit 4-2 and the third gray code converting circuit 4-3 are used for converting the values of the binary write pointer wptrb output by the write pointer control circuit 3, the read pointer rptrb output by the read pointer control circuit 11 and the read pointer rptrb +3 output by the read pointer plus 3 circuit into gray codes respectively. Taking the case of converting the binary write pointer wptrb into the gray code wptr, the processing method of the conversion circuit is as follows: and wptr is (wptrb > >1) ^ wptrb, and the conversion methods of the binary read pointer rptrb and the read pointer rptrb +3 are the same.
The IDLE mark memory circuit 5 is used for storing the result output by the IDLE detection circuit, 1 is written when an IDLE primitive signal is detected, otherwise 0 is written, and the written address is the same as the address written by the data in the data memory circuit; the depth of the IDLE mark memory circuit is required to be the same as that of the data memory circuit, and the data bit width is 1 bit;
the data memory circuit 6 is configured to store data input by the d _ in interface to a storage location corresponding to the write pointer wptr in each write clock cycle, and output received data at the storage location corresponding to the read pointer rptr to the d _ out interface in each read clock cycle; the memory depth of the data memory circuit can be determined according to the clock phase and frequency deviation of a write clock and a read clock, and the data memory bit width is the same as the widths of input data d _ in and output data d _ out;
the read-write pointer comparison circuit 7 compares the read pointer converted into the gray code with the upper two bits of the write pointer, and the used comparison method is as follows:
a_full＝(wptr[N]^rptr[N-1])&～(wptr[N-1]^rptr[N])；
a_empty＝(～wptr[N]^rptr[N-1])&(wptr[N-1]^rptr[N])；
an a _ full of 1 indicates that the write pointer will catch up with the read pointer and the elastic buffer will be full, an a _ empty of 1 indicates that the read pointer will catch up with the write pointer and the elastic buffer will be empty.
The current data is an IDLE detection circuit 8, the working principle of the IDLE detection circuit is the same as that of the IDLE detection circuit 2, a current read pointer rptr converted into a gray code is detected, whether the data stored in a corresponding data storage circuit is an IDLE primitive signal or not is judged, if yes, a DoutIsIdle signal is 1, and if not, the DoutIsIdle signal is 0;
the next data is an IDLE detection circuit 9, and the operation principle of the IDLE detection circuit is the same as that of the IDLE detection circuit, and the next position rprt _ pre of the current read pointer converted into the gray code is detected, whether the data stored in the corresponding data storage circuit is an IDLE primitive signal is detected, if yes, the doutnext primitive signal is 1, and if not, the doutnext primitive signal is 0.
The read pointer plus 3 circuit 10 is used for adding 3 to the current read pointer and is used for pre-reading the flag bit stored in the IDLE flag memory circuit;
the read pointer control circuit 11 is configured to, when the read enable signal r _ en is asserted: under normal conditions, the circuit controls the read pointer rptrb to add 1 to each read clock cycle, and data in the data memory circuit are read sequentially; detecting that the a _ full signal is valid, the DoutIsIdle signal and the DoutNextIsIdle signal are valid, adding 3 to the read pointer rptrb, skipping an address space for storing a complete IDLE primitive signal, reducing two read operations, starting the read operation from the next valid data address, accelerating the read operation of the elastic buffer area and preventing the elastic buffer area from overflowing; detecting that the a _ empty signal is valid and the DoutIsIdle signal is valid, subtracting 1 from the value of the read pointer rptrb, reading out a complete IDLE primitive signal stored in the current two addresses again, repeating the reading operation for two times, slowing down the reading operation of the elastic buffer area and preventing the underflow of the elastic buffer area; the initial value of the reset read pointer is located at the initial position of the elastic buffer area.
The read data interface 12 includes: elastic buffer data input interface: d _ out; elastic buffer write clock: r _ clk; elastic buffer write reset signal: r _ rst; elastic buffer write enable signal: r _ en.
Claims (2)
1. An FC link elastic buffer circuit is characterized by comprising a write data interface (1), an IDLE detection circuit (2), a write pointer control circuit (3), a first Gray code conversion circuit (4-1), a second Gray code conversion circuit (4-2), a third Gray code conversion circuit (4-3), an IDLE mark memory circuit (5), a data memory circuit (6), a read-write pointer comparison circuit (7), a current data IDLE detection circuit (8), a next data IDLE detection circuit (9), a read pointer plus 3 circuit (10), a read pointer control circuit (11) and a read data interface (12),
the data writing method comprises the following steps that a data writing interface (1), an IDLE detection circuit (2), a writing pointer control circuit (3), a first Gray code conversion circuit (4-1), an IDLE mark memory circuit (5) and a data memory circuit (6) are used for finishing the writing operation of inputting data into the IDLE mark memory circuit (5) and the data memory circuit (6) by the data writing interface (1) under a writing clock domain;
the device comprises a second Gray code conversion circuit (4-2), a third Gray code conversion circuit (4-3), an IDLE mark memory circuit (5), a data memory circuit (6), a read-write pointer comparison circuit (7), a current data IDLE detection circuit (8), a next data IDLE detection circuit (9), a read pointer adding 3 circuit (10), a read pointer control circuit (11) and a read data interface (12), wherein effective data are output from the read data interface (12) under a read clock domain, and the read data pointer is controlled only in the read clock domain, so that the elastic control of data buffering of a receiving port is realized, and the data loss caused by overflow and underflow of a buffer area is prevented;
the IDLE mark memory circuit (5) outputs data to the current data IDLE detection circuit (8) and the next data IDLE detection circuit (9) under the control of a read pointer rprt signal output by the second Gray code conversion circuit (4-2) and a read pointer rprt _ pre signal output by the third Gray code conversion circuit (4-3);
the data memory circuit (6) outputs read data to a read data interface (12);
the read-write pointer comparison circuit (7) outputs a full signal a _ full and an empty signal a _ empty to the read pointer control circuit (11);
the current data is that the IDLE detection circuit (8) outputs a DoutIsIdle signal to the read pointer control circuit (11); the next data is that the IDLE detection circuit (9) outputs a DoutNextIsIdle signal to the read pointer control circuit (11); the read pointer adding 3 circuit (10) outputs rprtb +3 signals to the second Gray code conversion circuit (4-2);
the third Gray code conversion circuit (4-3) outputs the converted reading pointer to the IDLE mark memory circuit (5), the data memory circuit (6) and the reading-writing pointer comparison circuit (7);
the read pointer control circuit (11) outputs a 2-system read pointer to the read pointer adding 3 circuit (10) and the third Gray code conversion circuit (4-3);
the read data interface (12) outputs a read clock signal r _ clk, a reset signal r _ rst of a read clock domain and a read enable signal r _ en to a read pointer control circuit (11); a read clock signal w _ clk is output to a data memory circuit (6).
2. The FC link elasticity buffer circuit of claim 1, wherein the write data interface (1) outputs a write data signal d _ in to the IDLE detection circuit (2); the write data interface (1) outputs a write clock signal w _ clk, a reset signal w _ rst of a write clock domain and a write enable signal w _ en to a write pointer control circuit (3) to control the change of a write pointer wprtb; a data memory circuit (6) for outputting a write clock signal w _ clk, a reset signal w _ rst of a write clock domain, and a write data signal d _ in from a write data interface (1);
the IDLE detection circuit (2) outputs the detected IDLE flag bit to an IDLE flag memory circuit (5); the write pointer control circuit (3) outputs a write pointer wprtb to the first gray code conversion circuit (4-1);
the first Gray code conversion circuit (4-1) outputs the converted Gray code pointer wprt to an IDLE mark memory circuit (5), a data memory circuit (6) and a read-write pointer comparison circuit (7).
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