CN102708086A

CN102708086A - Elastic buffer structure and method applied to universal serial bus 3.0 (USB 3.0)

Info

Publication number: CN102708086A
Application number: CN2012101454962A
Authority: CN
Inventors: 朱小明
Original assignee: WUXI HUADA GUOQI TECHNOLOGY CO LTD
Current assignee: WUXI HUADA GUOQI TECHNOLOGY CO LTD
Priority date: 2012-05-10
Filing date: 2012-05-10
Publication date: 2012-10-03
Anticipated expiration: 2032-05-10
Also published as: CN102708086B

Abstract

The invention discloses an elastic buffer structure and a method applied to universal serial bus 3.0 (USB 3.0). The elastic buffer structure comprises an input check module, a binary code and Gray code read-write pointer generation module, a synchronization module, a read-write control module, a threshold value monitoring module and an output control module. According to the protocol requirement of the USB 3.0, by means of the analysis of an action mechanism of elastic buffer, asynchronous first in first out (FIFO) which has innovative functions of writing pointer shield, point jumping, breakpoint saving and handshake, output control and the like is used for designing the elastic buffer, and the purpose of clock frequency compensation is well achieved; and according to the designed elastic buffer, parallel 40-bit data are used, the read-write clock frequency can reach 125 MHz.

Description

A kind of elastic buffer structure and method that is applied to USB3.0

Technical field

The present invention relates to the elastic buffer structure of a kind of USB3.0 of being applied to.

Background technology

(Universal Serial Bus 3.0 USB3.0) is the standard of being announced in November, 2008 by companies such as Intel, Microsoft, NEC to USB 3.0.USB is the new interface technology that was applied in the PC field in the last few years.With respect to USB2.0, USB3.0 still belongs at a high speed, serial, the host-host protocol that the source is synchronous.Adopt the mode of differential pair to send serial data at transmitting terminal, (Clock and Data Recovery CDR) recovers serial data and clock from serial data to utilize the clock and data recovery circuit at receiving end.Because the transmitting-receiving two-end of USB3.0 is supported independently reference clock source, so there is difference in the clock frequency that receiving end recovers with its local clock frequency.In order to compensate the frequency difference of two clocks, need an elastic buffer (Elastic buffer), with CDR clock recovered numeric field data efficient synchronization in the local clock territory.

Elastic buffer by Maurice Karnaugh in telephone network the transmission pulse coded modulation (Pulse Code Modulation PCM) puts forward in the signal.Elastic buffer is through inserting and delete the purpose that a certain special symbol is realized clock compensation; And synchrodata between two clock zones that can be stable; Therefore; Elastic buffer is used in a lot of technical application, has for example all adopted the elastic buffer technology to come synchrodata in the agreements such as USB, PCIE, Ethernet.Yet under the USB3.0 agreement, still there is not the elastic buffer that is applicable to the USB3.0 Physical layer.

Summary of the invention

To above-mentioned technical matters, the present invention designs a kind of according to the USB3.0 agreement, designed and Implemented the elastic buffer structure that is applicable to the USB3.0 Physical layer with and method.

In order to solve the problems of the technologies described above, technical scheme of the present invention is following:

A kind of elastic buffer structure that is applied to USB3.0 comprises input detection module, binary code and Gray code read-write pointer generation module, synchronization module, read-write control module, threshold monitoring module and output control module;

Said input detection module is responsible for detecting in the input data whether comprise SKP; If comprise SKP in the input data then provide indicator signal; The deletion that said indicator signal and said threshold monitoring module provide is perhaps inserted the SKP signal together, is used for controlling deletion or the insertion that said read-write control module is accomplished SKP;

Said binary code and Gray code read-write pointer generation module are responsible for producing the binary code and the Gray code read-write pointer of elastic buffer;

The Gray code that said synchronization module utilizes said binary code and Gray code read-write pointer generation module to produce realize Gray code read-write pointer between the read-write clock zone synchronously; The binary code that said binary code and Gray code read-write pointer generation module produce is as the address input of storage unit; Read pointer with Gray code; Be synchronized to through two registers of writing clock control and write in the clock zone; Then with write pointer be synchronized to the read pointer of writing clock zone and do and relatively produce the full sign of FIFO, write pointer is synchronized to reads to produce in the clock zone the empty sign of FIFO;

Said threshold monitoring module will be synchronized to the Gray code read pointer of writing in the clock zone and be converted into binary code and relatively judge the valid data among the FIFO with the write pointer of binary code; When the data among the FIFO are less than when equaling 6; Add SKP; The add_skp signal is effective, when the data among the FIFO more than or equal to 10 time deletion SKP, the dele_skp signal is effective; Whether the write pointer control module is effective based on dele_skp or add_skp signal; Accomplish the function that deletion is imported the SKP in the data or in FIFO, inserted new SKP, said output control module and said write pointer control module are accomplished the insertion function of SKP together;

The read pointer control module is controlled according to the symbol_lock signal and to be read enable signal.

Further, said FIFO realizes through the SKP removing module the deletion of SKP.

Further, said FIFO preserves the breakpoint that is inserted through of SKP, and write pointer jumps and shakes hands and output control module is realized.

A kind of elastic buffer method that is applied to USB3.0; Comprise the steps: to FIFO input data; Said input detection module is responsible for detecting in the input data whether comprise SKP; Provide indicator signal if comprise SKP in the input data, the deletion that this indicator signal and threshold monitoring module provide is perhaps inserted the SKP signal together, is used for controlling deletion or the insertion that the read-write control module is accomplished SKP;

The Gray code that said synchronization module utilizes said binary code and Gray code read-write pointer generation module to produce realize Gray code read-write pointer between the read-write clock zone synchronously; The binary code that said binary code and Gray code read-write pointer generation module produce is as the address input of storage unit; Read pointer with Gray code; Be synchronized to through two registers of writing clock control and write in the clock zone; Then with write pointer be synchronized to the read pointer of writing clock zone and do and relatively produce the full sign of FIFO, write pointer is synchronized to reads to produce in the clock zone the empty sign of FIFO; Time high-order with the read-write pointer address to the address of lowest order as storage unit, FIFO be empty when read/write address is identical, when read-write pointer most significant digit different and all the other all when identical FIFO for expiring; Said threshold monitoring module will be synchronized to the Gray code read pointer of writing in the clock zone and be converted into binary code and relatively judge the valid data among the FIFO with the write pointer of binary code; When the data among the FIFO are less than when equaling 6; Add SKP; The add_skp signal is effective, when the data among the FIFO more than or equal to 10 time deletion SKP, the dele_skp signal is effective;

Whether the write pointer control module is effective based on dele_skp or add_skp signal; Accomplish the function that deletion is imported the SKP in the data or in FIFO, inserted new SKP, said output control module and said write pointer control module are accomplished the insertion function of SKP together;

The read pointer control module is controlled according to the symbol_lock signal and to be read enable signal;

When reading clock faster than writing clock, the data of promptly reading are added SKP through writing control module to FIFO more than the data that write; Make FIFO keep half-full state; And write pointer carries out hop interval forward, and preserves the position of jump, when read pointer is read between the skip zone; Through output control module, accomplish SKP and add;

Be slower than and write clock when reading clock, the data that promptly write are more than the data of reading, and at this moment, FIFO should delete the SKP in the input data, and it is half-full to make that FIFO keeps, and regulates clock with this.

Further, the SKP in the said deletion input data specifically comprises the steps; With being used for the temporary data of importing deletion SKP module in the maintenance register; When deletion SKP threshold signal dele_skp is invalid; Need not delete SKP; Keep the input and output data bit number average of register identical with the data of input deletion SKP module, the data of said maintenance register upper byte are the write data of ram as output; The data of input write on the low byte that keeps register, the data shift of low byte that keeps register simultaneously on the upper byte as output; Simultaneously, the counter hr_cnt record of the number through keeping the byte in the register keeps the byte number that exists in the register this moment;

When deletion SKP threshold signal dele_skp signal is effective; And when having SKP in the data of input deletion SKP module; The input data are rejected SKP through after deleting the SKP module, only valid data are written in the low byte that keeps register; Keep the data in the register to become 6 this moment, because deleted 2 skp that import in 4 data.If during the clock period, the data of input do not comprise SKP at the next one, keep keeping in the register original 6 data constant so; If after a period of time, if comprise SKP again in the data of input, and this moment, the dele_skp signal was still effective; Then delete the SKP module and reject SKP in the data, valid data are written in the maintenance register, the storage data are a half of its entire capacity in the register if keep; I.e. 4 data, it is effective with the dele_skp_en signal then to delete the SKP module, makes and writes an invalid clock period of enable signal; Data are not written among the ram in the register keeping, and keep having recovered again in the register 8 valid data like this.

Further, the SKP in the said insertion input data specifically comprises the steps; Write pointer calculates the valid data number among the FIFO; According to the number of valid data among the FIFO and the gap of the full up data number of FIFO; Decision binary write address next pointer point pointed; Under the control of write pointer module, accomplish the jump of write pointer, be write pointer and jump, and be saved in current write pointer and next pointer point in current binary write address and the next binary write address writing clock zone; Writing clock zone to putting up a notice the read pointer signal simultaneously; When read pointer was read the start address of breakpoint, it was effective to insert the skp enable signal, and the feedback answer signal; Detect ack signal notice of cancellation read pointer signal when effective when writing clock zone; Output control module detect insert the skp enable signal effectively after, insert new skp according to the value of the RD operation difference parameter of the skp of input this moment, output control module guarantees to insert the requirement that all skp all satisfy the 8B10B coding; When read pointer was read the end address of breakpoint, it is invalid that insertion skp enable signal becomes, and cancels the ack signal simultaneously, accomplishes the insertion of skp, makes FIFO keep half-full state;

Said read pointer signal and ack signal are a pair of handshake, have guaranteed that a write pointer jumps in the insertion of reading a SKP of clock zone completion, has avoided in the read pointer territory, repeating to insert skp.

Beneficial effect of the present invention is: adopt and relatively judge the valid data number in the elastic buffer synchronously; The burr and the instability of asynchronous comparison have been avoided; Adopted a kind of new full empty sign production method, adopted the write pointer shielding, the mode that write pointer jumps and the read-write pointer is shaken hands realizes deletion and the insertion of SKP; Through having increased the removing module of SKP sequence sets, solved the problem of in the input data of 40 bits, how to delete the SKP sequence sets of 20 bit bit wides.

Description of drawings

Fig. 1 is a USB3.0 Physical layer receiving unit structure;

Fig. 2 reads faster than write in the Chang Banman pattern;

Fig. 3 writes faster than read in the Chang Banman pattern;

Fig. 4 is the structure of elastic buffer;

Fig. 5 is a SKP removing module schematic diagram;

Fig. 6 is deletion SKP module input and output sequential chart;

Fig. 7 is the deletion sequential chart of the elastic buffer of 40 bit bit wides to SKP.

Embodiment

Below in conjunction with accompanying drawing and specific embodiment the present invention is further specified.

The action scope of elastic buffer and capacity thereof:

The action scope of elastic buffer

The data transmission of USB3.0 adopts full duplex (Full duplex), and Physical layer has two differential signals right, and is a pair of right for sending differential signal, and another is to right for receiving differential signal.Because elastic buffer only is used for receiving end, provide the block diagram of receiving end of the Physical layer of 10 Bit data bit wides like Fig. 1, it comprises differential received, clock data recovery circuit, string and conversion, 8B10B decoding and descrambling circuit etc.As shown in Figure 1, differential signal is received by the differential received termination, recovers clock and data through CDR; Data become the data of 40 bits through string and conversion then; The beginning flag that detects bag through sequential detector accords with K28.5, when detecting K28.5, makes symbol lock (symbol lock) signal effective; When symbol lock was effective, elastic buffer began to write data.The clock of writing of elastic buffer is the CDR clock recovered, be called receive clock, and it reads the system clock that clock is a receiving end.Through elastic buffer with the data efficient synchronization in receive clock territory to the system clock territory, and through 8B10B decoding with descrambler with data transfer to system.The input data of 8B10B demoder are 40 bits, and output data is 32 bits, 4 the 8B10B demoders that are input as 10 bits that have been equivalent to cascade.

The elastic buffer capacity

In order to compensate the frequency difference of receive clock and system clock; Insert a SKP sequence to (SKP ordered set) in 354 bytes of the average every transmission of transmitting terminal; SKP ordered set is made up of 2 SKP (K28.1), when the receiving end elastic buffer detects SKP ordered set, deletes or insert SKP ordered set according to the number of data in this moment elastic buffer.Because transmission and the receiving end of USB3.0 adopt independently reference clock, so, have a clock jitter through the receive clock that CDR recovers out with local system clock at receiving end.In order to mate the frequency difference at two ends, need an elastic buffer, reach rate-matched through inserting and delete SKP.

The reference clock precision-300 of the present invention design is to+300ppm (ppm unit be 1,000,000/); The clock of spread spectrum clock (Spread Spectrum Clocking) is changed to-5000ppm to 0; Therefore; The clock jitter of transmitting terminal and receiving end is-and 5300ppm is to 300ppm, and maximum deviation is 5600ppm.No matter reference clock frequency how, deviation between the two is 5600*0.000001=0.0056T.The maximum data packet length is 1056 bytes in USB3.0, and protocol requirement can not insert SKP in a packet.The maximum data deviation that following two clocks of the poorest situation send data is: (T*1056*10-T (1-0.0056) * 1056*10)/T=59 bit=8 bytes take advantage of 10 to be to have considered the 8b/10b coding here, so elastic buffer capacity minimum are 8 bytes.

The elastic buffer degree of depth is its data number that can deposit, can know that through calculating the degree of depth of elastic buffer should be 8.This paper designs and adopts Chang Banman (Normal half full) pattern to come the design flexibility buffering, and its capacity is 16, and 8 data are arranged in the elastic buffer under normal conditions, and remaining 8 is cushion space, so claim Chang Banman.The Chang Banman pattern at first will write 8 data in elastic buffer, reach half-full, read then to enable effectively, the Chang Banman pattern only in the symbol formation, occur SKP to the time, could add that perhaps to delete SKP right.

The principle of elastic buffer and structure:

Embodiment one:

Being the principle of elastic buffer below, is example with 40 bits, 10 bits no matter, and 20 bits still are 40 bits, and its principle is identical.

The principle of elastic buffer:

Elastic buffer comes down to an asynchronous FIFO, and it writes clock is receive clock, and reading clock is system clock; Data bit width is 40 bits, and the FIFO degree of depth is 16, when symbol lock is effective; In the receive clock territory, in FIFO, write 8 data from deserializer.When the same speed of read-write clock, 8 valid data are arranged among the FIFO, maintain half-full state.

When reading clock faster than writing clock, the data of reading cause the data bulk among the FIFO to be less than 8 after after a while more than the data that write, even might be read sky.As shown in Figure 2, when SKP occurring in the data of input 40 bits, valid data are 4 among the FIFO, have lacked 4 than normality.At this moment, elastic buffer should add 4 SKP, makes FIFO keep half-full state, regulates clock with this.This moment write pointer 4 intervals of jumping forward, and the position of preserving jump is when read pointer is read between the skip zone; Through output control, accomplish SKP and add, that is to say; The SKP that will newly not insert writes among the FIFO really; Address date between the skip zone is invalid data, and the SKP that adds must satisfy the requirement of operation difference parameter (Running Disparity), otherwise makes mistakes can cause 8B10B decoding the time.

Be slower than and write clock when reading clock, the data that write are more than the data of reading, and after after a while, will cause data bulk among the FIFO more than 8, even might be write full.As shown in Figure 3, when in the input data, SKP occurring, valid data are 10 among the FIFO, Duo for 2. this moments than normality, and elastic buffer should be deleted the SKP in the input data, and it is half-full to make that FIFO keeps, and regulates clock with this.

In the process of elastic buffer read-write control, write prior to read.After data among the FIFO reached 8, read-write simultaneously effectively.When writing end, promptly a bag receives and finishes, but reads not necessarily to finish, and until reading sky, promptly all data have been synchronized in the local system clock zone, and expression is is this time read and write subtask and finished.This flow process control has just kept the integrality of system data.

The structural design of elastic buffer:

The present invention adopts and relatively judges the valid data number in the elastic buffer synchronously; The burr and the instability of asynchronous comparison have been avoided; Adopted a kind of new full empty sign production method, adopted the write pointer shielding, the mode that write pointer jumps and the read-write pointer is shaken hands realizes deletion and the insertion of SKP.This paper another one innovation part has been to increase the removing module of SKP sequence sets, has solved the problem of in the input data of 40 bits, how to delete the SKP sequence sets of 20 bit bit wides.

The elastic buffer of the Chang Banman pattern of this paper design; Its structure is shown in 4, and its structure can be divided into the input detection module, the SKP removing module; Scale-of-two and Gray code read-write pointer generation module; Gray code read-write pointer synchronization module between two clock zones, read-write control module, the threshold monitor module and the output control module of valid data in the judgement elastic buffer.

The input detection module is responsible for detecting in 40 Bit datas of input whether comprise SKP; Provide indicator signal if comprise SKP in the input data; The deletion that this indicator signal and threshold monitoring device module provide is perhaps inserted the SKP signal together, is used for controlling deletion or the insertion that read-write control unit is accomplished SKP.

The SKP removing module is responsible for 20 bit SKP in deletion input 40 bits, and its principle will be introduced in this patent is follow-up.

Read-write pointer generation module, the address of generation is used as the address of storage unit access, also is used for producing the full empty number that indicates and judge data among the FIFO of FIFO.The address comprises two kinds of scale-of-two and Gray codes.

Lock unit is used for the Gray code read pointer of reading clock zone is synchronized to and writes in the clock zone, the Gray code write pointer of writing clock zone is synchronized to reads in the clock zone.The read-write Gray code read-write pointer that is synchronized to corresponding clock zone is used for producing the full empty sign of FIFO.

The threshold monitoring module is used for judging the number of data among the FIFO, when the data in the elastic buffer are less than when equaling 6, adds SKP, and the add_skp signal is effective, and as the deletion SKP more than or equal to 10 time of the data in the elastic buffer, the dele_skp signal is effective.

Whether the write pointer control module is effective according to dele_skp or add_skp signal, accomplishes the function that deletion is imported the SKP in the data or in elastic buffer, inserted new SKP.Output control module and write pointer control module are accomplished the insertion function of SKP together.

The read pointer control module is controlled according to the symbol_lock signal and to be read enable signal and control and read enable signal.

The design of input detection module

The function of input detection module is to detect in the input data whether comprise SKP, and based on valid data number in this moment elastic buffer, selects whether to delete the SKP of input or insert new SKP.For the SKP that makes new insertion satisfies the 8B10B coding requirement, also should preserve the operation difference parameter of input SKP.

Read-write pointer generation module and synchronization module design

When the valid data number expires empty sign with generation in judging elastic buffer,, can not the pointer of two clock zones directly be compared, can produce bigger metastable state like this because the read-write of asynchronous FIFO is controlled by asynchronous clock.Utilize binary code and gray code pointer generation module in this paper design, produce binary code and Gray code, wherein with the address input of binary code as storage unit.Read pointer with Gray code; With writing clock sampling twice; Promptly be synchronized to and write in the clock zone, because Gray code only changes one at every turn, so through after synchronous through two registers of writing clock control; Can metastable possibility be dropped to minimum, then with write pointer be synchronized to the read pointer of writing clock zone and do and relatively produce the full sign of FIFO.Equally, write pointer is synchronized to the sign of reading to produce in the clock zone FIFO sky.This paper adopts new full empty sign production method; Only will read and write time high-order address of arriving lowest order as storage unit of pointer address; Elastic buffer is empty when read/write address is identical, when read-write pointer most significant digit different and all the other all when identical elastic buffer for full.

The threshold monitor modular design

The function of threshold monitor module is the valid data number that is used for judging elastic buffer; Directly can't judge the data in the buffering with Gray code; Therefore, need to be synchronized to the write pointer that the Gray code read pointer of writing in the clock zone is converted into binary code and binary code and relatively judge the valid data in the elastic buffer.Because the read pointer of binary code converts by being synchronized to the read pointer of writing the Gray code in the clock zone, can not produce metastable problem this moment.When the data in the elastic buffer are less than when equaling 6, add SKP, (add skp adds skp to add_skp; Be exactly a signal wire, design is exactly the lead of realizing at the employing silicon that physically exists through after the processing of microelectronic technique; With software very big difference being arranged, is not the order of software) signal is effective, as the deletion SKP more than or equal to 10 time of the data in the elastic buffer; Dele_skp (delete skp deletes skp) signal is effective.

Write pointer control module, SKP removing module and output control module design

The write pointer control module, the function of the control of responsible write address.The SKP removing module is responsible for deleting the SKP in input 40 Bit datas.In since USB3.0 in, the SKP sequence sets is 2 continuous SKP, the bit wide of SKP sequence sets is 20 bits.In the present invention, the data bit width of elastic buffer is 40 bits, has solved the problem of SKP sequence sets how to delete input.

The elastic buffer of 40 bits of the present invention's design is realized through the SKP removing module the deletion of SKP sequence sets.Can realize 20 bit SKP in the 40 bits input data are weeded out.The principle of SKP removing module is as shown in Figure 5.

The SKP removing module be input as 40 Bit datas; Exist the maintenance register (hold register) of one 80 bit to be used for keeping in the data of importing; When deletion SKP threshold signal dele_skp is invalid, need not delete SKP, because the input and output data of hold register are 40 bits; Therefore; The input data that always keep 8 bytes among the hold register, and the data of high 4 bytes of hold register are the write data of ram as output; The input data constantly write on low 40 bits of hold register, simultaneously the data shift of low 40 bits of hold register to high 40 bits of hold register as output.The displacement of whole hold register from the data of low 40 bits to the data of high 40 bits is equivalent to shift register.Simultaneously, the counter hr_cnt (hold register counter keeps data number in the register) that also defines the number of a byte among the hold register is used for writing down the byte number that exist among the hold register this moment.

When the dele_skp signal is effective, need the SKP in the deletion input data.When having the SKP of 20 bits in the data of input, after the template (mask) of input data through rejecting SKP, SKP is rejected; Only effective 20 Bit datas are written among the hold register; Data among this moment hold register are 60 bits, if when next clock period, the data of input do not comprise SKP; Keep 6 data constant so among the hold register, the value of Hr_cnt remains 6.If after a period of time; The SKP that comprises 20 bits in the input data again; And this moment, the dele_skp signal was still effective, and the mask module will be rejected the SKP that imports in the data so, and the valid data of 20 bits are written among the hold register; At this moment, the data of residue 40 bits among the hold register.When the value that detects hr_cnt is 4; Deletion SKP module is with dele_skp_en (delete skp enable; Deletion skp enable signal) signal is effective; Make and write an invalid clock period of enable signal, be not written to high 40 Bit datas among this moment hold register among the ram, kept high 40 Bit datas among the hold register.If this moment, the data of input did not comprise SKP, 80 Bit datas have been recovered again among the hold register so.Through above processing, the deletion that this module is successful import 20 bit SKP in 40 Bit datas, realized of the deletion of 40 bit elastic buffers to 20 bit SKP.Deletion SKP module input and output sequential is as shown in Figure 6.

When the add_skp signal is effective, and the input detection module data that detect input according to the data number of elastic buffer, are inserted new SKP when being SKP.SKP adds by the breakpoint preservation, and write pointer jumps and shakes hands and output control module is realized.

Occur and add the threshold values sign when effective at the SKP window; Write pointer calculates the valid data number among the FIFO at this moment; According to the number of valid data among the FIFO and 8 gap; Decide write_addr_b (binary write address, binary write address) next pointer point pointed, under the control of write pointer module, accomplish the jump of write pointer; Be write pointer jump (write pointer jump); And be saved in current write pointer and next pointer point among current_write_addr_b (current binary write address, current binary write address) and the next _ write_addr_b (next binary write address, next binary write address) writing clock zone.Simultaneously provide inform_rp (inform read pointer, notice read pointer) signal writing clock zone, because read pointer always lags behind write pointer; When read pointer was read the start address of breakpoint, inser_skp_en (insert skp enable inserts skp and enables) signal was effective; And feedback ack (acknowledgement; Reply) signal, detect the ack signal and cancel the inform_rp signal when effective when writing clock zone, output control module detect the inser_skp_en signal effectively after; RD (running disparity according to the SKP that imports this moment; The operation difference parameter is the value that in the 8b10b encoding and decoding, defines) value insert new SKP, output control module guarantees to insert the requirement that all SKP all satisfy the 8B10B coding; When read pointer was read the end address of breakpoint, it is invalid that the inser_skp_en signal becomes, and cancels the ack signal simultaneously, accomplishes the insertion of SKP, makes FIFO keep half-full state.

Inform_rp here and ack signal are a pair of handshake, have guaranteed that a write pointer jumps in the insertion of reading a SKP of clock zone completion, has avoided in the read pointer territory, repeating to insert skp.

The read pointer control module

The function of read pointer control module is that enable signal is read in control, and as symbol lock (symbol lock) when signal is effective, write clock and begin in FIFO, to write data this moment; Read to enable to wait until that FIFO could be effectively after writing 8 data, after symbol lock was invalid, promptly a packet had received and has finished; Write enable invalid, but this moment read to enable not necessarily invalid at once, till FIFO is read sky; All data all have been synchronized to this locality, and it is just invalid to read to enable.

The emulation of elastic buffer design

This paper adopts Verilog HDL design flexibility buffering, makes the simulating, verifying of function of NC-Verilog.

The design adopts the technology library of the TSMC 65nm of Taiwan Semiconductor Manufacturing Co. to carry out comprehensively with Design Compiler, and gives comparatively conservative temporal constraint, and the clock frequency of read-write all can reach 125MHZ.And carry out the place and route of rear end with Encounter, and obtain accurate time sequence information, adopt Prime Time to carry out static timing analysis then, finally adopt NC-Verilog to do sequential emulation, the sequential of deletion SKP is as shown in Figure 7.

Simulation result shows; The elastic buffer of this paper design can be correct write and sense data, can correctly delete and insert SKP, the SKP of insertion satisfies the requirement of 8B10B coding; The full empty sign of generation elastic buffer that can be correct, and can be between two clock zones synchrodata.Design meets the requirement of USB3.0 agreement fully, has verified the reliability of this paper design.

The above only is a preferred implementation of the present invention; Should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the present invention's design; Can also make some improvement and retouching, these improvement and retouching also should be regarded as in the protection domain of the present invention.

Claims

1. an elastic buffer structure that is applied to USB3.0 is characterized in that, comprises input detection module, binary code and Gray code read-write pointer generation module, synchronization module, read-write control module, threshold monitoring module and output control module;

Said binary code and Gray code read-write pointer generation module are responsible for producing binary code and the Gray code read-write pointer of FIFO;

Said threshold monitoring module will be synchronized to the Gray code read pointer of writing in the clock zone and be converted into binary code and relatively judge the valid data among the FIFO with the write pointer of binary code; When the data among the FIFO are less than when equaling 6; Add SKP; The add_skp signal is effective, when the data among the FIFO more than or equal to 10 time deletion SKP, the dele_skp signal is effective;

2. a kind of elastic buffer structure that is applied to USB3.0 according to claim 1 is characterized in that, said FIFO realizes through the SKP removing module the deletion of SKP.

3. a kind of elastic buffer structure that is applied to USB3.0 according to claim 1 is characterized in that, said FIFO preserves the breakpoint that is inserted through of SKP, and write pointer jumps and shakes hands and output control module is realized.

4. elastic buffer method that is applied to USB3.0; It is characterized in that; Comprise the steps: said input detection module is responsible for detecting in the input data whether comprise SKP to FIFO input data, provides indicator signal if comprise SKP in the input data; The deletion that this indicator signal and threshold monitoring module provide is perhaps inserted the SKP signal together, is used for controlling deletion or the insertion that the read-write control module is accomplished SKP;

The Gray code that said synchronization module utilizes said binary code and Gray code read-write pointer generation module to produce realize Gray code read-write pointer between the read-write clock zone synchronously; The binary code that said binary code and Gray code read-write pointer generation module produce is as the address input of storage unit; Read pointer with Gray code; Be synchronized to through two registers of writing clock control and write in the clock zone; Then with write pointer be synchronized to the read pointer of writing clock zone and do and relatively produce the full sign of FIFO, write pointer is synchronized to reads to produce in the clock zone the empty sign of FIFO; Time high-order with the read-write pointer address to the address of lowest order as storage unit, FIFO be empty when read/write address is identical, when read-write pointer most significant digit different and all the other all when identical FIFO for expiring;

5. method according to claim 4 is characterized in that, the SKP in the said deletion input data specifically comprises the steps; With being used for the temporary data of importing deletion SKP module in the maintenance register; When deletion SKP threshold signal dele_skp is invalid; Need not delete SKP; Keep the input and output data bit number average of register identical with the data of input deletion SKP module, the data of said maintenance register upper byte are the write data of ram as output; The data of input write on the low byte that keeps register, the data shift of low byte that keeps register simultaneously on the upper byte as output; Simultaneously, the counter hr_cnt record of the number through keeping the byte in the register keeps the byte number that exists in the register this moment;

When deletion SKP threshold signal dele_skp signal is effective, and import when having SKP in the data of deleting the SKP module, after the input data process deletion SKP module; SKP is rejected, only valid data are written in the low byte that keeps register, if when next clock period; The data of input do not comprise SKP, keep keeping in the register original data number constant so, if after a period of time; If comprise SKP again in the data of input, and this moment, the dele_skp signal was still effective, then deleted the SKP module and rejected SKP in the data; Valid data are written in the maintenance register, and the storage data are a half of its entire capacity in the register if keep; It is effective with the dele_skp_en signal then to delete the SKP module, makes to write an invalid clock period of enable signal, and data are not written among the ram in the register keeping.

6. method according to claim 4 is characterized in that, the SKP in the said insertion input data specifically comprises the steps; Write pointer calculates the valid data number among the FIFO; According to the number of valid data among the FIFO and the gap of the full up data number of FIFO; Decision binary write address next pointer point pointed; Under the control of write pointer module, accomplish the jump of write pointer, be write pointer and jump, and be saved in current write pointer and next pointer point in current binary write address and the next binary write address writing clock zone; Writing clock zone to putting up a notice the read pointer signal simultaneously; When read pointer was read the start address of breakpoint, it was effective to insert the skp enable signal, and the feedback answer signal; Detect ack signal notice of cancellation read pointer signal when effective when writing clock zone; Output control module detect insert the skp enable signal effectively after, insert new skp according to the value of the RD operation difference parameter of the skp of input this moment, output control module guarantees to insert the requirement that all skp all satisfy the 8B10B coding; When read pointer was read the end address of breakpoint, it is invalid that insertion skp enable signal becomes, and cancels the ack signal simultaneously, accomplishes the insertion of skp, makes FIFO keep half-full state;