CN102708086B - Elastic buffer structure and method applied to universal serial bus 3.0 (USB 3.0) - Google Patents

Elastic buffer structure and method applied to universal serial bus 3.0 (USB 3.0) Download PDF

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CN102708086B
CN102708086B CN201210145496.2A CN201210145496A CN102708086B CN 102708086 B CN102708086 B CN 102708086B CN 201210145496 A CN201210145496 A CN 201210145496A CN 102708086 B CN102708086 B CN 102708086B
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CN102708086A (en
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朱小明
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WUXI HUADA GUOQI TECHNOLOGY CO LTD
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Abstract

The invention discloses an elastic buffer structure and a method applied to universal serial bus 3.0 (USB 3.0). The elastic buffer structure comprises an input check module, a binary code and Gray code read-write pointer generation module, a synchronization module, a read-write control module, a threshold value monitoring module and an output control module. According to the protocol requirement of the USB 3.0, by means of the analysis of an action mechanism of elastic buffer, asynchronous first in first out (FIFO) which has innovative functions of writing pointer shield, point jumping, breakpoint saving and handshake, output control and the like is used for designing the elastic buffer, and the purpose of clock frequency compensation is well achieved; and according to the designed elastic buffer, parallel 40-bit data are used, the read-write clock frequency can reach 125 MHZ.

Description

A kind of elastic buffer structure and method being applied to USB3.0
Technical field
The present invention relates to a kind of elastic buffer structure being applied to USB3.0.
Background technology
USB (universal serial bus) 3.0(Universal Serial Bus 3.0, USB3.0) be the standard announced in November, 2008 by companies such as Intel, Microsoft, NEC.USB is the new interface technology being applied in PC field in the last few years.Still belong at a high speed relative to USB2.0, USB3.0, serial, the host-host protocol that source is synchronous.Adopt the mode of differential pair to send serial data at transmitting terminal, utilize clock and data recovery circuit (Clock and Data Recovery, CDR) from serial data, recover serial data and clock at receiving end.Transmitting-receiving two-end due to USB3.0 supports independently reference clock source, so the clock frequency that receiving end recovers exists difference with its local clock frequency.In order to compensate the frequency difference of two clocks, need an elastic buffer (Elastic buffer), the clock zone data that CDR recovers effectively are synchronized in local clock territory.
Elastic buffer is by put forward in Maurice Karnaugh in the telephone network transmission pulse coded modulation (Pulse Code Modulation, PCM) signal.Elastic buffer realizes the object of clock compensation by inserting and delete a certain special symbol, and synchrodata between two clock zones that can be stable, therefore, elastic buffer is used in a lot of technology application, such as, all have employed elastic buffer technology in the agreements such as USB, PCIE, Ethernet and carrys out synchrodata.But under USB3.0 agreement, there is no the elastic buffer being applicable to USB3.0 Physical layer.
Summary of the invention
For above-mentioned technical matters, the present invention designs a kind of according to USB3.0 agreement, has designed and Implemented the elastic buffer structure and its method that are applicable to USB3.0 Physical layer.
In order to solve the problems of the technologies described above, technical scheme of the present invention is as follows:
Be applied to an elastic buffer structure of USB3.0, comprise input detection module, binary code and Gray code read-write pointer generation module, synchronization module, Read-write Catrol module, threshold monitoring module and output control module;
Described input detection module is responsible for detecting in input data whether comprise SKP, if comprise SKP in input data, provide indicator signal, the deletion that described indicator signal and described threshold monitoring module provide or insert together with SKP signal, is used for controlling deletion or the insertion that described Read-write Catrol module completes SKP;
Described binary code and Gray code read-write pointer generation module are responsible for the binary code and the Gray code read-write pointer that produce elastic buffer;
The Gray code that described synchronization module utilizes described binary code and Gray code read-write pointer generation module to produce is to realize synchronous between read-write clock zone of Gray code read-write pointer, the binary code that described binary code and Gray code read-write pointer generation module produce inputs as access unit address, by the read pointer of Gray code, through two register synchronization writing clock control to writing in clock zone, then by write pointer be synchronized to the read pointer writing clock zone and compare and produce the full mark of FIFO, write pointer is synchronized to the mark reading to produce FIFO sky in clock zone;
Described threshold monitoring module is converted into binary code by being synchronized to the Gray code read pointer write in clock zone and comparing with the write pointer of binary code the valid data judged in FIFO, when the data in FIFO be less than equal 6 time, add SKP, add_skp signal is effective, SKP, dele_skp signal is deleted effective when the data in FIFO are more than or equal to 10; Whether write pointer control module is effective according to dele_skp or add_skp signal, delete the SKP inputted in data or the function inserting new SKP in FIFO, described output control module completes the insertion function of SKP together with described write pointer control module;
Read pointer control module, controls to read enable signal according to symbol_lock signal.
Further, described FIFO is realized by SKP removing module the deletion of SKP.
Further, the be inserted through breakpoint of described FIFO to SKP is preserved, and write pointer jumps and shakes hands and output control module realizes.
A kind of elastic buffer method being applied to USB3.0; comprise the steps: to input data to FIFO; described input detection module is responsible for detecting in input data whether comprise SKP; if comprise SKP in input data to provide indicator signal; the deletion that this indicator signal and threshold monitoring module provide or insert together with SKP signal, is used for controlling deletion or the insertion that Read-write Catrol module completes SKP;
The Gray code that described synchronization module utilizes described binary code and Gray code read-write pointer generation module to produce is to realize synchronous between read-write clock zone of Gray code read-write pointer, the binary code that described binary code and Gray code read-write pointer generation module produce inputs as access unit address, by the read pointer of Gray code, through two register synchronization writing clock control to writing in clock zone, then by write pointer be synchronized to the read pointer writing clock zone and compare and produce the full mark of FIFO, write pointer is synchronized to the mark reading to produce FIFO sky in clock zone; Using the secondary high-order lowest order that arrives of read-write pointer address as access unit address, when read/write address is identical, FIFO is empty, and when when reading and writing pointer most significant digit difference, all the other all positions are identical, FIFO is full; Described threshold monitoring module is converted into binary code by being synchronized to the Gray code read pointer write in clock zone and comparing with the write pointer of binary code the valid data judged in FIFO, when the data in FIFO be less than equal 6 time, add SKP, add_skp signal is effective, SKP, dele_skp signal is deleted effective when the data in FIFO are more than or equal to 10;
Whether write pointer control module is effective according to dele_skp or add_skp signal, delete the SKP inputted in data or the function inserting new SKP in FIFO, described output control module completes the insertion function of SKP together with described write pointer control module;
Read pointer control module, controls to read enable signal according to symbol_lock signal;
When reading clock faster than writing clock, namely the data read are more than the data of write, SKP is added to FIFO by writing control module, FIFO is made to maintain half-full state, and write pointer carries out hop interval forward, and preserve the position of jump, when read pointer is read between skip zone, by output control module, complete SKP and add;
Be slower than write clock when reading clock, the data namely write are more than the data read, and now, FIFO should delete the SKP in input data, make FIFO remain half-full, regulate clock with this.
Further, the described SKP deleted in input data specifically comprises the steps; With being used for the temporary data inputting deletion SKP module in a holding register, when deleting SKP threshold signal dele_skp and being invalid, do not need to delete SKP, the input and output data bit number of holding register is all identical with the data that SKP module is deleted in input, the data of described holding register upper byte are as output, data are write for ram, in the low byte of the data write holding register of input, the data shifts of the low byte of holding register conduct on upper byte simultaneously exports; Meanwhile, the byte number existed in now holding register is recorded by the counter hr_cnt of the number of the byte in holding register;
When deleting SKP threshold signal dele_skp signal and being effective, and when there is SKP in the data of input deletion SKP module, input data are after deleting SKP module, SKP is rejected, only valid data are written in the low byte of holding register, data now in holding register become 6, because deleted 2 skp in input 4 data.If when the next clock period, the data of input do not comprise SKP, so keep original 6 data constant in holding register, if after a period of time, if comprise SKP again in the data of input, and now dele_skp signal is still effective, then delete SKP module and reject SKP in data, valid data are written in holding register, if store the half that data are its whole capacity in holding register, i.e. 4 data, then delete SKP module by effective for dele_skp_en signal, make a write enable signal invalid clock period, data in holding register are not written in ram, 8 valid data have been recovered again in such holding register.
Further, the described SKP inserted in input data specifically comprises the steps; Write pointer calculates the valid data number in FIFO, according to the number of valid data in FIFO and the gap of the full up data amount check of FIFO, determine the next pointer point pointed by binary write address, the jump of write pointer is completed under the control of write pointer module, be write pointer to jump, and current write pointer and next pointer point be saved in current binary write address and next binary write address writing clock zone; Writing clock zone to read pointer signal of putting up a notice simultaneously, when read pointer reads the start address of breakpoint, insert skp enable signal effective, and feed back answer signal, the notice of cancellation read pointer signal when writing clock zone and detecting that ack signal is effective, after output control module detects that insertion skp enable signal effectively, the value running difference parameter according to the RD of the skp now inputted inserts new skp, and all skp of output control module guarantee insertion all meet the requirement that 8B10B encodes; When read pointer reads the end address of breakpoint, it is invalid that insertion skp enable signal becomes, and cancels ack signal simultaneously, complete the insertion of skp, make FIFO maintain half-full state;
Described read pointer signal and ack signal are a pair handshake, ensure that write pointer jumps reading clock zone and complete the insertion of a SKP, avoid and repeat to insert skp in read pointer territory.
Beneficial effect of the present invention is: adopt synchronous compare to judge the valid data number in elastic buffer, avoid burr and the instability of Asynchronous comparison, have employed a kind of full sky mark production method newly, employing write pointer shields, the mode that write pointer jumps and read-write pointer is shaken hands realizes deletion and the insertion of SKP, by adding the removing module of SKP sequence sets, solve the problem of the SKP sequence sets how deleting 20 bit bit wides in the input data of 40 bits.
Accompanying drawing explanation
Fig. 1 is USB3.0 Physical layer receiving unit structure;
Fig. 2 reads faster than writing in Chang Banman pattern;
Fig. 3 writes faster than reading in Chang Banman pattern;
Fig. 4 is the structure of elastic buffer;
Fig. 5 is SKP removing module schematic diagram;
Fig. 6 is for deleting SKP module input and output sequential chart;
Fig. 7 is the deletion sequential chart of elastic buffer to SKP of 40 bit bit wides.
Embodiment
Below in conjunction with the drawings and specific embodiments, the present invention will be further described.
The action scope of elastic buffer and capacity thereof:
The action scope of elastic buffer
The data transmission of USB3.0 adopts full duplex (Full duplex), and Physical layer has two Difference signal pairs, and be for a pair transmission Difference signal pair, another is to being reception Difference signal pair.Because elastic buffer is only for receiving end, provide the block diagram of the receiving end of the Physical layer of 10 Bit data bit wides as Fig. 1, it comprises differential received, clock data recovery circuit, serioparallel exchange, 8B10B decoding and descrambling circuit etc.As shown in Figure 1, differential signal is received by differential received termination, clock and data are recovered through CDR, then data become the data of 40 bits through serioparallel exchange, being detected the beginning flag symbol K28.5 of bag by sequential detector, when K28.5 being detected, making symbol lock (symbol lock) signal effective, when symbol lock is effective, elastic buffer starts to write data.The clock of writing of elastic buffer is the clock that CDR recovers, and be called receive clock, and it reads the system clock that clock is receiving end.By elastic buffer, the data of receiving clock-domain are effectively synchronized to system clock domain, and through 8B10B decoding and descrambler, data are passed to system.The input data of 8B10B demoder are 40 bits, and exporting data is 32 bits, is equivalent to the 8B10B demoder that cascade 4 is input as 10 bits.
Elastic buffer capacity
In order to compensate the frequency difference of receive clock and system clock, on average often send 354 bytes at transmitting terminal and insert a SKP sequence pair (SKP ordered set), a SKP ordered set is by 2 SKP(K28.1) form, delete or insert SKP ordered set when receiving end elastic buffer detects SKP ordered set according to the number of data in now elastic buffer.Because the transmission of USB3.0 and receiving end adopt independently reference clock, so the receive clock recovered by CDR at receiving end and local system clock have a clock jitter.In order to mate the frequency difference at two ends, needing an elastic buffer, reaching rate-matched by inserting and delete SKP.
The reference clock precision-300 of the present invention's design is 1,000,000/to+300ppm(ppm unit), the clock of spread spectrum clock (Spread Spectrum Clocking) is changed to-5000ppm to 0, therefore, the clock jitter of transmitting terminal and receiving end is-5300ppm to 300ppm, and maximum deviation is 5600ppm.No matter reference clock frequency how, and deviation is between the two 5600*0.000001=0.0056T.In USB3.0, maximum data packet length is 1056 bytes, and protocol requirement can not insert SKP in a packet.When the poorest, the maximum data deviation of two clock transmission data is: (T*1056*10-T(1-0.0056) * 1056*10)/T=59 bit=8 byte, and take advantage of 10 to be consider 8b/10b coding here, therefore elastic buffer capacity is minimum is 8 bytes.
The elastic buffer degree of depth is the data amount check that it can be deposited, known by calculating, and the degree of depth of elastic buffer should be 8.Design herein adopts Chang Banman (Normal half full) pattern to carry out design flexibility buffering, and its capacity is 16, has 8 data under normal conditions in elastic buffer, and remaining 8 is cushion space, therefore claims Chang Banman.First Chang Banman pattern will write 8 data in elastic buffer, reaches half-full, then reads effectively enable, when Chang Banman pattern only occurs SKP couple in symbol queue, could add or delete SKP couple.
The principle of elastic buffer and structure:
Embodiment one:
Be the principle of elastic buffer below, for 40 bits, no matter 10 bits, 20 bits or 40 bits, its principle is identical.
The principle of elastic buffer:
Elastic buffer is in fact an asynchronous FIFO, and it writes clock is receive clock, and reading clock is system clock, data bit width is 40 bits, and the FIFO degree of depth is 16, when symbol lock is effective, in receiving clock-domain, in FIFO, write 8 data from deserializer.When the same speed of read-write clock, there are 8 valid data in FIFO, maintain half-full state.
When reading clock faster than writing clock, the data of reading, more than the data of write, through causing the data bulk in FIFO to be less than 8 after a period of time, are even likely read sky.As shown in Figure 2, when there is SKP in the data of input 40 bit, in FIFO, valid data are 4, fewer than normality 4.Now, elastic buffer should add 4 SKP, makes FIFO maintain half-full state, regulates clock with this.Now write pointer skip-forwards 4 intervals, and preserve the position of jump, when read pointer is read between skip zone, controlling by exporting, completing SKP and adding, that is, the SKP newly inserted is not write in FIFO really, address date in skip zone is invalid data, and the SKP added must meet the requirement running difference parameter (Running Disparity), otherwise can cause makeing mistakes during 8B10B decoding.
Be slower than write clock when reading clock, the data of write more than the data read, through after a period of time by the data bulk that causes in FIFO more than 8, be even likely fully written.As shown in Figure 3, when there is SKP in input data, in FIFO, valid data are 10, and more than normality 2. now, and elastic buffer should delete the SKP in input data, make FIFO remain half-full, regulate clock with this.
In the process of elastic buffer Read-write Catrol, write prior to reading.After data in FIFO reach 8, read-write effectively simultaneously.When writing end, namely a bag receives, but reads not necessarily to terminate, until read sky, namely all data have been synchronized in local system clock territory, represents that this time read-write subtask terminates.This Row control just maintains the integrality of system data.
The structural design of elastic buffer:
The present invention adopts synchronous compare to judge the valid data number in elastic buffer, avoid burr and the instability of Asynchronous comparison, have employed a kind of full sky mark production method newly, adopt write pointer shielding, the mode that write pointer jumps and read-write pointer is shaken hands realizes deletion and the insertion of SKP.Another one innovation is the removing module adding SKP sequence sets herein, solves the problem of the SKP sequence sets how deleting 20 bit bit wides in the input data of 40 bits.
The elastic buffer of the Chang Banman pattern designed herein, its structure as indicated at 4, its structure can be divided into input detection module, SKP removing module, scale-of-two and Gray code read-write pointer generation module, Gray code read-write pointer synchronization module between two clock zones, Read-write Catrol module, judges threshold monitor module and the output control module of valid data in elastic buffer.
Input detection module is responsible for whether comprising SKP in 40 Bit datas of detection input, if comprise SKP in input data to provide indicator signal, the deletion that this indicator signal and threshold monitoring device module provide or insert together with SKP signal, is used for controlling deletion or the insertion that read-write control unit completes SKP.
SKP removing module, be responsible for deleting 20 bit SKP in input 40 bit, its principle will continue at this patent subsequent intermediary.
Read-write pointer generation module, the address of generation is used as the address of storage unit access, is also used for producing the full sky mark of FIFO and judging the number of data in FIFO.Address comprises scale-of-two and Gray code two kinds.
Lock unit is used for the Gray code read pointer reading clock zone to be synchronized to write in clock zone, is synchronized to by the Gray code write pointer writing clock zone and reads in clock zone.The read-write Gray code read-write pointer being synchronized to corresponding clock zone is used for producing the full empty mark of FIFO.
Threshold monitoring module is used for judging the number of data in FIFO, when the data in elastic buffer be less than equal 6 time, add SKP, add_skp signal effective, delete SKP, dele_skp signal when the data in elastic buffer are more than or equal to 10 effective.
Whether write pointer control module is effective according to dele_skp or add_skp signal, deletes the SKP inputted in data or the function inserting new SKP in elastic buffer.Output control module completes the insertion function of SKP together with write pointer control module.
Read pointer control module, controls to read enable signal to control to read enable signal according to symbol_lock signal.
The design of input detection module
The function of input detection module detects in input data whether comprise SKP, and according to valid data number in now elastic buffer, selects whether to delete the SKP of input or insert new SKP.In order to make the new SKP inserted meet 8B10B coding requirement, the operation difference parameter of input SKP also should be preserved.
Read-write pointer generation module and synchronization module design
When judging that in elastic buffer, valid data number and the full sky of generation indicate, because the read-write of asynchronous FIFO is controlled by asynchronous clock, the pointer of two clock zones directly can not be compared, larger metastable state can be produced like this.Utilize binary code and gray code pointer generation module in design herein, produce binary code and Gray code, wherein input as access unit address with binary code.By the read pointer of Gray code, with writing clock sampling twice, namely through two register synchronization writing clock control to writing in clock zone, due to Gray code only change one at every turn, therefore after synchronous, can metastable possibility be dropped to minimum, then by write pointer be synchronized to the read pointer writing clock zone and compare and produce the full mark of FIFO.Equally, write pointer is synchronized to the mark reading to produce FIFO sky in clock zone.Adopt new full sky mark production method herein, only a time high position for read-write pointer address is arrived lowest order as access unit address, when read/write address is identical, elastic buffer is empty, and when when reading and writing pointer most significant digit difference, all the other all positions are identical, elastic buffer is full.
Threshold monitor modular design
The function of threshold monitor module is used to the valid data number judging elastic buffer, direct Gray code cannot judge the data in buffering, therefore, binary code need be converted into compare being synchronized to the Gray code read pointer write in clock zone with the write pointer of binary code the valid data judged in elastic buffer.Because the read pointer of binary code is converted by the read pointer being synchronized to the Gray code write in clock zone, now can not the problem of generating metastable.When the data in elastic buffer be less than equal 6 time, add SKP, add_skp(add skp, add skp, being exactly a signal wire, designing after the processing of microelectronic technique, is exactly the wire of the employing silicon realization existed physically, make a big difference with software, the order of software) signal is effective, deletes SKP, dele_skp(delete skp when the data in elastic buffer are more than or equal to 10, delete skp) signal is effective.
Write pointer control module, SKP removing module and output control module design
Write pointer control module, is responsible for the function of the control of write address.SKP removing module is responsible for deleting the SKP in input 40 Bit data.In due in USB3.0, SKP sequence sets is 2 continuous print SKP, and the bit wide of SKP sequence sets is 20 bits.In the present invention, the data bit width of elastic buffer is 40 bits, solves the problem of the SKP sequence sets how deleting input.
The elastic buffer of 40 bits of the present invention's design is realized by SKP removing module the deletion of SKP sequence sets.20 bit SKP in 40 bit input data can be realized to weed out.The principle of SKP removing module as shown in Figure 5.
SKP removing module be input as 40 Bit datas, the holding register (hold register) that there are 80 bits is used for keeping in the data inputted, when deleting SKP threshold signal dele_skp and being invalid, do not need to delete SKP, because the input and output data of hold register are 40 bits, therefore, keep the input data of 8 bytes in hold register always, and the data of high 4 bytes of hold register are as output, data are write for ram, input data constantly write on low 40 bits of hold register, the data shifts of low 40 bits of hold register conduct to high 40 bits of hold register simultaneously exports.Whole hold register, from the data of low 40 bits to the displacement of the data of high 40 bits, is equivalent to shift register.Meanwhile, the counter hr_cnt(hold register counter of the number of the byte in a hold register is also defined, data amount check in holding register) be used for recording the byte number existed in now hold register.
When dele_skp signal is effective, need to delete the SKP in input data.When there is the SKP of 20 bits in the data inputted, input data are after rejecting the template (mask) of SKP, SKP is rejected, only effective 20 Bit datas are written in hold register, data now in hold register are 60 bits, if when the next clock period, the data of input do not comprise SKP, so keep 6 data constant in hold register, the value of Hr_cnt remains 6.If after a period of time, the SKP of 20 bits is comprised again in input data, and now dele_skp signal is still effective, so mask module will reject the SKP inputted in data, the valid data of 20 bits are written in hold register, now, the data of 40 bits are remained in hold register.When value hr_cnt being detected is 4, delete SKP module by dele_skp_en(delete skp enable, delete skp enable signal) signal is effective, make a write enable signal invalid clock period, high 40 Bit datas in now hold register are not written in ram, remain high 40 Bit datas in hold register.If the data now inputted do not comprise SKP, so 80 Bit datas are recovered again in hold register.Through above process, this module successfully deletes 20 bit SKP in input 40 Bit data, achieves the deletion of 40 bit elastic buffers to 20 bit SKP.Delete SKP module input and output sequential as shown in Figure 6.
When add_skp signal is effective, and input detection module when detecting that the data of input are SKP, according to the data amount check of elastic buffer, insert new SKP.SKP interpolation is preserved by breakpoint, and write pointer jumps and shakes hands and output control module realizes.
When SKP window occurs and interpolation threshold values mark is effective, write pointer now calculates the valid data number in FIFO, according to the number of valid data in FIFO and the gap of 8, decide write_addr_b(binary write address, binary write address) pointed by next pointer point, the jump of write pointer is completed under the control of write pointer module, be write pointer and jump (write pointer jump), and current write pointer and next pointer point are saved in current_write_addr_b(current binary write address writing clock zone, current binary write address) and next _ write_addr_b(next binary write address, next binary write address) in.Simultaneously provide inform_rp(inform read pointer writing clock zone, notice read pointer) signal, because read pointer always lags behind write pointer, when read pointer reads the start address of breakpoint, inser_skp_en(insert skp enable, inserting skp enable) signal is effective, and feed back ack(acknowledgement, response) signal, inform_rp signal is cancelled when writing clock zone and detecting that ack signal is effective, after output control module detects that inser_skp_en signal effectively, according to the RD(running disparity of the SKP now inputted, run difference parameter, the value defined in 8b10b encoding and decoding) value insert new SKP, output control module ensures to insert the requirement that all SKP all meet 8B10B coding, when read pointer reads the end address of breakpoint, it is invalid that inser_skp_en signal becomes, and cancels ack signal simultaneously, completes the insertion of SKP, makes FIFO maintain half-full state.
Here inform_rp and ack signal is a pair handshake, ensure that write pointer jumps reading clock zone and complete the insertion of a SKP, avoids and repeat to insert skp in read pointer territory.
Read pointer control module
The function of read pointer control module controls to read enable signal, when symbol lock(symbol lock) signal effective time, now write clock to start to write data in FIFO, read enable needs and wait until that FIFO could be effective after writing 8 data, after symbol lock is invalid, namely a packet receives, it is enable invalid to write, but now read enable not necessarily invalid at once, until FIFO is read sky, all data are all synchronized to this locality, read enable ability invalid.
The emulation of elastic buffer design
Adopt Verilog HDL design flexibility buffering herein, make the simulating, verifying of function of NC-Verilog.
The design adopts the technology library Design Compiler of Taiwan Semiconductor Manufacturing Co. TSMC 65nm to carry out comprehensively, and gives the temporal constraint comparatively guarded, and the clock frequency of read-write all can reach 125MHZ.And the place and route of rear end is carried out with Encounter, obtain accurate time sequence information, then adopt Prime Time to carry out static timing analysis, the final NC-Verilog that adopts does time stimulatiom, deletes the sequential of SKP as shown in Figure 7.
Simulation result shows, the elastic buffer designed herein can be correct writing and reading data, can correctly delete and insert SKP, the SKP of insertion meets the requirement of 8B10B coding, the full empty mark of generation elastic buffer that can be correct, and can between two clock zones synchrodata.Design meets the requirement of USB3.0 agreement completely, demonstrates the reliability designed herein.
The above is only the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, without departing from the inventive concept of the premise; can also make some improvements and modifications, these improvements and modifications also should be considered as in scope.

Claims (4)

1. be applied to an elastic buffer structure of USB3.0, it is characterized in that, comprise input detection module, binary code and Gray code read-write pointer generation module, synchronization module, Read-write Catrol module, threshold monitoring module and output control module;
Described input detection module is responsible for detecting in input data whether comprise SKP, if comprise SKP in input data, provide indicator signal, the deletion that described indicator signal and described threshold monitoring module provide or insert together with SKP signal, is used for controlling deletion or the insertion that described Read-write Catrol module completes SKP;
Described binary code and Gray code read-write pointer generation module are responsible for the binary code and the Gray code read-write pointer that produce FIFO;
The Gray code that described synchronization module utilizes described binary code and Gray code read-write pointer generation module to produce is to realize synchronous between read-write clock zone of Gray code read-write pointer, the binary code that described binary code and Gray code read-write pointer generation module produce inputs as access unit address, by the read pointer of Gray code, through two register synchronization writing clock control to writing in clock zone, then by write pointer be synchronized to the read pointer writing clock zone and compare and produce the full mark of FIFO, write pointer is synchronized to the mark reading to produce FIFO sky in clock zone;
Described threshold monitoring module is converted into binary code by being synchronized to the Gray code read pointer write in clock zone and comparing with the write pointer of binary code the valid data judged in FIFO, when the data in FIFO be less than equal 6 time, add SKP, add_skp signal is effective, SKP, dele_skp signal is deleted effective when the data in FIFO are more than or equal to 10;
Whether write pointer control module is effective according to dele_skp or add_skp signal, delete the SKP inputted in data or the function inserting new SKP in FIFO, described output control module completes the insertion function of SKP together with write pointer control module, wherein said FIFO is realized by SKP removing module the deletion of SKP, a described SKP removing module holding register keeps in the data that SKP module is deleted in input, when dele_skp is invalid, do not need to delete SKP, the input and output data bit number of holding register is all identical with the data that SKP module is deleted in input, the data of described holding register upper byte are as output, data are write for RAM, in the low byte of the data write holding register of input, the data shifts of the low byte of holding register conduct on upper byte simultaneously exports, meanwhile, the byte number existed in now holding register is recorded by the counter hr_cnt of the number of the byte in holding register, when dele_skp signal is effective, and when there is SKP in the data of input deletion SKP module, input data are after deleting SKP module, SKP is rejected, only valid data are written in the low byte of holding register, if when the next clock period, the data of input do not comprise SKP, so keep original data amount check constant in holding register, if after a period of time, if comprise SKP again in the data of input, and now dele_skp signal is still effective, then delete SKP module and reject SKP in data, valid data are written in holding register, if store the half that data are its whole capacity in holding register, then delete SKP module by effective for dele_skp_en signal, make a write enable signal invalid clock period, data in holding register are not written in RAM,
Read pointer control module, controls to read enable signal according to symbol_lock signal.
2. according to a kind of elastic buffer structure being applied to USB3.0 described in claim 1, it is characterized in that, the be inserted through breakpoint of described FIFO to SKP is preserved, and write pointer jumps and shakes hands and output control module realizes.
3. one kind is applied to the elastic buffer method of USB3.0; it is characterized in that; comprise the steps: to input data to FIFO; input detection module is responsible for detecting in input data whether comprise SKP; if comprise SKP in input data to provide indicator signal; the deletion that this indicator signal and threshold monitoring module provide or insert together with SKP signal, is used for controlling deletion or the insertion that Read-write Catrol module completes SKP;
The Gray code that synchronization module utilizes binary code and Gray code read-write pointer generation module to produce is to realize synchronous between read-write clock zone of Gray code read-write pointer, the binary code that binary code and Gray code read-write pointer generation module produce inputs as access unit address, by the read pointer of Gray code, through two register synchronization writing clock control to writing in clock zone, then by write pointer be synchronized to the read pointer writing clock zone and compare and produce the full mark of FIFO, write pointer is synchronized to the mark reading to produce FIFO sky in clock zone; Using the secondary high-order lowest order that arrives of read-write pointer address as access unit address, when read/write address is identical, FIFO is empty, and when when reading and writing pointer most significant digit difference, all the other all positions are identical, FIFO is full;
Threshold monitoring module is converted into binary code by being synchronized to the Gray code read pointer write in clock zone and comparing with the write pointer of binary code the valid data judged in FIFO, when the data in FIFO be less than equal 6 time, add SKP, add_skp signal is effective, SKP, dele_skp signal is deleted effective when the data in FIFO are more than or equal to 10;
Whether write pointer control module is effective according to dele_skp or add_skp signal, delete the SKP inputted in data or the function inserting new SKP in FIFO, output control module completes the insertion function of SKP together with described write pointer control module;
Read pointer control module, controls to read enable signal according to symbol_lock signal;
When reading clock faster than writing clock, and the data read are more than the data of write, SKP is added to FIFO by writing control module, FIFO is made to maintain half-full state, and write pointer carries out hop interval forward, and preserve the position of jump, when read pointer is read between skip zone, by output control module, complete SKP and add;
Be slower than write clock when reading clock, and the data of write are more than the data read, now, FIFO should delete the SKP in input data, FIFO is made to remain half-full, clock is regulated with this, wherein, the SKP deleted in input data specifically comprises the steps: to keep in a holding register data that SKP module is deleted in input, when dele_skp is invalid, do not need to delete SKP, the input and output data bit number of holding register is all identical with the data that SKP module is deleted in input, the data of described holding register upper byte are as output, data are write for RAM, in the low byte of the data write holding register of input, the data shifts of the low byte of holding register conduct on upper byte simultaneously exports, meanwhile, the byte number existed in now holding register is recorded by the counter hr_cnt of the number of the byte in holding register, when dele_skp signal is effective, and when there is SKP in the data of input deletion SKP module, input data are after deleting SKP module, SKP is rejected, only valid data are written in the low byte of holding register, if when the next clock period, the data of input do not comprise SKP, so keep original data amount check constant in holding register, if after a period of time, if comprise SKP again in the data of input, and now dele_skp signal is still effective, then delete SKP module and reject SKP in data, valid data are written in holding register, if store the half that data are its whole capacity in holding register, then delete SKP module by effective for dele_skp_en signal, make a write enable signal invalid clock period, data in holding register are not written in RAM.
4. method according to claim 3, it is characterized in that, the SKP inserted in input data specifically comprises the steps: that write pointer calculates the valid data number in FIFO, according to the number of valid data in FIFO and the gap of the full up data amount check of FIFO, determine the next pointer point pointed by binary write address, the jump of write pointer is completed under the control of write pointer module, be write pointer to jump, and current write pointer and next pointer point be saved in current binary write address and next binary write address writing clock zone; Writing clock zone to read pointer signal of putting up a notice simultaneously, when read pointer reads the start address of breakpoint, insert SKP enable signal effective, and feed back answer signal, the notice of cancellation read pointer signal when writing clock zone and detecting that ack signal is effective, after output control module detects that insertion SKP enable signal effectively, the value running difference parameter according to the RD of the SKP now inputted inserts new skp, and all skp of output control module guarantee insertion all meet the requirement that 8B10B encodes; When read pointer reads the end address of breakpoint, it is invalid that insertion SKP enable signal becomes, and cancels ack signal simultaneously, complete the insertion of SKP, make FIFO maintain half-full state; Described read pointer signal and ack signal are a pair handshake, ensure that write pointer jumps reading clock zone and complete the insertion of a SKP, avoid and repeat to insert SKP in read pointer territory.
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