KR0124176B1 - Header Data Error Checking Circuit of Split and Reassembly Protocol Data Unit in Asynchronous Transfer Mode Adaptive Layer-1 Type of Receiver - Google Patents

Abstract

The present invention relates to a header data error checking circuit capable of fast and stable error checking by performing error checking on CRC and parity check data received with a simple hardware structure in an ATM type receiving apparatus. For this purpose, the circuit is characterized in that the header data composed of the sequence number area and the sequence number protection area in the disassembly and reassembly protocol data unit of the asynchronous transmission mode adaptive layer-1 type existing between the higher protocol and the asynchronous transmission mode layer of the receiving apparatus. An error checking circuit comprising: an error checking unit for checking whether an error has occurred for a sequence number by comparing a clock signal applied in a disassembly and reassembly protocol data unit with a sequence number (SN) transmitted through a sequence number area; Pre-predicted predetermined cyclic redundancy check and parity check data, and pre-stored cyclic redundancy when a 1-bit convergence layer layer identifier (CSI) and a 3-bit sequence number (SN) are transmitted through the sequence number area. A table for reading corresponding data among the double check and parity check data; The first comparator for checking whether an error occurs in the cyclic redundancy check and parity check data by comparing the cyclic redundancy check and parity check data transmitted through the sequence number protection area with the cyclic redundancy check and parity check data read from the table. It is configured to include.

Description

Header Data Error Checking Circuit of Split and Reassembly Protocol Data Unit in Asynchronous Transfer Mode Adaptive Layer-1 Type of Receiver

1 is a block diagram of a partitioning and reassembly protocol data unit (SAR-PDU) of the asynchronous electric mode adaptive layer-1 (AAL-1) type.

2 is a block diagram of a header data error checking circuit according to the present invention.

3 is a detailed circuit diagram of a sequence number error check unit shown in FIG.

* Explanation of symbols for the main parts of the drawings

21: sequence number error check unit 22: cyclic redundancy check and parity check error check unit

23: cyclic redundancy test and parity check table 24: first comparator

31: counter 32: second comparator

The present invention relates to an error for header data of an Asynchronous Adaptation Layer-1 (AAL-1) type of a receiving apparatus in a communication system using an Asynchronous Transfer Mode (hereinafter referred to as ATM). And a header data error check circuit for fast and stable checking of errors with respect to header data of a segmentation and reassembly-protocol data unit (SAR-PDU). will be.

The communication system based on ATM has emerged as a realization of the BISDN (Broadband Integrated Services Digital Network), and is a system for transmitting data by integrating the digital communication mode and the packet mode communication method of the existing circuit mode. In this asynchronous transmission mode communication system, processing steps are divided into a physical layer, an ATM layer, an ATM adaptation layer (hereinafter referred to as an AAL), and a higher protocol.

ALL is the middle layer of the upper protocol, which is the ATM layer and the high-level user service layer. The ALL layer serves to bridge the difference between services between the ATM layer and the upper protocol. The convergence sublayer (CS) and the SAR layer It consists of.

These AALs are classified into various types according to whether or not the bit rate is constant, real-time, connectivity, etc. In the case of the AAL-1 type, the transmission device side includes the U-SDU (User-Service Data Unit) of the equal bit rate together with related time information. It serves to deliver at the same bit rate, and serves to provide services such as displaying unrecovered errors to higher layers on the receiving device side.

In the AAL-1 type SAR sublayer, the CS-PDU is divided after transmission, and then the SAR-PDU is created by attaching a header and a trailer to the ATM layer. Reassemble the SAR-PDU to perform the function of restoring the CS-PDU. In transmission, the configuration of the SAR-PDU formed in the SAR sublayer is as shown in FIG. That is, as shown in FIG. 1, the SAR-PDU is configured to use as the SAR-PDU flow path space by using the first 1-byte section of the 48-byte payload space.

As shown, the SAR-PDU header data is displayed in a sequence number (SN) area allocated to 4 bits, respectively. The sequence number field indicates data loss or insertion check and the presence or absence of a CS function. And data that can protect the sequence number from errors through the sequence number protection area.

In the AAL-1 type processing step of the receiving apparatus, the error check is performed on the SAR-PDU header data generated in the same structure as the first diagram, and the data is transmitted to the upper protocol only when the error check results in normal data.

In order to perform such an error check, when header data is received in the structure shown in FIG. 1, conventionally, a 1-bit Convergense Sublayer Identifier (hereinafter abbreviated as CSI) and a 3-bit sequence number applied through the sequence number area are used. Error checking is performed only for SN data among (SN) data. That is, when the clock signal applied in cell units (SAR-PDU unit) is not the same as the result of counting and comparing the currently applied SN value, it is checked that an error has occurred and the received data is not transmitted to the upper protocol. Here, the CSI bit is a bit set by the condition determination on the receiving side and is not an error checking object.

Also, for the 3-bit CRC and 1-bit parity check bits applied through the sequence number protection area, it is determined that an error does not exist if the remainder due to the exclusive logic sum (EXOR) after decoding has a value of 0 for CRC. If 1, it is determined that an error exists to control data transmission. The parity check bit exclusively sums 8 bits of data transmitted through the sequence number area and the sequence number protection area, and if the result value is 0, it is determined that no error has occurred, and if 1, the error is generated. It is determined that the data transmission is controlled.

If an error occurs in any of the received data such as SN, CRC, and parity check data, the data is not transmitted to the upper protocol. However, since error checking for CRC and parity check data must be done bit by bit, processing time is high. Not only that, but also the complexity of the hardware, there was a problem that increases the probability of error.

Accordingly, the present invention has been made to solve the above-mentioned problems. In the ATM type receiving apparatus, a header data error check capable of fast and stable error checking by performing error checking on the received CRC and parity check data with a simple hardware structure. The purpose is to provide a circuit.

In order to achieve the above object, the header data error checking circuit includes a sequence number field in a disassembly and reassembly protocol data unit of an asynchronous transmission mode adaptive layer-1 type existing between a higher protocol of the receiver and an asynchronous transmission mode layer. And an error checking circuit for header data comprising a sequence number protection area, wherein the sequence number is compared by comparing a clock signal applied in a disassembly and reassembly protocol data unit unit with a sequence number (SN) transmitted through the sequence number area. An error check circuit section for checking whether an error has occurred for (SN); Pre-predicted predetermined cyclic redundancy check and parity check data, and pre-stored cyclic redundancy when a 1-bit convergence layer layer identifier (CSI) and a 3-bit sequence number (SN) are transmitted through the sequence number area. A table for reading corresponding data among the duplicated and parity check data; The first comparator for checking whether the cyclic redundancy check and parity check data is detected by comparing the cyclic redundancy check and parity check data transmitted through the sequence number protection area with the cyclic redundancy check and parity check data read from the table. It is characterized by including.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a block diagram of a header data error checking circuit according to the present invention, and checks whether an error occurs for a sequence number (SN) data transmitted through a sequence number region of the header region shown in FIG. A cyclic redundancy check and parity check data error for checking whether or not an error has occurred in the CRC and parity check data transmitted through the sequence number protection area among the header areas shown in FIG. It consists of a check part 22.

In particular, the cyclic redundancy check and parity check data error check unit 22 stores predetermined cyclic redundancy check and parity check data, and stores corresponding cyclic redundancy check and parity check data as four addresses of 4-bit CSI and SN data transmitted through the sequence number area. The cyclic redundancy check and parity currently received through the table 23 for reading the redundancy check and parity check data, the cyclic redundancy check and parity check data output from the table 23, and the sequence number protection area shown in FIG. And a first comparator 24 for comparing the inspection data to check whether an error has occurred.

The operation of FIG. 2 configured as described above is as follows.

First, when the SAR-PDU data cast as shown in FIG. 1 is received, the 4-bit data transmitted through the sequence number area is the sequence number error check unit 21 and the cyclic redundancy check and parity check data error check unit 22. 4 bits of data transmitted through the sequence number protection area are transmitted to the cyclic redundancy check and parity check data error check unit 22.

As shown in FIG. 3, the sequence number error check unit 21 is a 3-bit counter 31 and a 3-bit data output from the counter 11 for counting the clock signal CLK generated at each SAR-PDU generation. And a second comparator 32 for comparing the 3-bit SN data transmitted through the sequence number area and performs an error check on the data transmitted through the sequence number area. That is, when 1-bit CSI data and 3-bit SN data are transmitted through the sequence number area, only the SN data is transmitted to the second comparator 32.

The second comparator 32 compares the 3-bit count value output from the counter 31 with the currently applied SN value, and outputs SN error check data indicating a state in which an error has not occurred, if the same is not the same. In this case, SN error check data indicating a state where an error has occurred is output. The output error check data is output from the AAL as a signal to control the transmission of the upper protocol. If an error occurs, the received data is controlled not to be transmitted to the upper protocol. If the error does not occur, the error check data is controlled normally. do.

On the other hand, the 4-bit CSI and SN data applied to the cyclic redundancy check and parity check data error check unit 22 are transmitted to the table 23. The table 23 stores cyclic redundancy check and parity check data that may occur in advance, and reads out cyclic redundancy check and parity check data corresponding to the applied CSI and SN data. Here, the table 23 may be configured of a programmable array logic circuit. The read data is sent to the first comparator 24.

The first comparator 24 compares the cyclic redundancy check and parity check data transmitted from the table 23 with the cyclic redundancy check and parity check data currently transmitted through the sequence number protection area as in the second comparator 32. . As a result of the comparison, if the CRC and parity check data applied from the table and the currently applied CRC and parity check data are the same, error check data indicating a state in which no error has occurred is generated, and if not, an error is generated. Generates error check data.

As described above, the header data error checking circuit according to the present invention implements a simple hardware structure using a table and a comparator to check errors for cyclic redundancy check and parity check data, thereby enabling fast error checking. In addition, there is an advantage that the error checking operation can be operated stably.

Although the present invention has been described as the above-described embodiment, those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (3)

In the error checking circuit for header data consisting of a sequence number area and a sequence number protection area in an asynchronous transfer mode adaptive layer-1 type disassembly and reassembly protocol data unit existing between a higher protocol of the receiver and an asynchronous transfer mode layer, An error checking unit for checking whether an error has occurred for the sequence number SN by comparing the clock signal applied in the decomposition and reassembly protocol data unit unit with the sequence number SN transmitted through the sequence number region; Pre-predicted predetermined cyclic redundancy check and parity check data are stored, and when a 1-bit convergence layer layer identifier (CSI) and a 3-bit sequence number (SN) transmitted through the sequence number area are applied, the predetermined stored A table for reading corresponding data among cyclic redundancy check and parity check data; Comparing the cyclic redundancy check and parity check data transmitted through the sequence number protection area with the cyclic redundancy check and parity check data read from the table to check whether an error occurs in the cyclic redundancy check and parity check data; 1. A header data error checking circuit comprising one comparator. 2. The header data error check circuit of claim 1, wherein the table comprises programmable array logic. The apparatus of claim 1, wherein the error checking unit for the sequence number comprises: a counter for counting the clock signal; And a second comparator for checking whether an error has occurred by comparing whether the value counted in the counter is equal to the sequence number (SN) data transmitted through the sequence number area.