KR970008677B1 - Header data generation circuit for sar-pdu in the all-1 type - Google Patents

Abstract

The header data generating circuit of a segmentation and reassembly protocol data unit in ATM transmission mode adaptation layer-1 type, comprises: a counter for counting a clock signal generated whenever the segmentation and reassembly protocol data unit is generated to thereby generate sequence number data; a cyclic redundancy check and parity check data table for reading cyclic redundancy check and parity check data corresponding to the sequency number data outputted from the counter and a convergence sublayer identifier provided to a higher rank protocol; and a data transmission processor for assigning the sequence number data and the convergence sublayer identifier to a sequence number area of the segmentation and reassembly protocol data unit header and for assigning the data outputted from the cyclic redundancy check and parity check data table to a sequence number protection area of the header.

Description

Header Data Generation Circuit of Partitioning and Reassembly Protocol Data Unit in Asynchronous Transfer Mode Adaptive Layer-1 Type

1 is a block diagram of a general asynchronous transmission mode adaptation layer-1 (AAL-1) type partitioning and reassembly protocol data unit (SAR-PDU).

2 is a block diagram of a header data generation circuit according to the present invention.

* Explanation of symbols for main parts of the drawings

11: counter 12: cyclic redundancy check and parity check data table

13: data transmission processing unit

The present invention relates to a circuit for generating header data of asynchronous adaptation layer-1 (AAL-1) type in a communication system in an asynchronous transfer mode (hereinafter referred to as ATM). In particular, the present invention relates to a header data generation circuit for rapidly and stably generating header data of a SAR-PDU (Segmentation And Reassemblya-Protocal Data Unit (SAR-PDU)).

Asynchronous transmission mode communication system has emerged as a realization of the BISDN (Broadband Integrated Services Digital Network), and is a system for transmitting data by integrating the digital communication mode and packet mode communication method of the existing circuit mode. The communication system using the asynchronous transmission mode divides processing steps into a physical layer, an ATM layer, an ATM adaptation layer (hereinafter referred to as an AAL), and a higher protocol.

The Asynchronous Transfer Mode Adaptation Layer (AAL) is an intermediate layer of the upper protocol, which is the ATM layer and the high-level user service layer, and serves to bridge the difference between services between the ATM layer and the upper protocol. A SAR unit that forms a user information section (or payload section) of an ATM cell by cutting a Convergence Sublayer (CS) and PDUs that are made into units (Protocal Data Units). It is organized in layers. Such AALs are classified into various types according to whether or not the bit rate is constant, real-time, connectivity, etc. In the case of the AAL-1 type, U-SDUs (User Service Data Units) of the same bit rate are transmitted along with related time information at the same bit rate. Service to the upper layer.

In the AAL-1 type SAR sublayer, the CS-PDU is divided after transmission, and then the SAR-PDU is created by attaching a header and a trailer to the ATM layer. Reassemble the SAR-PDU to perform the function of restoring the CS-PDU. The configuration of the SAR-PDU formed in such a SAR sublayer is as shown in FIG. As shown in FIG. 1, the SAR-PDU transmits SAR-PDU header data using the first 1-byte section of the 48-byte payload space, and uses the remaining 47-byte area as the SAR-PDU payload space. It is composed.

As shown, the SAR-PDU header data consists of sequence number (SN) and sequence number protection (SNP) data allocated to 4 bits, respectively, and the sequence number is a cell loss or insertion check and CS. It is used to indicate the presence or absence of a function, and sequence number protection is used for error correction to protect sequence numbers from errors.

In order to generate such SAR-PDU header data, conventionally, data corresponding to a 4-bit sequence number region is generated using a value obtained by counting a clock signal generated every SAR-PDU generation and a Convergense Sublayer Identifier (CSI). The cyclic redundancy check (CRC & parity check) data was generated using one count value and the CSI value to generate data corresponding to the sequence number protection area. At this time, CRC and parity check data are generated only one bit per clock due to hardware characteristics. SAR-PDU header data is finally generated because it takes four clock periods to generate 4-bit CRC and parity check data. The generated time is not only the time delayed by 4 clock periods after the sequence number is generated, but also the period of the clock signal used to generate the CRC and parity check data and the clock signal used to generate the sequence number. There is a problem that the hardware operation is unstable because the processing to be different so as to prevent the synchronization between them.

Accordingly, an object of the present invention is to provide a header data generation circuit for generating SAR-PDU hair data using a memory as a CRC and parity check data generation circuit to solve the above problems.

In order to achieve the above object, an apparatus according to the present invention is characterized in that in a circuit for generating header data of a decomposition and reassembly protocol data unit of an asynchronous transmission mode adaptation layer-1 type existing between a higher protocol and an asynchronous transmission mode layer. A counter for counting clock signals generated each time a reassembly protocol data unit is generated to generate sequence number data; A cyclic redundancy check and parity check data table for reading cyclic redundancy check and parity check data corresponding to sequence number data output from a counter and convergent sublayer identification data (CSI) provided from a higher protocol; Assigns sequence number data and convergence layer layer identification data (CSI) to the sequence number field of the decomposition and reassembly protocol data unit (SAR-PDU) header, and outputs data from the cyclic redundancy check and parity check data tables And a data transfer processing unit for performing data transfer processing to be allocated to the number protection area.

Hereinafter, with reference to the accompanying Figure 2 will be described in detail an embodiment according to the present invention.

FIG. 2 is a block diagram of a header data generation circuit according to the present invention, and includes a counter 11 for counting a clock signal generated each time a SAR-PDU is generated, and 3 bit data output from the counter 11 and a higher protocol. The table 12 for reading the cyclic redundancy check and parity check data corresponding to the CSI data, and the 3-bit data and the 1-bit CSI data output from the counter 11 are allocated to the sequence verno region of FIG. 4 bit data output from the check and parity check data table 12 are assigned to a data transfer processor 13 for processing data transfer so as to be allocated to the sequence number protection area of FIG.

The operation of FIG. 2 configured as described above is as follows.

The clock signal is applied periodically to generate one clock signal for each SAR-PDU generation. Therefore, since the SAR-PDU sets 48 bytes as one unit as shown in FIG. 1, the clock signal is applied with one clock signal per 48 bytes. The applied clock signal is transmitted to the counter 11.

The counter 11 outputs the counted clock signal in the form of 3 bits. At this time, since the output value of the counter 11 counts the clock signal applied every SAR-PDU occurrence, the counted result is the sequence number data of the transmitted SAR-PDU data. The sequence number data output from the counter 11 is transmitted to the data transfer processor 13 and the CRC and parity check data table 12.

The CRC and parity check data table 12 is composed of a programmable array logic table, and recognizes 3-bit data provided by the counter 11 and 1-bit CSI data provided by a higher protocol as an address value. Read the 4-bit CRC, parity check, and data already stored at the corresponding address. In this case, the CSI is data set by the user by condition determination on the receiving side at the time of call setup in the upper protocol, and is a bit indicating the presence or absence of a CS function in the AAL. The read 4-bit CRC and parity check data are transmitted to the data transfer processor 13.

The data transfer processing unit 13 applies CSI (1 bit), sequence number (3 bits), and CRC (3 bits) to the applied CSI data, the output data of the counter 11, and the output values of the CRC and parity check data table 12. ) And parity (1 bit) in order to be allocated to the SAR-PDU header area.

As described above, the header data generation circuit according to the present invention implements a circuit for generating cyclic redundancy check and parity check data as a memory, thereby simplifying the hardware configuration and stabilizing CRC and parity check data generation operations. In addition, there is an advantage that CRC and parity check data can be generated without delay after generating sequence numbers.

Claims (2)

A circuit for generating header data of a disassembly and reassembly protocol data unit of an asynchronous transfer mode adaptive layer-1 type existing between a higher protocol and an asynchronous transfer mode layer, the clock signal generated each time the disassembly and reassembly protocol data unit is generated. A counter for generating sequence number data by counting a number, and for reading the cyclic redundancy check and parity check data corresponding to the sequence number data outputted from the counter and converged layer layer identification data (CSI) provided from the higher protocol. A cyclic redundancy check and parity check data table, the sequence number data and the convergence layer layer identification data (CSI) are allocated to the sequence number area of the decomposition and reassembly protocol data unit (SAR-PDU) header, and the cyclic redundancy check And output from the parity check data table The emitter header data generating circuit, characterized in that it comprises a data transfer processing to the data transfer process such that the sequence number assigned to the protection area of the header. 2. The header data generation circuit of claim 1, wherein the table comprises programmable array logic.