KR0185865B1 - Memory mapping method for interleaving data in reed-solomon forward error correction system of aal type 1 - Google Patents

Abstract

The present invention comprises: a first step (S1) of inputting RS encoded data from an RS encoder into a standby state; Determining whether a virtual path identification number (VPI) and a virtual channel identification number (VCI) are determined for the RS encoded data and maintaining the idle state of the first step (S1) if the virtual path identification number (VPI) and the virtual channel identification number (VCI) are not determined; A third step S3 of recording an ATM cell header at the top of the teaching block of the memory when the virtual path identification number VPI and the virtual channel identification number VCI are determined as a result of the determination in the second step S2; A fourth step (S4) of recording a SAR header at the top of a teaching block of the memory; A fifth step (S5) of reading the RS encoded user data and sequentially recording the user data in the horizontal direction on the teaching block; A sixth step (S6) of sequentially reading and outputting the ATM cell header, SAR header and teaching block recorded in the memory in the longitudinal direction; If there is data to be transmitted, it is determined whether there is data to be transmitted, and a seventh step (S7) of performing the fifth step (S5) and terminating the data transmission if there is no data to be transmitted .

Description

Memory Mapping Method for Teaching in Reed Solomon Forward Error Correction System in AAL Type 1

The present invention relates to a memory mapping method for teaching in a Reed Solomon forward error correction system in AAL type 1, and more particularly, to a method and apparatus for writing 47 bytes of payload data into a memory for teaching in forward error correction, Header and ATM cell header on top of the payload data of 47 bytes and then outputting the cell data in the vertical direction to output the Reed Solomon forward error in the AAL type 1 in which the function of the ATM adaptation layer and the ATM layer can be performed simultaneously To a memory mapping method for teaching in a correction system.

In general, ATM is a connection-oriented technology for the implementation of broadband ISDN (B-ISDN), and can support both connection and non-connection services. However, B-ISDN is evolving by adding and merging functions and services step by step based on existing ISDN principles. Therefore, in the process of integrating existing public telecommunication networks into B-ISDN, it is inevitably necessary to interwork the existing network with the new network to be implemented due to economical efficiency and efficiency. There is a need for a solution that can be implemented.

On the other hand, from the viewpoint of the communication network, the BISDN service can be classified into a constant bit rate, a non-real-time information transmission, and a non-connection with a channel.

Therefore, in terms of bit rate, the BISDN service can be broadly classified into a constant bit rate and a variable bit rate. The former is called a constant bit rate (CBR) service and the latter is a variable bit rate (VBR) bit rate service. A representative example of the CBR service is a 64kbps PCM voice signal, and a video signal and a data signal can be provided in the form of a CBR service.

However, since data signals have VBR characteristics in general, it is natural to provide them as VBR services, and video and audio signals can also be provided as VBR services. The bit rate of the CBR service is determined by the negotiation between the user and the user at the time of call setup and the bit rate is kept constant while the service is maintained. In case of the VBR service, the bit rate is changed while the service is provided, If the variation is too large, it will interfere with the communication network. Therefore, the characteristic parameters of the VBR service should be informed to the communication network in the call setup.

On the other hand, in the AAL type 1, a function of bit error detection and correction in the user data is provided according to the service. In this case, it is recommended in the recommendation to detect and correct the bit error using Reed-Solomon code . Two corrective methods are proposed in the above recommendation. The first method is suitable for loss-sensitive signal transmission, and the second method is suitable for delay-sensitive signal transmission.

Therefore, it should be noted that the first segmentation and reassembly protocol data unit (SAR-PDU) of the converging sub-layer protocol data unit (CS-PDU) to match the synchronization of the converging sub- The convergence sublayer indicator (CSI) bit of the CSI is set to 1, thereby making it impossible to use the CSI at the same time with the structured data transfer (SDT) scheme.

In the method used for the transmission of the loss sensitive signal, a Reed Solomon code of 4 octets is added for each input data 124 bytes at the transmitting side, and the Reed Solomon code is transmitted to and processed in the octet teaching machine. One teaching matrix becomes the convergence sublayer protocol data unit (CS-PDU).

Meanwhile, the Reed-Solomon code is generated from a Galois field (256), and the generated polynomial is as follows.

Where a is a binary primitive polynomial , And the base exponent k of the generator polynomial is 120.

FIG. 1 is a diagram showing a structure of a general long teaching matrix. The errors that can be corrected by the process shown in this drawing are as follows. First, there are four cell losses, two second cell losses, one octet error in each column, no third cell loss, and two octet errors in each column. The overhead in the above method is 3.1%, and the delay at the transmitting / receiving end becomes 128 cells.

In addition, in the method used for loss-sensitive signal transmission, a Reed-Solomon code of 6 octets is added for every 88 octets of input data on the transmitting side, and one teaching matrix in the octet teaching machine is added to the converging sub- ). Then, the code used is generated from the Galois field 256, and the generator polynomial is as follows.

Where a is a binary primitive polynomial , And the base exponent k of the generator polynomial is 120.

FIG. 2 is a diagram showing a structure of a general short teaching matrix. Here, in order to reduce the delay in processing, it is taught in a diagonal direction, for example, in a diagonal direction while writing in a horizontal direction. Then, if a (i, j) is the (i, j) element of the teaching matrix, the matrix is read out in the following order.

... , a (i + 1, j + 1), a (i, j), a

The errors that can be corrected by the above process are as follows. First, one out of the 16 cells is missing, and three octets in each second column. The overhead in the above method is 6.38%, and the delay at the transmitting and receiving end is about the time required for teaching in the horizontal and vertical directions.

In addition, when there is no transmission bit error, the RS encoding can reproduce a byte erased up to NK bytes (where K is a block unit byte) out of N bytes (the number of parity bytes added) The error bit can be corrected as well, but the playback capability of the erased byte is statistically degraded. This phenomenon can be expressed as follows.

2e + E < N - K + 1

Where e is the number of erroneous bytes due to transmission bit errors and the like, and E represents the number of erased bytes.

For example, when RS encoding with N = 128 and K = 124 is performed, up to four erased bytes out of the 128 bytes can be reproduced if there is no error in the transmission byte. If there are no erased bytes, You can do it.

In this way, when the cell loss is to be reproduced by the RS encoding, RS encoding, for example N = 128, K = 124, is performed.

On the other hand, in the conventional Reed Solomon forward error correction system in the AAL type 1, data transmission is performed using an 8-bit data bus.

In addition, since the SAR header and the ATM cell header are separately processed in the ATM adaptation layer and the ATM layer separately from the payload data, the processing is complicated and a delay occurs in the processing.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a method and system for solving the above problems, in which 47 bytes of payload data are written to a memory for teaching in forward error correction, The present invention provides a memory mapping method for a teaching thread in an AAL type 1 forward error correcting system in which a function of an ATM adaptation layer and an ATM layer can be simultaneously performed by outputting cell data in a vertical direction after recording. There is a purpose.

According to an aspect of the present invention, there is provided a method of transmitting RS encoded data, the method comprising: receiving RS encoded data from an RS encoder; Determining whether a virtual path identification number and a virtual channel identification number are determined for the RS encoded data, and maintaining the idle state of the first step if the virtual path identification number and the virtual channel identification number are not determined; A third step of recording the ATM cell header at the top of the teaching block of the memory when the virtual path identification number and the virtual channel identification number are determined as a result of the determination in the second step; A fourth step of recording a SAR header at the top of a teaching block of the memory; A fifth step of reading the RS encoded user data and sequentially recording the user data in the horizontal direction on the teaching block; A sixth step of sequentially reading and outputting an ATM cell header, a SAR header and a teaching block recorded in the memory in a longitudinal direction; And a seventh step of performing the fifth step if there is data to be transmitted, and terminating the data transmission if there is no data to be transmitted.

According to the present invention configured as described above, when 47 bytes of payload data is recorded in the memory for teaching in forward error correction, the SAR header and the ATM cell header are recorded on the top of the payload data of 47 bytes, The ATM adaptation layer and the ATM layer functions can be performed at the same time, thereby simplifying the data processing process and reducing the data delay.

1 is a diagram showing a structure of a general long teaching matrix,

2 is a diagram showing a structure of a general short teaching matrix,

3A shows a data format of an ATM cell,

3B is a diagram showing a header structure at a user network interface (UNI)

3C is a diagram showing a header structure at a network node interface (NNI)

4A is a diagram showing a data format for each layer in the ATM communication system,

4B is a diagram illustrating the AAL type 1 SAR format shown in FIG. 2A,

5 is a diagram showing a teaching and reverse teaching apparatus in a Reed Solomon forward error correction system in the AAL type 1 according to the present invention,

FIG. 6 is a diagram illustrating a memory mapping for teaching in a Reed Solomon forward error correction system in AAL type 1 according to the present invention;

7 is a diagram illustrating an ATM cell header structure in a memory mapping process for teaching in a Reed Solomon forward error correction system in AAL type 1 according to the present invention;

8 is a flowchart illustrating a memory mapping method for teaching in a Reed Solomon forward error correction system in AAL type 1 according to the present invention.

DESCRIPTION OF THE REFERENCE NUMERALS

10: first RS encoder 12: first interleaver

20: teaching data transmitter 21: first RS decoder

23: a first inverse-interleaver

30: Teaching data receiver

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3A to 3C, the long message of the user is divided into ATM cells and transmitted, and the received ATM cells are reassembled into one message and transmitted to the upper user .

FIG. 3A is a diagram illustrating a data format of an ATM cell, FIG. 3B is a diagram illustrating a header structure at a user network interface (UNI), and FIG. 1C is a diagram illustrating a header structure at a network node interface (NNI).

Here, the ATM cell is divided into a 5-byte (or octet) header section and a 48-byte user information section. The 5-byte header is divided into a user network interface (UNI) The header structure of the UNI is divided into 4 bits of generic flow control (GFC) and 4 bits of virtual path identification (VPI) identifier.

The second byte is composed of a 4-bit virtual path identification number VPI and a 4-bit virtual channel identifier (VCI), and the third byte is an 8-bit virtual channel identification number (VCI) And the fourth byte is composed of a 4-bit virtual channel identification number (VCI), a 3-bit payload type (PT), and a 1-bit cell loss priority (CLP) The byte consists of 8 bits of header error control (HEC).

3C, the general flow control (GFC) in the first byte of the user network interface (NNI) is set to the virtual path identification number VPI It is possible to know the header structure of the user network interface (NNI) except that it is used. The ATM communication method has a hierarchical structure as shown in Table 1, and has standardized standards for each layer.

[Table 1]

Layer Sub-layer function Upper layer Upper layer function ATM adaptation layer Convergence (CS) sub-layer Convergence function Cutting and recombination (SAR) Cutting function and recombination function ATM layer Generic flow control and cell header processing Physical layer Transmission Convergence (TC) HEC signal generation and extraction function Physical medium Bit time information function

As shown in Table 1, the ATM communication method is classified into a vertical structure such as a physical layer, an ATM layer, an ATM adaptation layer (AAL), and an upper protocol layer. The AAL layer is divided into sub- segmentation and reassembly sublayer and a convergence sublayer (CS) sublayer. The physical layer is divided into a physical medium (PM) and a transmission convergence (TC) sublayer.

In addition, the service requested by the user in the ATM communication system can be classified as shown in Table 2 according to the characteristics thereof.

[Table 2]

Types of Services Time relationship between ends Bit rate Connection mode Examples of services A species Real-time cast Equality Connectivity Odds ratio video signal B species Real-time cast variable Connectivity Variable rate video signal C species Non-real-time property variable Connectivity Connectivity data D species Non-real-time property variable Non-connectivity Non-connectivity data

The AAL protocol corresponding to the service is divided into AAL 1 to AAL 5 as shown in Table 3 below.

[Table 3]

AAL form Typical functions AAL 1 Supports class A service with constant bit rate AAL 2 Supports Class B service with real-time property and variable bit rate AAL 3/4 Supports C and D service with variable bit rate AAL 5 Simplifies AAL 3/4 functionality to support high-speed services

In Table 3, the AAL layer is horizontally divided into AAL 1, AAL 2, AAL 3/4, and AAL 5 to efficiently process the corresponding service according to the type of the service.

Here, the AAL 1 layer includes a converging sublayer (CS) for transparently transmitting an A-type service data unit (U-SDU) having a constant bit rate, detecting a transmission error, and performing information identification and clock synchronization functions The ATM cell is divided into variable length data obtained by dividing the variable length data received from the convergence sublayer (CS) and transmitted to the ATM layer. In addition, the segmentation and reassembly sublayer (SAR ).

The convergence (CS) sublayer includes a common part convergence sublayer (CPCS) that performs functions common to the connectivity and non-connectivity services, a service specific convergence sublayer (SSCS: service specific convergence layer).

FIG. 4A is a diagram showing a data format for each layer in the ATM communication system. Here, a U-SDU of an upper layer passes through an AAL-service access point (AAL-SAP) (AAL-SDU) and stored in the AAL FIFO. The AAL1 SAR layer divides the CS-PDU into 47 bytes according to the message to be transmitted by the user, adds 1 byte of SAR header, Protocol unit (SAR-PDU) is formed and sent down to the ATM layer via the ATM service connection point (ATM-SAP). In the ATM layer, a 5-byte ATM header is attached to form an ATM cell of 53 bytes, and the ATM cell is transmitted to another terminal or an ATM exchange through an optical path of the physical layer.

That is, in the AAL type 1 protocol, the U-SDU of the identity bit rate is transmitted at the same bit rate together with the related time information so that the clock information of the information source can be extracted from the receiving side, and in the converging sub- In the partitioning and reassembling sublayer, the CS-PDU is divided, and a 1-byte header is added and sent down to the ATM layer.

4B shows a SAR format of AAL type 1 shown in FIG. 4A. Here, the transmitted message is divided into a 47-byte SAR-PDU payload and a 1-byte header. The header includes a 4-bit sequence number protection Sequence number protection (SNP). The sequence number SN consists of a 1-bit convergence sublayer indicator (CSI) and a 3-bit sequence count (SC) The number protection (SNP) consists of 3-bit cyclic redundancy check (CRC) and 1-bit parity (P).

Meanwhile, in the embodiment of the present invention, a 1-bit convergent sublayer identifier (CSI) is 1 in the first SAR header and 0 in the subsequent SAR header. A 3-bit cyclic redundancy check (CRC) is a calculation for the convergence sublayer identifier (CSI) and the sequence number (SN), and the 3-bit cyclic redundancy check (CRC) The parity P of the bits performs calculations on the Convergence Sublayer Identifier (CSI), the Sequence Number (SN) and the cyclic redundancy check (CRC).

FIG. 5 is a diagram showing a teaching and reverse teaching apparatus in a Reed Solomon forward error correction system in the AAL type 1 according to the present invention. Here, the apparatus is composed of a transmitter, for example, a teaching processor 20 and a receiver, for example, an inverse teaching processor 30.

The teaching processor 20 comprises a first RS encoder 10 and a first teaching machine 12 and the inverse teaching processor 30 comprises a first RS decoder 21 and a first reverse teaching machine 23). In AAL type 1, data is processed in units of 8 bits.

In the AAL type 1 of this embodiment, the pay load is 47 bytes, and this 47 bytes is processed using the 8-bit data bus.

In the embodiment shown in FIG. 5, a bit error is corrected and reproduced simultaneously using a Reed-Solomon (RS) encoding method, which is one of the error correction encoding methods.

First, the image data and the predetermined data are input to the first RS encoder 10 in 8-bit data units, RS encoding is performed, and then input to the first interleaver 12 (interleaver).

Then, the first interlaced machine 12 writes the RS encoded payload data from the first RS encoder 10 in the memory in units of 128 bytes in the horizontal direction, that is, in units of block data, In other words, the payload data is output from the left to the right in units of payload data units, and the payload data is transmitted through the transmission line.

In addition, the receiver 30 receives the video data and the predetermined data from the transmission path into the first RS decoder 21 in units of 8-bit data, performs RS decoding, and then performs a first inverse-interleaver 23, .

The first inverse associative interpolator 23 performs the inverse teaching on the interlaced block data and outputs the interlaced block data when the interlaced block data of 128 bytes is input from the first RS decoder 21.

FIG. 6 is a diagram illustrating a memory mapping scheme for teaching in a Reed Solomon forward error correction system in the AAL type 1 according to the present invention. The memory mapping pattern in FIG. 6 includes a teacher matrix of 47 bytes x 128 bytes, Byte ATM cell header, and a 1-byte SAR header. Therefore, in the course of performing the teaching for the forward error correction, 47 bytes of the teaching matrix are read out from the memory after storing the teaching matrix, for example, 47 bytes 128 bytes, 5 ATM cells header 1 byte, and SAR header in advance The ATM cell header and the SAR header are simultaneously read out and output.

In this way, while the teaching is performed, the ATM cell header and the SAR header are output simultaneously, so that functions of the ATM adaptation layer and the ATM layer are performed, and the SAR header can be fixedly stored in the teaching matrix. For example, since 128 cells are the generation period of the SAR header, that is, an integral multiple of 8 cells, an ATM cell can be generated in the course of teaching using such a multiple.

FIG. 7 is a diagram illustrating an ATM cell header structure in a memory mapping process for teaching in a Reed Solomon forward error correction system in AAL type 1 according to the present invention, wherein the ATM cell has a 5-byte (or octet) And a 48-byte user information section. The 5-byte header includes a 4-bit generic flow control (GFC) and a 12-bit virtual path identification (VPI) path identifier).

The third byte and the fourth byte correspond to a 12-bit virtual channel identifier (VCI), a 3-bit payload type (PT), and a cell loss priority (CLP) ), And the fifth byte is composed of 8-bit header error control (HEC).

Meanwhile, the virtual path identification number VPI and the virtual channel identification number VCI are determined in the connection acceptance process, and the header error control (HEC) is calculated in the physical layer.

8 is a flowchart for explaining a memory mapping method for teaching in a Reed Solomon forward error correction system in AAL type 1 according to the present invention. In the first step S1, RS encoded data is input from an RS encoder The second step S2 determines whether a virtual path identification number VPI and a virtual channel identification number VCI are determined for the RS encoded data. If the virtual path identification number VPI and the virtual channel identification number VCI are not determined, ) In the standby state.

If the virtual path identification number VPI and the virtual channel identification number VCI are determined as a result of the determination in the second step S2, the third step S3 is to record the ATM cell header at the top of the teaching block of the memory , And the fourth step S4 records the SAR header at the top of the teaching block of the memory.

In the fifth step S5, the RS encoded user data is read and recorded in the lateral direction in the orthogonal direction to the teaching block. In the sixth step S6, the ATM cell header, the SAR header, and the teaching block And sequentially read out in the longitudinal direction and output.

In the seventh step S7, it is determined whether there is data to be transmitted. If there is data to be transmitted, the process of the fifth step S5 is performed. If there is no data to be transmitted, .

As described above, according to the present invention, when payload data of 47 bytes is written in the memory for teaching in forward error correction, the SAR header and the ATM cell header are recorded at the top of the payload data of 47 bytes, The ATM adaptation layer and the ATM layer functions can be performed at the same time, thereby simplifying the data processing process and reducing the data delay.

Claims (2)

A first step (S1) of inputting RS encoded data from an RS encoder to a standby state; Determining whether a virtual path identification number (VPI) and a virtual channel identification number (VCI) are determined for the RS encoded data and maintaining the idle state of the first step (S1) if the virtual path identification number (VPI) and the virtual channel identification number (VCI) are not determined; A third step S3 of recording an ATM cell header at the top of the teaching block of the memory when the virtual path identification number VPI and the virtual channel identification number VCI are determined as a result of the determination in the second step S2; A fourth step (S4) of recording a SAR header at the top of a teaching block of the memory; A fifth step (S5) of reading the RS encoded user data and sequentially recording the user data in the horizontal direction on the teaching block; A sixth step (S6) of sequentially reading and outputting the ATM cell header, SAR header and teaching block recorded in the memory in the longitudinal direction; If there is data to be transmitted, it is determined whether there is data to be transmitted, and a seventh step (S7) of performing the fifth step (S5) and terminating the data transmission if there is no data to be transmitted A method for memory mapping for teaching in a Reed Solomon forward error correction system in AAL type 1. 2. The apparatus of claim 1, wherein the memory structure comprises 53 bytes x 128 bytes, and the 53 bytes comprise an ATM cell header of 5 bytes, a SAR header of 1 byte, and payload data of 47 bytes. A Memory Mapping Method for Teaching in a Reed Solomon Forward Error Correction System in Type.