KR19980017799A - Memory Mapping Method for Teaching in Reed Solomon Forward Error Correction System in AAL Type 1 - Google Patents

Abstract

The present invention includes a first step (S1) in which RS encoded data is input from an RS encoder and placed in a standby state; Determining whether a virtual path identification number (VPI) and a virtual channel identification number (VCI) are determined for the RS coded data, and if not determined, maintaining a standby state of the first step (S1); A third step (S3) of recording the ATM cell header on the upper side of the teaching block of the memory when the virtual path identification number (VPI) and the virtual channel identification number (VCI) are determined as a result of the determination in the second step (S2); A fourth step (S4) of recording a SAR header on top of the teaching block of the memory; A fifth step (S5) of reading RS-coded user data and sequentially writing them in a teaching block in a horizontal direction; A sixth step (S6) of sequentially reading and outputting the ATM cell header, the SAR header, and the teaching block written in the memory in a vertical direction; Determining whether there is data to be transmitted, and if there is data to be transmitted, the fifth step (S7) is performed. If there is no data to be transmitted, the seventh step (S7) is terminated. It is characterized by.

Description

Memory Mapping Method for Teaching in Reed Solomon Forward Error Correction System in AAL Type 1

The present invention relates to a memory mapping method for teaching in a Reed Solomon forward error correction system in AAL type 1, and particularly, in the case of recording 47 bytes of payload data into memory for teaching in forward error correction. Reed-Solomon forward error in AAL Type 1, where the header and ATM cell headers are written on top of the 47-byte payload data and then the cell data are output in the vertical direction to output the ATM adaptation layer and the ATM layer. A memory mapping method for teaching in a correction system.

In general, ATM is a connection-oriented technology for the implementation of broadband ISDN (B-ISDN) and can support both connected and disconnected services. However, B-ISDN is evolving by adding and merging functions and services step by step based on the existing principles of ISDN. Therefore, in the process of integrating and developing the existing public telecommunication networks into B-ISDN, it is necessary to interwork the existing network with the network to be newly implemented due to economic efficiency and efficiency, and to accommodate the functions of the existing network. A plan that can be implemented should be prepared.

On the other hand, in terms of communication networks, BISDN services can be classified into constant bitrates, variable information transfers, non-real time transfers, channel connectivity and connectivity.

Therefore, in terms of bit rate, the BISDN service can be broadly classified into that the bit rate is kept constant and variable, in which the former is called a constant bit rate (CBR) service and the latter is a variable bit rate (VBR) variable. bit rate) service. A representative example of the CBR service is a 64kbps PCM audio signal, and can provide a video signal or a data signal in the form of a CBR service.

However, in general, since data signals have a VBR characteristic, it is natural to provide a VBR service, while video and audio signals can also be provided as a VBR service. The bit rate of the CBR service is determined by negotiation between the user and the network at the time of call establishment, and the bit rate is kept constant while the service is continued, and in the case of the VBR service, the bit rate is changed while the service is provided. If the change is too large, it will interfere with the communication network. Therefore, the characteristics of the VBR service should be informed to the network in advance.

On the other hand, AAL Type 1 provides the function of detecting and correcting bit errors in user data depending on the service, and in this case, it is recommended to detect and correct bit errors using Reed-Solomon code. It is. Two recommendations are presented in the above recommendations: the first method is suitable for loss-sensitive signal transmission and the second method is suitable for delay-sensitive signal transmission.

Therefore, note that the recommendation is that the first partitioning and recombination protocol data unit (SAR-PDU) of the convergence layer protocol data unit (CS-PDU) to match the synchronization of the convergence layer protocol data unit (CS-PDU). The convergence sublayer indicator (CSI) bit of the CSI is set to 1, thereby preventing simultaneous use of the structured data transfer (SDT) scheme.

In the loss sensitive signal transmission method, the transmitter adds a 4-octet lead solomon code for every 124 octets of input data, and the lead solomon code is transmitted to and processed by an octet loom. One cross matrix becomes the convergence layer protocol data unit (CS-PDU).

On the other hand, the Reed Solomon code is generated from the Galois Field (256, Galois Field), the generated polynomial is as follows.

Where a is a binary primitive polynomial And the base exponent k of the generated polynomial is 120.

1 is a view showing the structure of a general long teaching matrix, the error correctable by the process shown in the figure is as follows. First, there are 4 cells lost, 2 cells lost 2 and 1 octet error in each column, 3 cells lost and 2 octet errors in each column. The overhead in this method is 3.1%, and the delay at the transceiver is 128 cells.

In addition, in the method used for loss-sensitive signal transmission, the sender adds 6 octets of a lead solomon code for every 88 octets of input data, and one intersection matrix in the octet loom is a convergence layer protocol data unit (CS-PDU). Will be The code used is generated from galoa field 256, and the generated polynomial is as follows.

Where a is a binary primitive polynomial And the base exponent k of the generated polynomial is 120.

FIG. 2 is a view illustrating a structure of a general short teaching matrix. Here, in order to reduce a delay in processing, the apparatus reads in a diagonal direction while writing in a diagonal direction, for example, in a horizontal direction. If a (i, j) is an element (i, j) of the matrix, it is read from the matrix in the following order.

… , a (i + 1, j-1), a (i, j), a (i-1, j + 1),...

Errors that can be corrected by the above process are as follows. First, 1 loss of 16 cells, 2 octets in each column. The overhead in this method is 6.38%, and the delay at the transmit / receive end is about the time required for teaching in the horizontal and vertical directions.

In addition, RS coding can reproduce a byte erased up to NK bytes (where K is a byte in blocks) out of N bytes (number of bytes added with parity bytes) when there is no transmission bit error. In this case, the error bit can be corrected as well, but the reproduction capability of the erased byte is degraded in a state. This phenomenon is expressed as follows.

2e + E <N-K + 1

Here, e represents the number of error bytes due to transmission bit error, etc., and E represents the number of erased bytes.

For example, if RS = N = 128, K = 124, if there is no error in the transmission byte, up to 4 erased bytes of 128 bytes can be played. If there is no erased byte, up to 2 transmission byte errors can be corrected. I can do it.

As such, when cell loss is to be reproduced by the RS encoding, interleaving is performed after RS encoding, for example, N = 128 and K = 124.

On the other hand, in the conventional AAL type 1 Reed Solomon forward error correction system has a problem that the processing speed of the data is delayed as the data is transmitted using the 8-bit data bus.

In addition, since the SAR header and the ATM cell header are processed separately in the ATM adaptation layer and the ATM layer separately from the payload data, there is a problem that the processing is complicated and a delay occurs in the processing.

Accordingly, the present invention is to solve the above problems, in the case of recording 47 bytes of payload data in memory for teaching in forward error correction, the SAR header and ATM cell header is placed on top of the 47 bytes of payload data. It provides a memory mapping method for teaching in Reed Solomon's forward error correction system in AAL type 1, which records and writes cell data in a vertical direction so that the functions of the ATM adaptation layer and the ATM layer can be simultaneously performed. There is a purpose.

According to an aspect of the present invention, there is provided a method including: a first step of receiving RS encoded data from an RS encoder and entering a standby state; A second step of determining whether the virtual path identification number and the virtual channel identification number have been determined for the RS encoded data and maintaining the standby state of the first step if not determined; A third step of writing an ATM cell header on an upper end of the teaching block of the memory when the virtual path identification number and the virtual channel identification number are determined as a result of the determination in the second step; A fourth step of writing a SAR header on top of the teaching block of the memory; A fifth step of reading RS encoded user data and sequentially recording the teaching data in a teaching block; A sixth step of sequentially reading and outputting the ATM cell header, the SAR header, and the teaching block written in the memory in a vertical direction; The method includes determining a presence or absence of data to be transmitted, and performing a fifth step if there is data to be transmitted, and ending a data transmission if there is no data to be transmitted.

According to the present invention configured as described above, in the case of recording 47 bytes of payload data in memory for teaching in forward error correction, the SAR header and ATM cell header are recorded on the top of 47 bytes of payload data and then in the vertical direction. By alternately outputting cell data, the functions of the ATM adaptation layer and the ATM layer can be simultaneously performed, thereby simplifying data processing and reducing data delay.

1 is a diagram showing the structure of a general long teaching matrix,

2 is a view showing the structure of a general short teaching matrix,

3A is a diagram illustrating a data format of an ATM cell;

3b is a diagram illustrating a header structure at a user network interface (UNI);

3c is a diagram illustrating a header structure at a network node interface (NNI);

4A is a diagram illustrating a data format for each layer in an ATM communication method;

4B is a diagram showing a SAR format of the AAL type 1 shown in FIG. 2A;

5 is a view showing the teaching and reverse processing apparatus in Reed Solomon forward error correction system in AAL type 1 according to the present invention,

FIG. 6 is a view showing the form of memory mapping for teaching in the Reed Solomon forward error correction system in AAL type 1 according to the present invention; FIG.

7 is a diagram illustrating an ATM cell header structure in a memory mapping process for teaching in a Reed Solomon forward error correction system in AAL type 1 according to the present invention;

8 is a flowchart illustrating a memory mapping method for teaching in the Reed Solomon forward error correction system of the AAL type 1 according to the present invention.

Explanation of symbols on the main parts of the drawings

10: first RS encoder, 12: first interleaver,

20: teaching data transmitter, 21: first RS decoder,

23: first inverse-interleaver,

30: Teaching data receiver.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in detail.

As shown in FIGS. 3A to 3C, the user's long message is divided into ATM cells and transmitted, and the received ATM cell is reassembled into one message and transmitted to the upper user. .

3A is a diagram illustrating a data format of an ATM cell, FIG. 3B is a diagram illustrating a header structure at a user network interface (UNI), and FIG. 1C is a diagram illustrating a header structure at a network node interface (NNI).

Here, the ATM cell is divided into a header section of 5 bytes (or octets) and a user information section of 48 bytes, and the header of 5 bytes is a user network interface (UNI) as shown in FIGS. 1B and 3C. Header structure in the user network interface (UNI), where the first byte is a 4-bit generic flow control (GFC) and a 4-bit virtual path identification number (VPI). identifier).

The second byte is composed of a 4-bit virtual path identification number (VPI) and a 4-bit virtual channel identifier (VCI), and the third byte is an 8-bit virtual channel identifier (VCI). The fourth byte consists of a 4-bit virtual channel identification number (VCI), a 3-bit payload type (PT), and a 1-bit cell loss priority (CLP). The byte consists of 8 bits of header error control (HEC).

Also, in the header structure of the network node interface (NNI) as shown in FIG. 3C, the general flow control (GFC) in the first byte of the user network interface (NNI) is converted into a virtual path identification number (VPI). Except for being used, it can be seen that it is identical to the header structure of NNI. This ATM communication method has a hierarchical structure as shown in Table 1 below and has standardized standards for each layer.

TABLE 1

Hierarchy Tier function Upper hierarchy Higher layer function ATM Adaptation Layer Convergence (CS) sublayer Convergence function Cutting and Recombination (SAR) Cutting function and recombination function ATM layer General flow control and cell header processing Physical layer Transmission Convergence (TC) HEC signal generation and extraction function Physical medium Bit time information function

As shown in Table 1, the ATM communication scheme is divided into vertical structures such as a physical layer, an ATM layer, an ATM adaptation layer (AAL), and a higher protocol layer, and the AAL layer is divided and recombined sublayer (SAR). It is divided into segmentation and reassembly sublayer (CS) and convergence (CS) sublayers, and the physical layer is divided into physical media (PM) and transmission convergence (TC) sublayers.

In addition, a service required by a user in an ATM communication method may be classified as shown in Table 2 below according to its characteristics.

TABLE 2

Type of service End-to-end time relationship Bit rate Connection mode Example of service Class A Real time Identity Connectivity Video signal Class B Real time variable Connectivity Variable Rate Video Signal Class C Non-real-time variable Connectivity Connectivity data Class D Non-real-time variable Connectionless Connectionless data

The AAL protocol corresponding to the service is divided into AAL 1 to AAL 5 as shown in Table 3 below.

TABLE 3

AAL form Typical feature AAL 1 Support class A service of equal bit rate AAL 2 Support real-time, variable bit rate Class B service AAL 3/4 Support class C and D services with variable bit rate AAL 5 High speed service by simplifying AAL 3/4 function

In Table 3, the AAL layer is divided horizontally as AAL 1, AAL 2, AAL 3/4, and AAL 5 to efficiently process the corresponding service according to the type of service.

Here, the AAL layer 1 is a convergent sub-layer (CS) that transparently transmits a Class A service data unit (U-SDU) having a constant bit rate, detects transmission errors, and performs information identification and clock synchronization functions. Partitioning and recombination sublayer (SAR) that divides variable-length data received from the convergence sublayer (CS) to create an ATM cell, transfer it to the ATM layer, and receive and reassemble the ATM cell from the ATM layer to recover the CS-PDU. Will be divided into

In addition, the convergence (CS) sublayer is a common part convergence sublayer (CPCS) that performs functions common to the connectivity and connectionless services, and a service specific convergence sublayer for providing a specific AAL user service. (SSCS: service specific convergence layer).

4A is a diagram illustrating a data format for each layer in the ATM communication method, wherein an upper layer user service data unit (U-SDU) passes through an AAL service access point (AAL-SAP) and then AAL. It is formed as a service data unit (AAL-SDU) and stored in the AAL FIFO.In the AAL1 SAR layer, the CS-PDU is divided into 47 bytes according to the message to be transmitted by the user, and then 1-byte SAR header is added to divide and recombine. A protocol unit (SAR-PDU) is formed and sent down to the ATM layer via an ATM service access point (ATM-SAP). In the ATM layer, a 5-byte ATM header is attached to form a 53-byte ATM cell, and then transmitted to another terminal or ATM switch through an optical transmission path of the physical layer.

That is, AAL type 1 protocol transmits U-SDU of equal bit rate at the same bit rate along with related time information, so that clock information of information source can be extracted at the receiving side, and at the convergence part layer, the bit for high quality video or audio signal Error correction function is provided, and the division and reassembly sublayer divides the CS-PDU and adds a 1-byte header to send it to the ATM layer.

FIG. 4B illustrates the SAR format of the AAL Type 1 shown in FIG. 4A, wherein the transmitted message is divided into a 47-byte SAR-PDU payload and a 1-byte header, which is a 4-bit sequence number protection. (SNP: sequence number protection), which consists of a 1-bit convergence sublayer indicator (CSI) and a 3-bit sequence count (SC). Number protection (SNP) consists of a 3-bit cyclic redundancy check (CRC) and a 1-bit parity (P).

Meanwhile, in the embodiment according to the present invention, the 1-bit convergence layer layer identifier (CSI) is 1 in the first SAR header and becomes 0 in the subsequent SAR header. The 3-bit sequence count SC represents a sequence count of 0 to 7, and the 3-bit circular redundancy check (CRC) is a calculation for the convergent sublayer identifier CSI and the sequence number SN. The parity P of the bit is calculated for the converged sublayer identifier CSI, the sequence number SN, and the circuit redundancy check.

5 is a view showing the teaching and reverse processing apparatus in the Reed Solomon forward error correction system in AAL type 1 according to the present invention. Here, the apparatus is composed of a transmitter such as a teaching processing apparatus 20 and a receiver such as a reverse teaching processing apparatus 30.

The teaching processing device 20 is composed of a first RS encoder 10 and a first weaving machine 12, the reverse teaching processing device 30 is the first RS decoder 21 and the first reverse weaving machine ( 23). In AAL type 1, data is processed in units of 8 bits.

In the AAL type 1 of the present embodiment, since the payload is 47 bytes, the 47 bytes are processed using an 8-bit data bus.

In the embodiment shown in FIG. 5, bit error correction and reproduction are simultaneously performed using a Reed-Solomon (RS) encoding method, which is one of error correction encoding methods.

First, image data and predetermined data are input to the first RS encoder 10 in units of 8-bit data, and RS coding is performed to the first interleaver 12.

Thereafter, the first loom 12 writes the RS-encoded payload data from the first RS encoder 10 to a memory in a horizontal 128-byte unit, that is, a block data unit, and then records the vertical direction of the block data, That is, the payload data is transmitted from left to right in units of data, and the paid payload data is transmitted through the transmission path.

In addition, the receiver 30 inputs image data and predetermined data from the transmission path to the first RS decoder 21 in units of 8-bit data, and performs RS decoding, thereby performing a first inverse-interleaver (23). Will be entered.

Subsequently, when the 128-byte unit of block data is input from the first RS decoder 21, the first reverse interlocker 23 performs reverse reversal on the interlaced block data and outputs the reverse block.

FIG. 6 is a diagram illustrating a memory mapping form for teaching in a Reed Solomon forward error correction system in AAL type 1 according to the present invention. In this diagram, the memory mapping form is a matrix of 47 bytes x 128 bytes, and FIG. It consists of an ATM cell header of bytes and a SAR header of 1 byte. Therefore, in the process of performing the teaching for forward error correction, the teaching matrix, for example, 47 bytes x 128 bytes, 5 bytes of ATM cell header, 1 byte of SAR header is stored in advance, and then 47 bytes of reading matrix are read from the memory. If so, the ATM cell header and the SAR header are simultaneously read and output.

As described above, the ATM cell header and the SAR header are output while the teaching job is performed, and the functions of the ATM adaptation layer and the ATM layer are performed, and the SAR header can be fixedly stored in the teaching matrix. For example, since 128 cells are the generation period of the SAR header, that is, an integer multiple of 8 cells, an ATM cell can be generated in the teaching process using this multiple.

7 is a diagram illustrating an ATM cell header structure in a memory mapping process for teaching in a Reed Solomon forward error correction system in AAL type 1 according to the present invention, wherein the ATM cell is a header of 5 bytes (or octets). Section and 48 bytes of user information section, and the 5 byte header consists of 4 bits of generic flow control (GFC) and 12 bits of virtual path identification number (VPI: virtual). path identifier).

In addition, the third byte and the fourth byte have a 12-bit virtual channel identifier (VCI), a 3-bit payload type (PT), and a 1-bit cell loss priority (CLP). ), And the fifth byte consists of 8 bits of header error control (HEC).

Meanwhile, the virtual path identification number (VPI) and the virtual channel identification number (VCI) are determined during the connection acceptance process, and the header error control (HEC) is calculated at the physical layer.

FIG. 8 is a flowchart illustrating a memory mapping method for teaching in the Reed Solomon Forward Error Correction System in AAL Type 1 according to the present invention. First, in step S1, RS coded data is input from an RS encoder. In the standby state, if the second step (S2) is not determined by determining whether the virtual path identification number (VPI) and the virtual channel identification number (VCI) for the RS encoded data is not determined, the first step (S1) ), The standby state is maintained.

In the third step S3, when the virtual path identification number VPI and the virtual channel identification number VCI are determined as a result of the determination in the second step S2, the ATM cell header is recorded on the upper side of the teaching block of the memory. In the fourth step S4, the SAR header is written on the upper end of the teaching block of the memory.

In addition, the fifth step (S5) reads RS-coded user data and writes sequentially to the teaching block in the horizontal direction, and the sixth step (S6) writes the ATM cell header, the SAR header, and the teaching block written in the memory. It reads sequentially in the vertical direction and outputs them.

In the seventh step S7, if there is data to be transmitted by determining whether to transmit data, the fifth step S7 is performed. If there is no data to be transmitted, the data is transmitted. Will end.

As described above, according to the present invention, in the case of recording 47 bytes of payload data into memory for teaching in forward error correction, the SAR header and ATM cell header are recorded on the top of 47 bytes of payload data. By alternately outputting cell data in the direction, the functions of the ATM adaptation layer and the ATM layer can be simultaneously performed, thereby simplifying data processing and reducing data delay.

Claims (2)

A first step (S1) in which RS encoded data is input from an RS encoder and placed in a standby state; Determining whether a virtual path identification number (VPI) and a virtual channel identification number (VCI) are determined for the RS coded data, and if not determined, maintaining a standby state of the first step (S1); A third step (S3) of recording the ATM cell header on the upper side of the teaching block of the memory when the virtual path identification number (VPI) and the virtual channel identification number (VCI) are determined as a result of the determination in the second step (S2); A fourth step (S4) of recording a SAR header on top of the teaching block of the memory; A fifth step (S5) of reading RS-coded user data and sequentially writing them in a teaching block in a horizontal direction; A sixth step (S6) of sequentially reading and outputting the ATM cell header, the SAR header, and the teaching block written in the memory in a vertical direction; Determining whether there is data to be transmitted, and if there is data to be transmitted, the fifth step (S7) is performed. If there is no data to be transmitted, the seventh step (S7) is terminated. A memory mapping method for teaching in a Reed Solomon forward error correction system in AAL type 1. 2. The AAL as claimed in claim 1, wherein the memory structure is 53 bytes x 128 bytes, and the 53 bytes are 5 bytes of ATM cell header, 1 byte of SAR header, and 47 bytes of payload data. Memory mapping method for teaching in Reed Solomon forward error correction system of type 1.