KR0185860B1 - Apparatus and method for processing the cbr data in aal type 1 - Google Patents

Abstract

In the present invention, two 8-bit data, for example 16-bit data, are input from the upper layer to form ATM cell data, and then 16-bit data is transmitted to the ATM layer at a high speed so that a separate memory is not needed A fixed bit rate data processing apparatus and its processing method in an AAL type 1, comprising: first and second FIFOs (10, 11) in which data is input and stored in units of 8 bits from an upper layer; A delay element 12 for delaying the data from the second FIFO 11 by one byte; First to fourth buffer units (13 to 16) for selectively outputting data from the first FIFO (10) and the delay element (12); First and second registers (20, 21) storing header information of data input to the first and second FIFOs (10, 11); First and second multiplexers 22 and 23 for selectively outputting header information from the first and second registers 20 and 21 and data from the buffer units 13 and 16; Third and fourth FIFOs 24 and 25 for storing data from the first and second multiplexers 22 and 23 and outputting the data to the ATM service connection point (ATM-SAP); Control means 26 for controlling the delay element 12, the buffer units 13 to 16, the registers 20 and 21, the multiplexers 22 and 23 and the third and fourth FIFOs 24 and 25, .

Description

Fixed bit rate data processing device and its processing method in AAL type 1

The present invention relates to an apparatus for processing a fixed bit rate data in an AAL type 1 and a processing method thereof. More particularly, the present invention relates to an apparatus for processing a fixed bit rate data, To a fixed bit rate data processing apparatus in AAL type 1 and a processing method thereof.

In general, ATM is a connection-oriented technology for the implementation of broadband ISDN (B-ISDN), and can support both connection and non-connection services. However, B-ISDN is evolving by adding and merging functions and services step by step based on existing ISDN principles. Therefore, in the process of integrating existing public telecommunication networks into B-ISDN, it is inevitably necessary to interwork the existing network with the new network to be implemented due to economical efficiency and efficiency. There is a need for a solution that can be implemented.

On the other hand, from the viewpoint of the communication network, the BISDN service can be classified into a constant bit rate, a non-real-time information transmission, and a non-connection with a channel.

Therefore, in terms of bit rate, the BISDN service can be broadly classified into a constant bit rate and a variable bit rate. The former is called a constant bit rate (CBR) service and the latter is a variable bit rate (VBR) bit rate service. A representative example of the CBR service is a 64kbps PCM voice signal, and a video signal and a data signal can be provided in the form of a CBR service.

However, since data signals have VBR characteristics in general, it is natural to provide them as VBR services, and video and audio signals can also be provided as VBR services. The bit rate of the CBR service is determined by the negotiation between the user and the user at the time of call setup and the bit rate is kept constant while the service is maintained. In case of the VBR service, the bit rate is changed while the service is provided, If the variation is too large, it will interfere with the communication network. Therefore, the characteristic parameters of the VBR service should be informed to the communication network in the call setup.

On the other hand, in the conventional method of processing the CBR data in the AAL type 1, there is a problem that the data processing speed is delayed as the data is transmitted using the 8-bit data bus.

In order to solve the above problems, the present invention provides an ATM cell in which two 8-bit data, for example 16-bit data, are input from an upper layer to form ATM cell data, In addition, it is an object of the present invention to provide a fixed bit rate data processing apparatus and its processing method in an AAL type 1 in which a separate memory is not required.

According to an aspect of the present invention, there is provided a data processing apparatus including first and second FIFOs, each of which receives data stored in units of 8 bits from an upper layer; A delay element for delaying the data from the second FIFO by one byte; First to fourth buffers for selectively outputting data from the first FIFO and the delay elements; First and second registers storing header information of data input to the first and second FIFOs; First and second multiplexers for selectively outputting header information from the first and second registers and data from the buffer unit; Third and fourth FIFOs for storing data from the first and second multiplexers and outputting the data to the ATM service connection point; And a control unit for controlling the delay element, the buffer unit, the register, the multiplexer, and the third and fourth FIFOs.

In the present invention configured as described above, two 8-bit data, for example 16-bit data, are input from an upper layer to form ATM cell data, and then 16-bit data is transmitted to the ATM layer, thereby enabling data to be transmitted at high speed and efficiently No memory is needed.

1A is a diagram showing a data format of an ATM cell,

1B shows a header structure at a user network interface (UNI)

1C is a diagram showing a header structure at a network node interface (NNI)

2A is a diagram showing a data format for each layer in the ATM communication system,

FIG. 2B is a diagram illustrating the SAR format of AAL type 1 shown in FIG. 2A,

3 is a block diagram showing a configuration of a fixed bit rate data processing apparatus in AAL type 1 according to an embodiment of the present invention;

4 is a flowchart illustrating an operation of the fixed bit rate data processing method in AAL type 1 according to the present invention.

DESCRIPTION OF THE REFERENCE NUMERALS

10, 11: first and second FIFOs 12: delay elements

13 to 16: first to fourth buffer units 20 21: first and second registers

22,23: first and second multiplexers 24,25: third and fourth FIFOs

26:

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1A to 1C, the long message of the user is divided into ATM cells and transmitted, and the received ATM cells are reassembled into one message and transmitted to the upper user .

1A is a diagram illustrating a data format of an ATM cell, FIG. 1B is a diagram illustrating a header structure at a user network interface (UNI), and FIG. 1C is a diagram illustrating a header structure at a network node interface (NNI).

Here, the ATM cell is divided into a 5-byte (or octet) header section and a 48-byte user information section. The 5-byte header is divided into a user network interface (UNI) The header structure of the UNI is divided into 4 bits of generic flow control (GFC) and 4 bits of virtual path identification (VPI) identifier.

The second byte is composed of a 4-bit virtual path identification number VPI and a 4-bit virtual channel identifier (VCI), and the third byte is an 8-bit virtual channel identification number (VCI) And the fourth byte is composed of a 4-bit virtual channel identification number (VCI), a 3-bit payload type (PT), and a 1-bit cell loss priority (CLP) The byte consists of 8 bits of header error control (HEC).

1C, the general flow control (GFC) in the first byte of the user network interface (NNI) is set to a virtual path identification number (VPI) in the header of the network node interface (NNI) It is possible to know the header structure of the user network interface (NNI) except that it is used. The ATM communication method has a hierarchical structure as shown in Table 1, and has standardized standards for each layer.

Layer Sub-layer function Upper layer Upper layer function ATM adaptation layer Convergence (CS) sub-layer Convergence function Cutting and recombination (SAR) Cutting function and recombination function ATM layer Generic flow control and cell header processing Physical layer Transmission Convergence (TC) HEC signal generation and extraction function Physical medium Bit time information function

As shown in Table 1, the ATM communication method is classified into a vertical structure such as a physical layer, an ATM layer, an ATM adaptation layer (AAL), and an upper protocol layer, and the AAL layer is divided into a truncation and recombination sub- segmentation and reassembly sublayer and a convergence sublayer (CS) sublayer. The physical layer is divided into a physical medium (PM) and a transmission convergence (TC) sublayer.

In addition, the service requested by the user in the ATM communication system can be classified as shown in Table 2 according to the characteristics thereof.

Types of Services Time relationship between ends Bit rate Connection mode Examples of services A species Real-time cast Equality Connectivity Odds ratio video signal B species Real-time cast variable Connectivity Variable rate video signal C species Non-real-time property variable Connectivity Connectivity data D species Non-real-time property variable Non-connectivity Non-connectivity data

The AAL protocol corresponding to the service is divided into AAL 1 to AAL 5 as shown in Table 3 below.

AAL form Typical functions AAL 1 Supports class A service with constant bit rate AAL 2 Supports Class B service with real-time property and variable bit rate AAL 3/4 Supports C and D service with variable bit rate AAL 5 Simplifies AAL 3/4 functionality to support high-speed services

In Table 3, the AAL layer is horizontally divided into AAL 1, AAL 2, AAL 3/4, and AAL 5 to efficiently process the corresponding service according to the type of the service.

Here, the AAL 1 layer includes a converging sublayer (CS) for transparently transmitting an A-type service data unit (U-SDU) having a constant bit rate, detecting a transmission error, and performing information identification and clock synchronization functions The ATM cell is divided into variable length data obtained by dividing the variable length data received from the convergence sublayer (CS) and transmitted to the ATM layer. The ATM cell is received and reassembled to recover the CS-PDU. ).

The convergence (CS) sublayer includes a common part convergence sublayer (CPCS) that performs functions common to the connectivity and non-connectivity services, a service specific convergence sublayer (SSCS: service specific convergence layer).

FIG. 2A is a diagram showing a data format for each layer in the ATM communication method. Here, a user service data unit (U-SDU) of an upper layer passes through an AAL-service access point (AAL-SAP) (AAL-SDU) and stored in the AAL FIFO. The AAL1 SAR layer divides the CS-PDU into 47 bytes according to the message to be transmitted by the user, adds 1 byte of SAR header, Protocol unit (SAR-PDU) is formed and sent down to the ATM layer via the ATM service connection point (ATM-SAP). In the ATM layer, a 5-byte ATM header is attached to form an ATM cell of 53 bytes, and the ATM cell is transmitted to another terminal or an ATM exchange through an optical path of the physical layer.

That is, in the AAL type 1 protocol, the U-SDU of the identity bit rate is transmitted at the same bit rate together with the related time information so that the clock information of the information source can be extracted from the receiving side, and in the converging sub- In the partitioning and reassembling sublayer, the CS-PDU is divided, and a 1-byte header is added and sent down to the ATM layer.

2B shows a SAR format of the AAL type 1 shown in FIG. 2A, wherein the transmitted message is divided into a 47-byte SAR-PDU payload and a 1-byte header, which has 4-bit sequence number protection Sequence number protection (SNP). The sequence number SN consists of a 1-bit convergence sublayer indicator (CSI) and a 3-bit sequence count (SC) The number protection (SNP) is made up of 3 bits of CRC and 1 bit of parity (P).

FIG. 3 shows the configuration of the present embodiment. In the conventional AAL type 1, data from the upper layer is processed in units of 8 bits. In the embodiment of the present invention, data is processed in units of 16 bits. In the AAL type 1 of this embodiment, when payload is 47 bytes and 47 bytes is to be processed by using a 16-bit data bus, 1 byte is delayed, and then data inputted after 1 byte is swapped (swapping) is required.

3, the data input to the FIFOs 10 and 11 are processed in 16-bit units in order to have registers as small as possible in the AAL layer and the ATM layer, The payload of 47 bytes, for example, 53 bytes, is processed.

That is, when data of a payload corresponding to one cell, for example, 47 bytes or more, is input to the first and second FIFOs 10 and 11, data processing is started. First, the ATM header and the SAR header And the header information of the first register 20 is formed by ATM_H5, ATM_H3, and ATM_H1. The header information of the second register 21 is composed of SAR_H, ATM_H4 and ATM_H2, and the user clock usr_clk information is input from the upper layer to the first FIFO 10 and the second FIFO 11, respectively.

Then, the controller 26 reads the payload data of the cell data, for example, 48 bytes, and then transmits payload data 16 bits at a time. At this time, the transmission of the payload data of the ATM cell is transmitted in units of 47 bytes, the 47 bytes of data are sequentially transmitted, the last 1 byte is delayed in the delay element 12, And transmitted.

Therefore, when the next ATM cell data is transmitted, one byte of data delayed by the delay element 12 and one byte of data from the first FIFO 10 are swapped and transmitted to each other, and the subsequent ATM cell data is transmitted The method of sequentially transmitting the same as the previous ATM cell data is repeatedly performed.

When payload data of an ATM cell is sequentially transmitted, 8-bit data from the first FIFO 10 is input to the first multiplexer 22 through the first buffer 13, The 8-bit data from the first multiplexer 22 is input to the second multiplexer 22 through the delay element 12 and the fourth buffer 16. Then, each data is selectively stored in the third and fourth FIFOs 24 and 25 by a control signal of the control unit 26 by 8 bits, and after the effective load of 47 bytes is selected and output, The header information (ATM_H5, ATM_H3, ATM_H1, SAR_H, ATM_H4, ATM_H2) from the two registers 20 and 21 is selectively output to the third and fourth FIFOs 24 and 25 by the control unit 26 .

Then, the third and fourth FIFOs 24 and 25 form an AAL-service data unit (AAL-SDU) based on the data stored by the output signal atm-w from the controller 26, (Not shown). The AAL1 SAR layer divides the CS-PDU into 47 bytes according to a message to be transmitted by the user, adds a 1-byte SAR header to the segmentation and re-association protocol unit (SAR-PDU) And sent down to the ATM layer via the ATM service access point (ATM-SAP). In the ATM layer, 5-byte ATM cells are formed and then transmitted to another terminal or an ATM exchange through an optical path of the physical layer.

FIG. 4 is a flowchart illustrating an operation of the fixed bit rate data processing method in AAL type 1 according to the present invention. In the first step (S1), two 8-bit data from an upper layer are divided into first and second The data is input to the FIFOs 10 and 11 and then enters a standby state. In the second step S2, it is determined whether data input to the first and second FIFOs 10 and 11 is 48 bytes or more.

If it is 48 bytes or less as a result of the determination in the second step S2, the third step S3 maintains the standby state of the first step S1, And the ATM cell header and the SAR header data recorded in the second register 20 and 21, respectively.

In the fourth step S4, if it is 48 bytes or more in the second step S2, the payload of 48 bytes is read out from the first and second FIFOs 10 and 11 to output only 47 bytes, In the delay element 12. In the fifth step S5, the data is input to the first and second FIFOs 10 and 11 from the upper layer, and then is put into a standby state. In the sixth step S6, the first and second FIFOs 10 and 11 , 11) is 46 bytes or more.

In the seventh step S7, if the result of the sixth step S6 is equal to or smaller than 46 bytes, the control unit 26 maintains the standby state of the fifth step S5, And the ATM cell header and the SAR header data recorded in the second register 20 and 21, respectively.

In the sixth step S6, if the number of bytes is equal to or larger than 46 bytes, one byte of data stored in the delay element 12 and 46 bytes of data from the first and second FIFOs 10 and 11 The load is read out and 47 bytes are output.

It should be noted that the drawings are not intended to limit the technical scope of the present invention to the embodiments shown in the drawings in order to facilitate understanding of the present invention.

As described above, according to the present invention, two 8-bit data, for example 16-bit data, are input from the upper layer to form ATM cell data, and then 16-bit data is transmitted to the ATM layer, No additional memory is required.

Claims (7)

First and second FIFOs (10, 11) in which data is input and stored in units of 8 bits from an upper layer; A delay element 12 for delaying the data from the second FIFO 11 by one byte; First to fourth buffer units (13 to 16) for selectively outputting data from the first FIFO (10) and the delay element (12); First and second registers (20, 21) storing header information of data input to the first and second FIFOs (10, 11); First and second multiplexers 22 and 23 for selectively outputting header information from the first and second registers 20 and 21 and data from the buffer units 13 and 16; Third and fourth FIFOs 24 and 25 for storing data from the first and second multiplexers 22 and 23 and outputting the data to the ATM service connection point (ATM-SAP); Control means 26 for controlling the delay element 12, the buffer units 13 to 16, the registers 20 and 21, the multiplexers 22 and 23 and the third and fourth FIFOs 24 and 25, Wherein the bit rate of the fixed bit rate data in the AAL type 1 is set to a predetermined value. The apparatus of claim 1, wherein the first and second FIFOs (10, 11) output data by a user clock (usr_clk) input from an upper layer. The apparatus of claim 1, wherein the first buffer unit (13), the second buffer unit (14), the third buffer unit (15), and the fourth buffer unit (16) Wherein the first and second bit rates are different from each other. The method of claim 1, wherein header information (ATM_H5, ATM_H3, ATM_H1) for data input to the first FIFO (10) is stored in the first register (20) Wherein header information (SAR_H, ATM_H4, ATM_H2) for data input to the AAL type 1 is stored. 2. The apparatus according to claim 1, wherein the first and second multiplexers (22, 23) select one of the ATM cell header stored in the first and second registers (22, 23) And outputting the 47 bytes of data after outputting the SAR header of the fixed bit rate data. The method according to claim 1, wherein the third and fourth FIFOs (24, 25) output ATM cell data by an output signal (atm_w) from the control means (26) Bit rate data processing device. A first step (S1) in which data of each 8-bit unit is input from the upper layer to the first and second FIFOs (10, 11) and then enters a standby state; A second step S2 of determining whether or not the data input to the first and second FIFOs 10 and 11 is 48 bytes or more; The control means 26 keeps the first and second registers 20 and 21 in the waiting state in the first step S1 if the number of bytes is 48 bytes or less, A third step (S3) of outputting an ATM cell header and SAR header data recorded in the ATM cell header and the SAR header data; If it is 48 bytes or more in the second step S2, the payload of 48 bytes is read out from the first and second FIFOs 10 and 11 to output only 47 bytes, and one byte is stored in the delay element 12 A fourth step S4; A fifth step (S5) in which data from the upper layer is input to the first and second FIFOs (10, 11) and then is put into a standby state again; A sixth step (S6) of determining whether or not the data input to the first and second FIFOs 10 and 11 is 46 bytes or more; If the number of bytes is equal to or larger than 46 bytes, the control means 26 controls the first and second registers 20 and 21 to be in the standby state in the fifth step S5, A seventh step (S7) of outputting the ATM cell header and the SAR header data recorded in the ATM cell header and the SAR header data; If it is 46 bytes or more in the sixth step S6, one byte of data stored in the delay element 12 and a payload of 46 bytes from the first and second FIFOs 10 and 11 are read and 47 bytes are read out And an eighth step (S8) of outputting the fixed bit rate data.