JP5176646B2 - Error correction function confirmation circuit, error correction function confirmation method, computer program thereof, and storage device - Google Patents

Description

  The present invention relates to a storage device such as a random access memory (hereinafter referred to as RAM). In particular, the present invention relates to a circuit and method for confirming the ECC function of an error correcting code (hereinafter referred to as ECC) circuit in a storage device.

  In a storage device such as a RAM, a soft error may occur due to α rays or the like. Therefore, an ECC circuit that can correct such an error may be provided.

  As a technique for confirming the ECC function of the ECC circuit, there is, for example, Patent Document 1. In the background art disclosed in Patent Document 1, a data inversion circuit is provided for each of actual data that is original data and ECC data that is added separately from the actual data in order to correct an error in the data. A predetermined bit of write data is inverted by the data inversion circuit in accordance with preset bit inversion data. This causes a pseudo error.

JP 2007-41665 A

  In addition, a method of providing a function capable of directly writing data to the RAM without using an ECC circuit and generating a pseudo error by software is also conceivable. For example, software in which only an arbitrary bit is inverted based on data once read from the RAM is generated by software, and directly written into the RAM without going through the ECC circuit. This causes a pseudo error.

  However, in the technique disclosed in Patent Document 1, it is necessary to provide an extra circuit for setting and storing bit inversion data for instructing data inversion, such as a flip-flop.

  In general, when checking the ECC function, it is necessary to frequently change the bit to be inverted in order to check various patterns of errors. In any of the technique described in Patent Document 1 and the above-described software method, it is necessary to rewrite the register in order to change the bit to be inverted. This is very troublesome when it is desired to easily and efficiently check the ECC function.

  The present invention has been proposed in view of the above problems. An object of the present invention is to provide an ECC function confirmation circuit, an ECC function confirmation method, a computer program thereof, and a storage device that can easily and efficiently confirm an ECC function.

The ECC function confirmation circuit according to the present invention is for confirming an error correction function of a storage device . An ECC generation circuit, a data inversion circuit, and an ECC error detection circuit are included. The ECC generation circuit adds error correction data to the write data and stores it in the storage device. The data inversion circuit divides the output data of the memory device into two parts, upper N bits and lower N bits, and excludes either the upper N bits or the lower N bits of the output data and the lower N bits of the write data Perform logical OR operation. Data generated by combining the result of the exclusive OR operation and the other of the upper N bits or the lower N bits of the output data is overwritten on the data stored in the ECC generation circuit of the storage device. The ECC error detection circuit is characterized by detecting a bit in which an error has occurred from the output data of the storage device after the data inversion circuit overwrites the data .

The ECC function confirmation method according to the present invention is for confirming the ECC function using the error correction function confirmation circuit.

First, in the error correction function confirmation method for confirming the error correction function of the storage device, the error correction data is added to the write data and stored in the storage device, and the output data of the storage device is divided into upper N bits and lower N bits. Then, an exclusive OR operation is performed on one of the upper N bits or the lower N bits of the output data and the lower N bit of the write data, and the result of the exclusive OR operation and the upper N bits or the lower side of the output data The data generated by combining the other of the N bits is overwritten on the data stored by the ECC generation circuit of the storage device, and after the data inversion circuit overwrites, the bit in which an error has occurred from the output data of the storage device Detect .

A storage device according to the present invention includes the error correction function confirmation circuit.

  Thus, according to the present invention, it is not necessary to provide an extra circuit for setting and storing bit inversion data for instructing data inversion as in Patent Document 1. Since the data inversion instruction is given by the write data to the storage device, it is not necessary to frequently rewrite the register to change the bit to be inverted.

  According to the ECC function confirmation circuit, the ECC function confirmation method, the computer program, and the storage device according to the present invention, the ECC function can be confirmed easily and efficiently.

  FIG. 1 is a block diagram showing a first embodiment of the overall configuration of an ECC function confirmation circuit according to the present invention. The output of the CPU 1 is connected to the input of the ECC generation circuit 2 and the input of the data inversion circuit 3 through a 32-bit bus. The CPU 1 outputs WDATA [31: 0] that is write data.

  The output of the ECC generation circuit 2 and the output of the data inversion circuit 3 are connected to the input of the selector 4 via a 48-bit bus, respectively. In the first embodiment, 4 bits of error correction data are added for every 8 bits of WDATA [31: 0] to correct a 1-bit error. Therefore, the ECC generation circuit 2 generates ECCDATA [15: 0], which is error correction data corresponding to WDATA [31: 0], and outputs WDATA [31: 0] + ECCATA [15: 0].

  On the other hand, in addition to WDATA [31: 0], KDATA [47: 0], which is output data of the 48-bit holding register 7, is input to the data inverting circuit 3, and CDATA [47: 0] is output.

  The output of the selector 4 is connected to the input of the ECCRAM 5 via a 48-bit bus. In the selector 4, in accordance with the ECCOFF signal, whichever of the two inputs of input WDATA [31: 0] + ECCDATA [15: 0] from the input terminal 0 and input CDATA [47: 0] from the input terminal 1 is selected. Is selected and output.

  The output of the ECCRAM 5 is connected to the input of the ECC error detection and correction circuit 6 and the input of the 48-bit holding register 7 through a 48-bit bus. The ECCRAM 5 is a main storage device of the CPU 1 and stores WDATA [31: 0] and corresponding ECCDATA [15: 0]. Data stored in the ECCRAM 5 is read in response to a read instruction from the CPU 1.

  The output of the ECC error detection and correction circuit 6 is connected to the input of the CPU 1 by a 32-bit bus. The ECC error detection and correction circuit 6 detects an error in the data read from the ECCRAM 5 and outputs RDATA [31: 0], which is data in which the error has been corrected.

  The output of the 48-bit holding register 7 is connected to the input of the data inverting circuit 3 by a 48-bit bus. The 48-bit holding register 7 holds read data from the ECCRAM 5 and outputs KDATA [47: 0] that is the held data.

  The operation of the first embodiment configured as described above will be described. Write data WDATA [31: 0] to the ECCRAM 5 is output from the CPU 1. The ECC generation circuit 2 generates ECCDATA [15: 0] corresponding to WDATA [31: 0]. WDATA [31: 0] + ECCATA [15: 0] in which ECCATA [15: 0] is added to WDATA [31: 0] is output. Usually, since the ECC function is enabled, the ECCOFF signal is 0 (L level). Therefore, the selector 4 selects and outputs the input WDATA [31: 0] + ECCATA [15: 0] from the input terminal 0. In the ECCRAM 5, WDATA [31: 0] + ECCATA [15: 0] is written.

  When checking the ECC function, the ECC function is once invalidated in order to generate a pseudo error, so the ECCOFF signal is set to 1 (H level). WDATA [31: 0] + ECCATA [15: 0] stored in the ECCRAM 5 is read and held in the 48-bit holding register 7. WDATA [31: 0] instructing data inversion is output from the CPU 1. The data inversion circuit 3 is instructed to invert data by WDATA [31: 0], and inverts a predetermined bit of KDATA [47: 0] output from the 48-bit holding register 7. The data inversion circuit 3 outputs CDATA [47: 0], which is data obtained by inverting a predetermined bit of KDATA [47: 0]. Since the ECCOFF signal is 1, the selector 4 selects and outputs the input CDATA [47: 0] from the input terminal 1. The ECCRAM 5 is overwritten with CDATA [47: 0]. As a result, a pseudo error occurs.

  The ECCOFF signal is returned to 0 (L level), and the ECC function is enabled. CDATA [47: 0] stored in the ECCRAM 5 is read and input to the ECC error detection and correction circuit 6. Since predetermined bits of CDATA [47: 0] are inverted, an error is detected by the ECC error detection / correction circuit 6, and RDATA [31: 0], which is data in which the error has been corrected, is output. By checking whether or not RDATA [31: 0] matches the original write data WDATA [31: 0], it is possible to check whether or not the ECC function has operated correctly.

  The data inverting circuit 3 will be described in detail with reference to FIG. FIG. 2 is a block diagram showing an example of the internal configuration of the data inverting circuit 3. As described in FIG. 1, WDATA [31: 0] and KDATA [47: 0] are input to the data inversion circuit 3. A data inversion instruction is given by 32-bit WDATA [31: 0], and predetermined bits of 48-bit KDATA [47: 0] are inverted. Therefore, KDATA [47: 0] is divided into upper 24 bits KDATA [47:24] and lower 24 bits KDATA [23: 0] in the data inverting circuit 3. For KDATA [47:24] and KDATA [23: 0] divided into 24 bits, the bits inverted by WDATA [23: 0], which are the lower 24 bits of WDATA [31: 0], are indicated. Is done.

  The data inverting circuit 3 includes EOR gates 31 and 32. The EOR gate 31 receives WDATA [23: 0] and KDATA [47:24]. The EOR gate 32 receives WDATA [23: 0] and KDATA [23: 0]. The output of the EOR gate 31 is input to the input terminal 1 of the selector 33, and the output of the EOR gate 32 is input to the input terminal 0 of the selector 34. KDATA [47:24] is input to the other input terminal 0 of the selector 33, and KDATA [23: 0] is input to the other input terminal 1 of the selector 34. The selectors 33 and 34 both select and output one of the two inputs according to WDATA [31] which is the most significant bit of WDATA [31: 0]. The output CDATA [47:24] of the selector 33 and the output CDATA [23: 0] of the selector 34 become the output CDATA [47: 0] of the data inversion circuit 3.

  For example, when the bits included in KDATA [47:24] are inverted, WDATA [31: 0] has the most significant bit WDATA [31] of 1 (H level) and the lower 24 bits WDATA [23: 0]. CPU 1 outputs WDATA [31: 0] in which the bit corresponding to the inverted KDATA [47:24] bit is 1 (H level). The EOR gate 31 inverts KDATA [47:24] bits corresponding to 1 (H level) bits of WDATA [23: 0]. Since the most significant bit WDATA [31] of WDATA [31: 0] is 1 (H level), the selector 33 selects the input from the input terminal 1 and outputs it. Accordingly, the output of the EOR gate 31, that is, the data in which the predetermined bits of KDATA [47:24] are inverted is selected and output. On the other hand, the selector 34 selects and outputs KDATA [23: 0].

  As shown in FIG. 1, the first embodiment has a configuration in which a 48-bit ECCRAM 5 exceeding the data bus width of 32 bits of the CPU 1 is mounted. However, as shown in FIG. 2, KDATA [47: 0] is divided into upper 24 bits and lower 24 bits. The most significant bit WDATA [31] of WDATA [31: 0] switches whether the bits included in the upper and lower bits of KDATA [47: 0] are inverted. Thereby, an arbitrary bit of KDATA [47: 0] can be inverted. Therefore, an arbitrary error can be generated in a pseudo manner with respect to the data stored in the ECCRAM 5. Since the data inversion instruction is given by WDATA [31: 0], there is no need to provide an extra circuit for setting and storing bit inversion data for instructing data inversion as in Patent Document 1. Also, it is not necessary to rewrite the register frequently to change the bit to be inverted.

  FIG. 3 is a block diagram showing a second embodiment of the overall configuration of the ECC function confirmation circuit according to the present invention. In the second embodiment, the ECCRAM 5 at the time of the write operation holds and outputs the previous read data. Therefore, in the second embodiment, the 48-bit holding register 7 that holds the read data from the ECCRAM 5 is unnecessary, and the output of the ECCRAM 5 is connected to the input of the data inverting circuit 3.

  The second embodiment shown in FIG. 3 includes a control signal generation unit 8. The control signal generator 8 includes the CPU 1 to the CPU. ADD signal and CPU. WRX signal is input. The control signal generator 8 outputs a READY signal to the CPU 1 in response to the ECCOFF signal. In addition, the control signal generator 8 stores the RAM. ADD signal and RAM. WRX signal is output. Other configurations are the same as those of the first embodiment shown in FIG.

  The operation of the second embodiment configured as described above will be described with reference to the timing chart of FIG. FIG. 4 shows data CDATA [47] in which read data KDATA [47: 0] is read from the ECCRAM 5 and a predetermined bit is inverted by the data inversion circuit 3 in the confirmation of the ECC function in the second embodiment shown in FIG. 47: 0] is overwritten on the ECCRAM 5 and a timing chart until a pseudo error occurs is shown. Here, FIG. 4 is a timing diagram illustrating an Advanced High-performance Bus (hereinafter referred to as AHB) as an example. AHB is defined as a bus specification. Note that the timing diagram of FIG. 4 is described using signal names that match those in FIG. 3 instead of signal names generally used in AHB. Replacement with signal names commonly used in AHB is to replace CK with HCLK, CPU. ADDR to CPU. HADDR, CPU. WRX to CPU. Inversion of HWRITE is possible by setting READY to HREADY.

  As already described, in order to generate a pseudo error, the ECCRAM 5 performs a write operation after the read operation. Therefore, the CPU 1 instructs the ECCRAM 5 to read → write. At that time, a dummy lead may be inserted depending on the CPU 1. If a dummy read is inserted, unintended data may be read. Therefore, in the second embodiment shown in FIG. 3, the ECCRAM 5 performs a write operation after a read operation only by a write instruction from the CPU 1.

  In FIG. 4, a CK signal is a clock, and cyc1 to cyc5 are periods thereof. CPU. The ADD signal is a signal that the CPU 1 indicates an address. The WRX signal is a signal that the CPU 1 instructs to write. CPU. The WDATA signal corresponds to the write data WDATA [31: 0] output by the CPU 1 in FIG. The READY signal is a signal for applying a wait to the CPU 1. That is, while the READY signal is output, the CPU 1 does not issue the next instruction. RAM. The CE signal is not shown in FIG. 3, but is a signal input to the ECCRAM 5 from a general address decoder. RAM. The ADD signal is a signal in which the ECCRAM 5 indicates an address. The WRX signal is a signal that the ECCRAM 5 is instructed to write. In the second embodiment, the ECCRAM 5 is RAM. CE signal is at L level and RAM. A write operation is performed when the WRX signal is at the L level. ECCRAM 5 is RAM. CE signal is at L level and RAM. A read operation is performed when the WRX signal is at the H level. RAM. The RDATA signal corresponds to the read data KDATA [47: 0] output from the ECCRAM 5 in FIG. RAM. The WDATA signal corresponds to the data CDATA [47: 0] output from the data inversion circuit 3 in FIG.

  As described above, when checking the ECC function, the ECCOFF signal is set to 1 (H level) in order to generate a pseudo error (cyc1 to cyc5). CPU1 is CPU. The ECC function confirmation target address AA is indicated by the ADD signal (cyc2). Write is instructed by the WRX signal (cyc2), and CPU. The WDATA signal is set as write data WA (cyc3). When the ECCOFF signal is 1 (H level), the control signal generation unit 8 is connected to the CPU. In response to a write instruction by the WRX signal, a READY signal is output to the CPU 1 (cyc3). Therefore, the CPU 1 does not issue the next instruction and the CPU. The WDATA signal is maintained as the write data WA (cyc4). The ECCRAM 5 is supplied from the control signal generator 8 to the RAM. Address AA is indicated by the ADD signal (cyc3 to cyc4), and RAM. The WRX signal instructs reading in cyc3 and writing in cyc4 (cyc3 to cyc4). On the other hand, RAM. The CE signal is input to the ECCRAM 5 (cyc3 to cyc4).

  In the cycle cyc3, the RAM. CE signal is at L level and RAM. Since the WRX signal is H level, the ECCRAM 5 is RAM. A read operation is performed from the address AA indicated by the ADD signal. RAM. The RDATA signal becomes data RA read from the address AA.

  In the cycle cyc4, the RAM. CE signal is at L level and RAM. Since the WRX signal is L level, the ECCRAM 5 is RAM. A write operation is performed on the address AA indicated by the ADD signal. As described above, in the second embodiment, the ECCRAM 5 during the write operation holds and outputs the immediately preceding read data. Therefore, RAM. The RDATA signal remains as data RA. Therefore, the data inversion circuit 3 is CPU. A data inversion instruction is given by the write data WA of the WDATA signal, and data WA ^ RA in which a predetermined bit of the data RA is inverted is output. That is, RAM. The WDATA signal is data WA ^ RA. Since the ECCOFF signal is 1 (H level), the data WA ＾ RA is written to the address AA of the ECCRAM 5 via the selector 4.

  Thus, when the ECCOFF signal is 1 (H level), the control signal generation unit 8 is connected to the CPU. In response to a write instruction by the WRX signal, a READY signal is output to the CPU 1 and a wait is applied to the CPU 1. While the READY signal is output, the CPU 1 does not issue the next instruction and the CPU. The WDATA signal remains as write data WA until the cycle cyc4. The control signal generator 8 is a RAM. By outputting the write instruction by the WRX signal not in the cycle cyc3 but in the cycle cyc4, the ECCRAM 5 can perform the write operation (cyc4) after the read operation (cyc3) only by the write instruction from the CPU1. As a result, there is no possibility that unintended data is read by the dummy read.

  Even if the ECCRAM 5 performs a write operation after a read operation only by a write instruction from the CPU 1, the CPU 1 can issue a normal read instruction. When the CPU 1 issues a normal read instruction, data RDATA [31: 0] that has undergone error detection and correction by the ECC error detection and correction circuit 6 is input to the CPU 1. Therefore, when the ECC function confirmation program or the like is read from a region other than the ECC function confirmation target area of the ECCRAM 5, the ECC function is validated. Therefore, when the ECC function is confirmed, there is no problem even if a soft error occurs in an area other than the ECC function confirmation target area.

  In addition, since the ECCRAM 5 at the time of the write operation holds and outputs the immediately preceding read data, the 48-bit holding register 7 is unnecessary in the second embodiment. Therefore, there is an effect that the circuit can be made small.

  With reference to FIG. 5, the ECC function confirmation method in 2nd Embodiment is demonstrated. FIG. 5 shows a flow of ECC function confirmation according to the second embodiment. Initially, the reverse instruction mode is turned off (S1). This step S1 is executed when the ECCOFF signal is set to 0 (L level).

  Arbitrary write data WDATA [31: 0] is instructed to be written to the ECC function confirmation target address (S2). Since the ECCOFF signal is set to 0 (L level), WDATA [31: 0] + ECCATA [15: 0] to which ECCDATA [15: 0] is added by the ECC generation circuit 2 is sent to the ECCRAM 5 via the selector 4. Written.

  The ECCOFF signal is set to 1 (H level), and the inversion instruction mode is turned on (S3).

  The data read (S4) and the inversion instruction data write (S5) are executed by instructing the write of the write data WDATA [31: 0] that inverts an arbitrary bit to the ECC function confirmation target address. The Accordingly, as described with reference to FIG. 4, the ECCRAM 5 performs the write operation after the read operation according to the control signal generation unit 8. That is, the read data KDATA [47: 0] is read from the ECCRAM 5. Data CDATA [47: 0] in which a predetermined bit of the read data KDATA [47: 0] is inverted is given via the selector 4 by a data inversion instruction given by the write data WDATA [31: 0] to the ECCRAM 5 The ECCRAM 5 is overwritten. Steps S4 and S5 can be repeated for any address and any data without intervening other processing such as register rewriting thereafter.

  The ECCOFF signal is set to 0 (L level), and the inversion instruction mode is turned off (S6).

  Read is instructed to the ECC function confirmation target address (S7). An error is detected by the ECC error detection and correction circuit 6 for a pseudo error caused by inversion of a predetermined bit of the read data KDATA [47: 0], and RDATA [31: 0], which is data in which the error has been corrected, is output. Is done.

  It is confirmed whether or not the ECC function has been operated correctly (S8). This step S8 is executed, for example, by comparing RDATA [31: 0] with the prepared expected value and confirming a coincidence / mismatch, or by confirming with a general error occurrence bit. .

  As described above, also in the second embodiment, it is possible to generate an arbitrary error in a pseudo manner as in the first embodiment. Since the data inversion instruction is given by WDATA [31: 0], it is not necessary to provide an extra circuit for setting and storing the bit inversion data for instructing the data inversion as in Patent Document 1, and the bit to be inverted There is no need to rewrite the register frequently to change

Here, the correspondence with the claims is as follows.
The ECCRAM 5 is an example of a storage device.
The ECC generation circuit 2, the ECCRAM 5, and the ECC error detection / correction circuit 6 are examples of an error correction circuit.
WDATA [31: 0] is an example of write data.
KDATA [47: 0] is an example of read data.
CDATA [47: 0] is an example of data in which a predetermined bit is inverted.
The data inverting circuit 3 is an example of a data inverting circuit.
The selector 4 is an example of a circuit to be selected.
The 48-bit holding register 7 is an example of a holding circuit.
The EOR gates 31 and 32 are examples of EOR gates included in the data inversion circuit.
The data write step S2 is an example of a step in which write data is written to the storage device.
The data read step S4 is an example of a step in which read data is read from the storage device.
The inversion instruction data write step S5 is an example of a step in which data in which a predetermined bit is inverted is overwritten in the storage device.
Data read step S7 and ECC function confirmation step S8 are examples of steps in which the overwritten data is read from the storage device and the error correction function of the error correction circuit is confirmed.

  As described above in detail, according to the first embodiment of the present invention, when the ECC function is confirmed, the data inversion circuit 3 that inverts a predetermined bit of the read data KDATA [47: 0] from the ECCRAM 5. Causes a pseudo error. The data inversion circuit 3 is instructed to invert data by the write data WDATA [31: 0] to the ECCRAM 5.

  In the data inverting circuit 3, 48-bit read data KDATA [47: 0] from the ECCRAM 5 is divided into upper 24 bits and lower 24 bits. According to the most significant bit WDATA [31] of the 32-bit write data WDATA [31: 0], whether the bit included in the upper or lower order of KDATA [47: 0] is inverted is switched.

  Thereby, an arbitrary bit of KDATA [47: 0] can be inverted. Even in the configuration in which the 48-bit ECCRAM 5 exceeding the data bus width 32 bits of the CPU 1 is mounted as in the first embodiment, an arbitrary error can be generated in a pseudo manner with respect to the data stored in the ECCRAM 5. It becomes. Since the data inversion instruction is given by WDATA [31: 0], there is no need to provide an extra circuit for setting and storing bit inversion data for instructing data inversion as in Patent Document 1. Also, it is not necessary to rewrite the register frequently to change the bit to be inverted. It is possible to easily and efficiently check the ECC function.

  Also, the second embodiment of the present invention can provide the same effects as those of the first embodiment. In addition, in the second embodiment, the control signal generation unit 8 receives the CPU. In response to a write instruction by the WRX signal, a READY signal is output to the CPU 1 and a wait is applied to the CPU 1. Thus, the ECCRAM 5 can perform the write operation after the read operation only by the write instruction from the CPU 1. As a result, there is no possibility that unintended data is read by the dummy read. In the second embodiment, the ECCRAM 5 at the time of the write operation holds and outputs the previous read data, so that the 48-bit holding register 7 is unnecessary. Therefore, there is an effect that the circuit can be made small.

Note that the present invention is not limited to the above-described embodiment, and it goes without saying that various improvements and modifications can be made without departing from the spirit of the present invention.
For example, in the ECC function confirmation flow of the second embodiment shown in FIG. 5, the write of arbitrary write data WDATA [31: 0] is instructed in step S2, but the present invention is not limited to this. Usually, since initialization is performed by full-surface writing of the storage device at the time of activation, it may be used.

  In both the first embodiment shown in FIG. 1 and the second embodiment shown in FIG. 3, the ECC generation circuit 2 and the ECC error detection / correction circuit 6 are shown separately from the ECCRAM 5. However, it is not limited to this. The ECCRAM 5 may be configured to include ECC generation and ECC error detection and correction.

  Further, the read data KDATA [47: 0] input to the data inverting circuit 3 is taken from the output of the ECCRAM 5, but may be taken from the output of the ECC error detection and correction circuit 6. In the case of this configuration, the same effect as in the above-described embodiment can be obtained by providing a selector that switches between valid and invalid of ECC error detection and correction in accordance with the ECCOFF signal in the subsequent stage of the ECC error detection and correction circuit 6. Further, if a signal indicating a write instruction is input to the selector, even if the ECCRAM 5 performs the write operation after the read operation only by the write instruction from the CPU 1, the read operation with the ECC function enabled can be performed. It becomes possible. Therefore, when the ECC function is confirmed, there is no problem as in the second embodiment even if a soft error occurs in a region other than the ECC function confirmation target area.

1 is a block diagram of a first embodiment. It is a block diagram which shows an example of an internal structure of a data inversion circuit. It is a block diagram of 2nd Embodiment. It is a timing diagram of a 2nd embodiment. It is a flowchart of ECC function confirmation of 2nd Embodiment.

1 CPU
2 ECC generation circuit 3 Data inversion circuit 4 Selector 5 ECCRAM
6 ECC error detection and correction circuit 7 48-bit holding register 8 Control signal generators 31 and 32 EOR gates 33 and 34 Selector CDATA [47: 0] Data ECCATA [15: 0] with predetermined bits inverted Error correction data KDATA [ 47: 0] Read data RDATA [31: 0] Error corrected data WDATA [31: 0] Write data

Claims (5)

In the error correction function confirmation circuit for confirming the error correction function of the storage device,
  An ECC generation circuit for adding error correction data to write data and storing the data in the storage device;
  The output data of the storage device is divided into two, upper N bits and lower N bits, and one of the upper N bits or the lower N bits of the output data and the lower N bits of the write data are exclusive logic Performs a sum operation, and overwrites the data stored by the ECC generation circuit of the storage device with data generated by combining the result of the exclusive OR operation and the other of the upper N bits or the lower N bits of the output data A data inversion circuit to
  An error correction function confirmation circuit comprising: an ECC error detection circuit for detecting a bit in which an error has occurred from the output data of the storage device after the data inversion circuit performs the overwriting. 2. The error correction function confirmation circuit according to claim 1, further comprising a holding register that temporarily stores output data of the storage device and outputs the data to the data inversion circuit. 2. A selector that receives an output of the ECC generation circuit and an output of the data inversion circuit, selects an output of the ECC generation circuit or an output of the data inversion circuit, and stores it in the storage device. Error correction function confirmation circuit. In the error correction function confirmation method for confirming the error correction function of the storage device,
  Adding error correction data to the write data and storing it in the storage device;
  The output data of the storage device is divided into two, upper N bits and lower N bits, and one of the upper N bits or the lower N bits of the output data and the lower N bits of the write data are exclusive logic Performs a sum operation, and overwrites the data stored by the ECC generation circuit of the storage device with data generated by combining the result of the exclusive OR operation and the other of the upper N bits or the lower N bits of the output data And steps to
  And a step of detecting a bit having an error from the output data of the storage device after the data inversion circuit performs the overwriting. Storage device, characterized in that it comprises an error correction function check circuit according to what Re one of claims 1 to 3.

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