TWI652688B - Dynamic random access memory and its operation method - Google Patents

Abstract

The disclosure provides a dynamic random access memory (DRAM) with a data correction function and an operation method thereof. The dynamic random access memory includes a memory array; a control circuit configured to receive a read address and a defect information of the read address; and an access circuit configured to receive the read information from the control circuit. Generating a read data from the memory array at the read address; and a modification circuit connected to the access circuit and the control circuit, wherein the modification circuit is configured to modify the read according to the defect information Part of the information.

Description

Dynamic random access memory and operation method thereof

This application claims the priority and benefits of US Provisional Application No. 62 / 610,341 filed on December 26, 2017 and US Official Application No. 15 / 904,912 filed on February 26, 2018. And the content of the official US application is incorporated herein by reference in its entirety. The present disclosure relates to a dynamic random access memory (DRAM) and an operation method thereof, and more particularly to a dynamic random access memory with a data correction function and an operation method thereof.

Dynamic random access memory (DRAM) is a type of random access memory. This type of random access memory stores each bit of data in a separate capacitor. The simplest DRAM cell includes a single n-type metal-oxide-semiconductor (NMOS) transistor. And a single capacitor. If the charge is stored in a capacitor, the unit is called storage logic high according to the convention used. If no charge is present, the cell is said to store a logic low. Since the charge in the capacitor is consumed over time, the DRAM system needs an update circuit to periodically update the charge stored in the capacitor. Since capacitors can only store a very limited amount of charge, in order to quickly distinguish the difference between logic 1 and logic 0, two bit lines (BL) are usually used for each bit. One bit is called bit line true (BLT), and the other is bit line complement (BLC). The gate of a single NMOS transistor is controlled by a word line (WL). The above description of the "prior art" is only for providing background technology. It does not recognize that the above description of the "prior technology" reveals the subject of this disclosure, does not constitute the prior technology of this disclosure, and any description of the "prior technology" above Neither shall be part of this case.

The disclosure provides a dynamic random-access memory (DRAM) including a memory array; a control circuit configured to receive a read address and a defect information of the read address; An access circuit configured to generate a read data from the memory array according to the read address from the control circuit; and a modification circuit connected to the access circuit and the control circuit, wherein the modification The circuit is configured to modify a portion of the read data based on the defect information. In some embodiments, the modification circuit includes a flip circuit configured to modify the portion of the read data, and the flip circuit flips at least one bit of the read data from a first logic state according to the defect information To a second logic state. In some embodiments, the modification circuit further includes a bit register, configured to store the defect information from the control circuit. In some embodiments, the DRAM further includes an error correction circuit connected to the modification circuit. In some embodiments, the modification circuit is configured to modify a first portion of the read data, and the error correction circuit is configured to correct a second portion of the read data that has not been modified by the modification circuit. The disclosure further provides a dynamic random access memory including a memory array; a control circuit configured to receive a read address; and an access circuit configured to respond to the read bit from the control circuit A read data is generated from the memory array; a modification circuit; and an error correction circuit connected to the modification circuit and configured to generate a defect information of the read data; wherein the modification circuit includes a connection to An address register of the control circuit and a flip circuit connected to the access circuit. The address register is connected to the error correction circuit to receive the defect information of the read address. Configured to modify a portion of the read data based on the defect information. In some embodiments, the flip circuit is configured to modify the portion of the read data, the flip circuit flips at least one bit of the read data from a first logic state to a second logic according to the defect information status. In some embodiments, the error correction circuit is connected to the control circuit, and the error correction circuit is configured to send a signal to the control circuit when the read data includes an uncorrectable error. In some embodiments, the control circuit is configured to schedule a corrective operation of the modification circuit. The disclosure also provides a method for operating a dynamic random access memory, including: receiving a read address; generating a read data from a memory array according to the read address; and receiving a defect of the read data. Information; and modifying a portion of the read data to generate a modified data based on the defective data. In some embodiments, modifying a part of the read data includes: flipping at least one bit of the read data from a first logic state to a second logic state according to the defect information. In some embodiments, the operation method further includes: storing the defect information in a bit register, and at least one bit of the read data according to the defect information from the address register. Flip from a first logic state to a second logic state. In some embodiments, the operation method includes: modifying a first part of the read data, and correcting a second part of the read data. In some embodiments, a first part of modifying the read data is performed by a modification circuit, and a second part of correcting the read data is performed by an error correction circuit. In some embodiments, the operation method further includes: determining whether the modified data includes an uncorrectable error. In some embodiments, the operation method further includes: when the modification data includes an uncorrectable error, generating update defect information. In some embodiments, the operation method further includes: modifying the modification data according to the updated defect information. In some embodiments, the operation method further includes: scheduling a subsequent modification operation to modify the modification data including the uncorrectable error. In some embodiments, a defect information generating the read address is performed after an error correction circuit performs an error correction code operation. This disclosure discloses that the data is corrected by the flip operation before the data enters the ECC circuit, so that the ECC circuit does not need to spend too much time on the data correction operation. On the contrary, if the flip operation is not used to correct the data, the ECC circuit needs to Long time to correct reading data. Traditionally, if a data row has a defective bit, all data stored in the data row will be marked and replaced with another row, which requires additional storage space. The technical features and advantages of this disclosure have been outlined quite extensively above, so that the detailed description of this disclosure below can be better understood. Other technical features and advantages that constitute the subject matter of the patent application of this disclosure will be described below. Those with ordinary knowledge in the technical field to which this disclosure belongs should understand that the concepts and specific embodiments disclosed below can be used quite easily to modify or design other structures or processes to achieve the same purpose as this disclosure. Those with ordinary knowledge in the technical field to which this disclosure belongs should also understand that such equivalent constructions cannot be separated from the spirit and scope of this disclosure as defined by the scope of the attached patent application.

The following description of this disclosure is accompanied by the drawings incorporated in and constitutes a part of the description to explain the embodiment of this disclosure, but this disclosure is not limited to this embodiment. In addition, the following embodiments can be appropriately integrated with the following embodiments to complete another embodiment. "One embodiment", "embodiment", "exemplified embodiment", "other embodiment", "another embodiment", etc. refer to the embodiment described in this disclosure may include specific features, structures, or characteristics, however Not every embodiment must include the particular feature, structure, or characteristic. Furthermore, the repeated use of the phrase "in the embodiment" does not necessarily refer to the same embodiment, but may be the same embodiment. In order that this disclosure may be fully understood, the following description provides detailed steps and structures. Obviously, the implementation of this disclosure does not limit the specific details known to those skilled in the art. In addition, the known structures and steps are not described in detail, so as not to unnecessarily limit the present disclosure. The preferred embodiments of the present disclosure are detailed below. However, in addition to the embodiments, the disclosure can be widely implemented in other embodiments. The scope of this disclosure is not limited to the content of the embodiments, but is defined by the scope of patent application. FIG. 1 is a functional block diagram illustrating a dynamic random access memory (DRAM) 100A according to some embodiments of the present disclosure. Referring to FIG. 1, in some embodiments, the DRAM 100A includes a data storage 10, a control circuit 20 connected to the data storage 10, a memory array 30, and a memory array 30 connected to the control circuit 20 and a memory array 30. The fetch circuit 40, a modification circuit 50 connected to the access circuit 40 and the control circuit 20, and an error-correction code (ECC) circuit 60 connected to the modification circuit 50. In some embodiments, the data storage 10 is configured to store memory of defective memory cell information, and the defective memory cell information includes a memory cell position, that is, a row address of a defective memory cell including a bit. In some embodiments, the data store 10 includes a defect data table configured to store defect memory cell information. In some embodiments, the defective bit cannot store the charge normally; for example, the defective bit is always at a low voltage during the test, and thus is identified through a test process at the factory or during operation. In some embodiments, the data storage 10 may be selectively disposed inside or outside the DRAM 100A. In some embodiments, the control circuit 20 is configured to control the data storage 10, the access circuit 40, and the modification circuit 50. In some embodiments, the control circuit 20 receives the defect memory cell information from the defect data table of the data storage 10. In some embodiments, the control circuit 10 executes a write cycle to update the defect data table in the data storage 10 during a test performed in a factory or during operation. In some embodiments, the control circuit 20 receives a bit address, such as a read address, from an external element, for example, an external controller (not shown). In some embodiments, the memory array 30 is configured to store data; for example, the memory array 30 includes a plurality of memory cells, each memory cell is configured to store one bit of data, wherein the plurality of memory cells are arranged in a matrix, Each memory cell is accessed by a column decoder and a row decoder. In some embodiments, the access circuit 40 is configured to perform a read cycle to read data from the memory array 30. In some embodiments, the access circuit 40 is configured to perform a write cycle to write data to the memory array 30. In some embodiments, the ECC circuit is configured to perform a data correction operation. Many different error correction codes can be applied to data correction operations; for example, Hamming Code can be used. In some embodiments, the scheme used for ECC depends on the complexity of the data, the length of the data, and the time of correction. A more powerful "severe correction" takes longer to process, while a weaker "slight correction" takes less time to process. FIG. 2 is a flowchart illustrating an operation method 200 of the dynamic random access memory shown in FIG. 1. The operation method 200 starts from operation 201 and receives the read address and the defect information of the read address in operation 201; for example, the control circuit 20 receives the read address from an external controller and receives the defect from the data storage 10 Information (defective address). The operation method 200 proceeds to operation 202, where read data is generated from the memory array according to the read address; for example, the access circuit 40 reads data from the memory array 30 according to the read address. Next, the operation method 200 proceeds to operation 203, in which a part of the read data is modified according to the defective address to generate modified data; for example, the modification circuit 50 modifies a part of the read data according to the defective address to generate modified data. FIG. 3 is a functional block diagram illustrating a dynamic random access memory (DRAM) 100B according to some embodiments of the present disclosure; in some embodiments, the modification circuit includes a bit address register 51 and a flip circuit 52. In some embodiments, the address register 51 is configured to store defect information from the control circuit 20; for example, the address register 51 temporarily stores defect information such as a defective address (the position of a defective bit), and This defect address is supplied to the flip circuit 52. In some embodiments, the flip circuit 52 is configured to flip at least one bit of the read data from the access circuit 40. In some embodiments, the flip circuit 52 includes a plurality of controllable inverters 53, wherein each of the inverters 53 is configured to transition logic data from a first logic state to a second logic state; for example, from logic "0" to logic "1" (or from logic "1" to logic "0"), or directly output a logic signal representing a high voltage of a data bit at a defect position. As shown in FIG. 3, in some embodiments, the control circuit 20 receives the read address from an external component, and receives defect information of the read address from the defect data table of the data storage 10. In some embodiments, the control circuit 20 then checks whether the read address includes a defect address according to the defect information in the defect data table. In some embodiments, the defect data table stores defect location information of the defect address in the data storage 10. In some embodiments, the data storage 10 is a non-volatile memory and may be disposed inside or outside the DRAM 100B. In some embodiments, when the read address includes a defective address, the control circuit 20 configures a modification circuit 50 including an address register 51 and a flip circuit 52 according to the defect information. In some embodiments, the defective address (the position of the defective bit) provided by the control circuit 20 is then stored in the address register 51. In some embodiments, the access circuit 40 reads data from the memory array 30 according to the read address provided by the control circuit 20, and the access circuit 40 transmits the read data to the flip circuit 52 of the modification circuit 50. In some embodiments, the flip circuit 52 of the modification circuit 50 receives the read data and flips at least one defective bit according to the defective address stored in the address register 51. In some embodiments, after the flip operation, the flip circuit 52 outputs the modified data to the ECC circuit 60 for further processing to provide the corrected data. In some embodiments, the flip operation of the flip circuit 52 is configured to transition the logic data from a first logic state to a second logic state; for example, from logic "0" to logic "1" (or from logic "1" to logic "0"), or directly output a logic signal indicating a high voltage of a data bit at a defect position. FIG. 4 is a flowchart illustrating an operation method 300 of the DRAM 100B shown in FIG. 3. The operation method 300 starts from operation 301, in which a read address and defect information are received; for example, the control circuit 20 receives a read address from an external controller and defect information (eg, a defect address) from the data storage 10. Subsequently, the operation method 300 proceeds to operation 302, where the read data of the memory array of the DRAM is generated according to the read address; for example, the access circuit 40 generates a read from the memory array 30 of the DRAM 100B according to the read address data. Next, the operation method 300 proceeds to operation 303, where it is determined whether the read address includes a defective address; for example, the control circuit 20 checks whether the read address includes a defective address according to the defect information. If the check result is negative, the operation method 300 proceeds to operation 304, in which the data passed by the check is output. If the check result is positive, the operation method 300 proceeds to operation 305, where the read data is stored in the flip circuit; for example, the read data is stored in the flip circuit 52. Next, the operation method 300 proceeds to operation 306, where the defective address is stored in the address register; for example, the defective address (the position of the defective bit) provided by the control circuit 20 is stored in the address register 51. Subsequently, the operation method 300 proceeds to operation 307, in which a portion of the read data is modified to generate modified data according to the defective address; for example, the flip circuit 52 of the modification circuit 50 modifies the read data by flipping the data located at the defective address The first part to generate modified information. In some embodiments, the flip circuit 52 receives the read data and flips at least one defective bit according to the defective address stored in the address register 51. In some embodiments, after the flip operation, the flip circuit 52 outputs the modified data to the ECC circuit 60 for further data correction. In some embodiments, after the flipped circuit 52 outputs the modified data, the operation method 300 proceeds to operation 308, where a data correction operation is performed on the modified data to modify the second part of the read data; for example, the ECC circuit 60 performs data correction Operate to modify the second part of the read data (ie, bit data stored in addition to the defective bit). 5 is a functional block diagram illustrating a dynamic random access memory (DRAM) 100C according to some embodiments of the present disclosure; in some embodiments, the control circuit 20 described in FIG. 1 is configured to control the access circuit 40 and modified circuit 50. As described above, the control circuit 20 controls the access circuit 40 to read data from the memory array 30 according to the read address, and then the access circuit 40 transmits the read data to the flip circuit 52 of the modification circuit 50. In some embodiments, the flip circuit 52 temporarily stores the read data and outputs the read data to the ECC circuit 60. In some embodiments, the ECC circuit 60 checks for errors. If there is no error, the ECC circuit 60 outputs correct read data; if there is a correctable error, the ECC circuit 60 corrects the error and outputs the corrected read data. In some embodiments, if there is an error that cannot be corrected, the ECC circuit 60 provides a signal to the control circuit 20 for further data correction operations. In some embodiments, the control circuit 20 schedules read operations and correction operations. In some embodiments, the ECC circuit 60 provides defect information (wrong bit information) including the wrong bit address to the address register 51, and the circuit 52 then flips the circuit according to the error bit from the address register 51. Meta information, flipping at least one error bit of the stored data. In some embodiments, after the flip operation, the flip circuit 52 outputs the modified data. In some embodiments, the flip circuit 52 provides the modified data to the ECC circuit 60 to determine whether there are no errors or whether the errors can be corrected; if the check result is positive, the ECC circuit 60 then outputs correct or corrected data; If there is an error that cannot be corrected, the ECC circuit 60 provides the control circuit 20 with a signal for another data correction operation, for example, a second flip operation may be performed to flip an extra error bit. FIG. 6 is a flowchart illustrating an operation method 400 of the DRAM 100C shown in FIG. 5. The operation method 400 starts with operation 401 in which a read address is received; for example, the control circuit 20 receives a read address from an external controller. The operation method 400 proceeds to operation 402, where read data is generated from the memory array according to the read address; for example, the access circuit 40 reads data from the memory array 30 according to the read address. Next, the operation method 400 proceeds to operation 403, where the read data is stored in the flip circuit; for example, the access circuit 40 transmits the read data to the flip circuit 52, and the flip circuit 52 temporarily stores the read data. Next, the operation method 400 proceeds to operation 404, where it is checked whether the read data includes an uncorrectable error; for example, the ECC circuit 60 checks whether the read data includes an uncorrectable error. If the check result is negative, the operation method 400 proceeds to operation 405, in which the data that passed the check is output, and the read data temporarily stored in the flip circuit 52 is discarded. If the check result is positive, the operation method 400 proceeds to operation 406 where a data correction operation is scheduled; for example, the control circuit 20 is guided by the ECC circuit 60 to schedule a read operation and a data correction operation. Subsequently, the operation method 400 proceeds to operation 407, where the defect information is provided to the address register; for example, the ECC circuit 60 provides the defect information, that is, the error bit information to the address register 51. Next, the operation method 400 proceeds to operation 408, in which at least one error bit in the stored data is flipped according to the defect information; for example, the flip circuit 52 flips at least one error bit in the stored data according to the defect information, and then outputs the modified data To ECC circuit 60. Subsequently, the operation method 400 returns to operation 404, where it is checked whether the modified data still contains uncorrectable errors. And if the modified data still contains errors that cannot be corrected, repeat the data correction cycle (for example, steps 406, 407, and 408). Before the data enters the ECC circuit, the disclosure performs data correction through a flip operation, so that the ECC circuit does not need to spend too much time on the data correction operation. Conversely, if the flip operation is not used to correct the data, the ECC circuit needs a longer time to correct the read data. Traditionally, if a data row has one or more defective bits, all data stored in the data row will be marked and replaced with another row. This process requires additional storage space. The disclosure provides a dynamic random access memory (DRAM) including a memory array; a control circuit configured to receive a read address and a defect information of the read address; an access circuit, via Configured to generate a read data from the memory array according to the read address from the control circuit; and a modification circuit connected to the access circuit and the control circuit, wherein the modification circuit is configured to Defect information, modify part of the read data. The disclosure further provides a dynamic random access memory (DRAM), which includes a memory array; a control circuit configured to receive a read address; and an access circuit configured to receive a read address from the control circuit. Taking an address to generate a read data from the memory array; a modification circuit including a bit register connected to the control circuit and a flip circuit connected to the access circuit; and an error correction circuit, A defect information connected to the modification circuit and configured to generate the read data; wherein the address register is connected to the error correction circuit to receive the defect information of the read address, and the flip circuit is configured to According to the defect information, a part of the read data is modified. The disclosure also provides a method for operating a dynamic random access memory (DRAM), which includes: receiving a read address; generating a read data from a memory array according to the read address; and receiving the read data A defect information of; and modifying a part of the read data according to the defect data to generate a modified data. Although the disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and substitutions can be made without departing from the spirit and scope of the disclosure as defined by the scope of the patent application. For example, many of the processes described above can be implemented in different ways, and many of the processes described above can be replaced with other processes or combinations thereof. Moreover, the scope of the present application is not limited to the specific embodiments of the processes, machinery, manufacturing, material compositions, means, methods and steps described in the description. Those skilled in the art can understand from the disclosure of this disclosure that according to this disclosure, they can use existing, or future developmental processes, machinery, manufacturing, materials that have the same functions or achieve substantially the same results as the corresponding embodiments described herein. Composition, means, method, or step. Accordingly, such processes, machinery, manufacturing, material compositions, means, methods, or steps are included in the scope of the patent application of this application.

10‧‧‧Data Storage

20‧‧‧Control circuit

30‧‧‧Memory Array

40‧‧‧Access circuit

50‧‧‧ modify circuit

51‧‧‧Address Register

52‧‧‧ flip circuit

53‧‧‧Inverter

60‧‧‧Error correction code circuit

200‧‧‧operation method

201‧‧‧ Operation

202‧‧‧Operation

203‧‧‧Operation

300‧‧‧Operation method

301‧‧‧operation

302‧‧‧Operation

303‧‧‧operation

304‧‧‧ Operation

305‧‧‧operation

306‧‧‧operation

307‧‧‧operation

308‧‧‧Operation

400‧‧‧operation method

401‧‧‧operation

402‧‧‧operation

403‧‧‧operation

404‧‧‧operation

405‧‧‧operation

406‧‧‧Operation

407‧‧‧ Operation

408‧‧‧operation

100A‧‧‧Dynamic Random Access Memory

100B‧‧‧Dynamic Random Access Memory

100C‧‧‧Dynamic Random Access Memory

When referring to the drawings combined with the embodiments and the scope of the patent application, the disclosure in this application can be understood more fully. The same component symbols in the drawings refer to the same components. FIG. 1 is a functional block diagram illustrating a dynamic random-access memory (DRAM) of some embodiments of the disclosure; FIG. 2 is a flowchart illustrating an operation method of the dynamic random-access memory of FIG. 1 3 is a functional block diagram illustrating a dynamic random access memory of some embodiments of the present disclosure; FIG. 4 is a flowchart illustrating an operation method of the dynamic random access memory of FIG. 3; FIG. 5 is a functional block diagram, An example of a dynamic random access memory of some embodiments of the present disclosure is illustrated. FIG. 6 is a flowchart illustrating an operation method of the dynamic random access memory of FIG. 5.

Claims (19)

A dynamic random access memory (DRAM) includes: a memory array; a control circuit configured to receive a read address and a defect information of the read address; an access circuit configured to Generating a read data from the memory array according to the read address from the control circuit; and a modification circuit connected to the access circuit and the control circuit, wherein the modification circuit is configured to be based on the defect information And modify a part of the read data. The DRAM according to claim 1, wherein the modification circuit includes a flip circuit configured to modify the portion of the read data, and the flip circuit changes at least one bit of the read data from a first bit according to the defect information. A logic state is inverted to a second logic state. The DRAM according to claim 2, wherein the modification circuit further comprises a bit address register configured to store the defect information from the control circuit. The DRAM according to claim 1, further comprising an error correction circuit connected to the modification circuit. The DRAM of claim 4, wherein the modification circuit is configured to modify a first portion of the read data, and the error correction circuit is configured to correct a second portion of the read data that has not been modified by the modification circuit . A dynamic random access memory (DRAM) includes: a memory array; a control circuit configured to receive a read address; and an access circuit configured to respond to the read bit from the control circuit A read data is generated from the memory array; a modification circuit including a bit register connected to the control circuit and a flip circuit connected to the access circuit; and an error correction circuit connected to The modification circuit is configured to generate defect information of the read data; wherein the address register is connected to the error correction circuit to receive the defect information of the read address, and the flip circuit is configured to Defect information and modify part of the read data. The DRAM according to claim 6, wherein the flip circuit is configured to modify the modified portion of the read data, and the flip circuit changes at least one bit of the read data from a first logic state according to the defect information Flip to a second logic state. The DRAM according to claim 6, wherein the error correction circuit is connected to the control circuit, and the error correction circuit is configured to send a signal to the control circuit when the read data includes an uncorrectable error. The DRAM of claim 6, wherein the control circuit is configured to schedule a corrective operation of the modification circuit. A method for operating a dynamic random access memory includes: receiving a read address; generating a read data from a memory array according to the read address; receiving a defect information of the read data; and The defect information modifies a part of the read data to generate a modified data. The operating method according to claim 10, wherein modifying a part of the read data comprises: flipping at least one bit of the read data from a first logic state to a second logic state according to the defect information. The operation method according to claim 10, further comprising: storing the defect information in a bit register, and at least one bit of the read data according to the defect information from the address register. The element flips from a first logic state to a second logic state. The operation method according to claim 10 includes: modifying a first part of the read data, and correcting a second part of the read data. The operation method according to claim 13, wherein a first part of modifying the read data is performed by a modification circuit, and a second part of correcting the read data is performed by an error correction circuit. The operation method according to claim 10 further includes: determining whether the modification data includes an uncorrectable error. The operation method according to claim 15, further comprising: when the modification data includes an uncorrectable error, generating update defect information. The operation method according to claim 16, further comprising: modifying the modification data according to the update defect information. The operation method described in claim 16 further includes: scheduling a subsequent modification operation to modify the modification data including the uncorrectable error. The operation method of claim 10, wherein a defect information generating the read address is executed after an error correction circuit performs an error correction code operation.