JPH10124386A - Portable information terminal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the minimum value of memory loading quantity to a half and to reduce the minimum unit of memory extension to a half by using a CPU capable of switching bus width during the period of operation and a memory of bus width smaller than that of the CPU. SOLUTION: Three memories 2 to 4 having 16-bit bus width are connected to the CPU 1 capable of switching its bus width to 32 bits or 16 bits during the period of its operation. The lower part of a data bus is connected to the memories 2, 4 and the upper part of the data bus is connected to the memory 3. A memory controller 5 is connected to the CPU 1 through an operation control line 9. The memories 2 to 4 are connected to the controller 5 respectively through memory control lines 6 to 8. The controller 5 controls the memory control lines 6 to 8 in accordance with the previously set number of connected memories and operates so as to access memories as many as possible by the maximum bus width of the CPU 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a memory control device used for a portable information terminal such as a pocket computer, an electronic organizer, and a PHS, and a control method thereof.

[0002]

2. Description of the Related Art In a conventional portable information terminal, a CPU is used.
And the same data bus width was used.
For example, a 32-bit CPU uses a plurality of 32-bit memories or 16-bit memories.

[0003]

The conventional portable information terminal uses the same bus width for the CPU and the memory.
At least two 2M byte memory must be mounted for a 32 bit CPU. Therefore, the minimum memory capacity is 4 Mbytes, and there is a problem that the memory is increased by 8, 12, and 16 Mbytes in units of 4 Mbytes.

[0004] Here, the portable information terminal is usually driven by a battery to be used while moving, so that the amount of installed memory must be minimized in order to suppress power consumption. Furthermore, it is necessary to minimize the size of the fuselage in order to emphasize portability, and in order to reduce the area of semiconductor mounting,
There is a problem that the amount of mounted memory must be minimized.

[0005]

In a portable information terminal according to the present invention, a CP capable of switching a bus width during operation is provided.
U and a memory having a bus width smaller than the number of bus widths of the CPU are used. Then, the minimum value of the amount of installed memory can be reduced to half the conventional value, and the minimum unit of memory expansion can be reduced to half the conventional value.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The portable information terminal according to the present invention has a first bit width and a second bit width which is half of the first bit width. One or a plurality of memories having the second bit width are connected to a CPU that can be switched to a bit width of one. As a result, a memory having a small bit width, which can be conventionally mounted only in an even number unit, can be mounted in an odd number unit, and the memory can be controlled with the maximum bus width of the CPU according to the number of connected memories. 2N + 1 memories of the second bit width can be accessed with the first bit width.

[0007]

Embodiments will be described with reference to the drawings.
In FIG. 1, three 16-bit bus width memories 2, 3, and 4 are connected to a CPU 1 that can be switched between a 32-bit bus width and a 16-bit bus width during operation. Here, memory 2 and memory 4
Is connected to the lower part of the data bus, and the memory 3 is connected to the upper part of the data bus. Further, a memory controller 5 is connected to the CPU 1 via an operation control line 9. The memories 2, 3, and 4 are connected to a memory controller 5 via memory control lines 6, 7, and 8, respectively.

Here, the memory controller 5 controls the memory control line according to the preset number of connected memories by the operation control control line 9 so that as many memories as possible can be accessed with the maximum bus width of the CPU 1. Works.

That is, the memories 2 and 3 are controlled so as to be accessed with a 32-bit width, and the memories 4 and 16 are accessed in 16 bits.
Control to access in bit width. As another embodiment, one memory is connected and accessed with a 16-bit width. Two memories can be connected and accessed with a 32-bit width.

[0010]

The present invention is embodied in a portable device as described above, and has the following effects. An odd number of memories having a smaller bus width than the CPU bus width can be connected. • One memory with a smaller bus width than the CPU bus width
Can be connected. The memory expansion unit can be reduced to one half of the conventional one.・ The area occupied by the memory can be reduced, and the size of the portable information terminal can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of the present invention.

[Explanation of symbols]

 1 CPU 2, 3, 4 memory 5 memory controller 6, 7, 8 memory control line 9 operation control line

Claims (7)

[Claims] A first bus having a first bus width and a second bus width which is a half of the first bus width;
A CPU (1) capable of switching the bus width of a first memory (2) having a second bus width connected to a lower part of a data bus of the CPU (1); A second memory (3) having the second bus width connected to the upper part of the data bus; and a third memory having the second bus width connected to the lower part of the data bus of the CPU (1). A memory (4), the CPU (1), the first memory (2), and the second memory
A portable information terminal having a memory (3) and a memory controller (5) connected to the third memory (4). 2. The method according to claim 1, wherein the first bus width is half of the first bus width and the second bus width is half of the first bus width.
A portable information terminal, comprising: a CPU (1) capable of switching a bus width of the above; and a memory having the second bus width connected to the CPU (1). 3. The method of claim 1, wherein the first bus width and the second bus width are half of the first bus width.
A portable information terminal comprising: a CPU (1) capable of switching a bus width of the CPU; and a memory having the second bus width to which a lower part of a data bus of the CPU (1) is connected. 4. The method according to claim 1, wherein the first bus width is half of the first bus width and the second bus width is half of the first bus width.
A CPU having a second bus width connected to a lower part of a data bus of the CPU; a CPU having a second bus width connected between the CPU and the memory; Portable information terminal having a memory controller (5). 5. A bus having a first bus width and a second bus width which is half of said first bus width, said first bus width and said second bus width being in operation.
A CPU (1) capable of switching the bus width of the CPU, an odd number of memories connected to the CPU (1) and having the second bus width, and a memory controller connected to the CPU (1) and the memory A portable information terminal having 5). 6. A bus having a first bus width and a second bus width which is half of said first bus width, said first bus width and said second bus width being in operation.
And 2N + 1 memories connected to the CPU (1) and having a second bus width, wherein N is a natural number greater than or equal to 0, and wherein the 2N memories are connected to the CPU (1). A memory control method for a portable information terminal that operates on a first bus width. 7. A CPU capable of switching a bus width during operation
(1) A portable information terminal comprising a plurality of memories having a bus width smaller than a data bus width of the CPU (1), wherein the number of the plurality of memories is variable.