JP2007532001A - Method for forming sidewall spacer - Google Patents

Abstract

In accordance with the present invention, sidewall spacers (217, 218) adjacent to features (206) on the substrate (201) can be formed. The feature (206) is covered by one or more protective layers (220, 207). A spacer material layer (211) is deposited on the feature (206) and anisotropically etched. The etchant used for anisotropic etching is suitable for selectively removing the spacer material, while one or more protective layers (220, 207) are substantially unaffected by this etchant. . As a result, the one or more layers (220, 207) protect the features from exposure to the etchant.

Description

  The present invention relates to the field of manufacturing semiconductor devices, and more particularly to the field of forming sidewall spacers.

  Integrated circuits include a large number of individual circuit elements such as transistors, capacitors, resistors, and the like. These elements are connected internally to form composite circuits such as memory devices, logic devices, and microprocessors. In order to improve the performance of the integrated circuit, it is necessary to reduce the processing dimension. In addition to improving the operation speed by shortening the signal propagation time, reducing the processing dimension can increase the number of functional elements of the circuit in order to expand the functionality of the circuit.

  FIG. 1c shows a schematic cross-sectional view of a field effect transistor 100 according to the state of the art. The substrate 101 includes an active region 102. Shallow trench isolations 103 and 104 insulate the active region 102 from adjacent circuit elements. A gate electrode 106 having side surfaces 114 and 115 and an upper surface 116 is formed on the substrate 101, and the gate electrode 106 is insulated from the substrate 101 by the gate insulating layer 105. A protective layer 108 is formed on the surface of the substrate 101 and on the side surfaces 114 and 115 of the gate electrode 106. Sidewall spacers 117 and 118 are disposed on the side surfaces of the gate electrode 106.

  Further, the field effect transistor 100 includes an extended source region 109, an extended drain region 110, a source region 112, and a drain region 113. A part of the extended source region 109 described as “source extension” and a part of the extended drain region 110 described as “drain extension” extend under the sidewall spacers 117 and 118, Each extension is adjacent to the gate electrode 106.

  A method of forming the field effect transistor 100 will be described with reference to FIGS. FIG. 1a shows a schematic cross-sectional view of a field effect transistor 100 in a first stage of the manufacturing process.

  First, trench isolations 103 and 104 and an active region 102 are formed in the substrate 101. Next, the gate insulating layer 105 and the gate electrode 116 are formed over the substrate 102. The upper surface 116 of the gate electrode 106 is covered with the covering layer 107. These structures can be formed using state-of-the-art ion implantation, vapor deposition, oxidation, and photolithography techniques.

  Specifically, the gate electrode 106 is formed by patterning a gate electrode material layer such as polysilicon on the substrate 101 and the gate insulating layer 105 using a known photolithography and etching technique. Photolithography, a technique well known to those skilled in the art, deposits a photoresist layer (not shown) on the substrate 101 and exposes the photoresist layer. An anti-reflective coating layer 107 may be formed on the gate electrode material layer to avoid adverse effects resulting from interference due to incident light and light reflected from the gate electrode material layer. The thickness of the cover layer 107 can be such that light reflected from the surface of the cover layer 107 interferes with light reflected from the contact surface between the cover layer 107 and the surface of the gate electrode material layer in a destructive manner. As a result, the reflectivity of the material layer and the covering layer 107 is substantially reduced. After a photoresist layer is patterned using a well-known photolithography technique to form a mask, an etching process is performed on the exposed portion of the gate electrode material layer and the covering layer 107 to form the gate electrode 106.

  After the formation of the gate electrode 106 covered with the covering layer 107, a protective layer 108 is formed on the substrate and the side surfaces 114 and 115 of the gate electrode 106. This treatment can be performed by thermally oxidizing part of the gate electrode and part of the substrate 101. During the thermal oxidation, since the upper surface 116 of the gate electrode 106 is covered with the covering layer 107, the protective layer 108 does not expand on the upper surface 106. Next, the covering layer 107 is etched.

  FIG. 1b shows the late stage of the manufacturing process. The extended source region 109 and the extended drain region are formed by implanting dopant material ions into the substrate 101 adjacent to the gate electrode 106. Each portion of the substrate 101 outside the undoped field effect transistor 100 is covered with a photoresist layer (not shown) that blocks and absorbs ions.

  After ion implantation, sidewall spacers 117 and 118 are formed. A spacer material layer 111 is conformally, that is, uniformly deposited on the substrate 101 by, for example, chemical vapor deposition (CVD). In uniform deposition, the local thickness of the deposited layer does not depend on the local slope of the surface to be deposited. Specifically, the layer 111 has substantially the same thickness on the surface of the substrate 101 and the horizontal surface such as the upper surface 116 of the gate electrode 106 and the thickness on the vertical surface such as the side surfaces 114 and 115 of the gate electrode 106. .

  The spacer material layer 111 is anisotropically etched. In anisotropic etching, the vertical etching rate is faster than the horizontal etching rate. Accordingly, each portion of the spacer material layer 111 whose surface is substantially horizontal, for example, the layer 111 on the upper surface 116 of the gate electrode 106 or each portion of the surface of the substrate 101 is removed faster than the inclined portion of the layer 111. Can do. Specifically, each portion of the layer 111 whose surface is substantially horizontal is each portion of the layer whose surface is substantially vertical, for example, each of the layers 111 on each side 114 and 115 of the gate electrode 106. Can be removed faster than part.

  When the portions of the layer having a horizontal surface are removed, the etching of the spacer material layer 111 is stopped. Since the removal rate of each portion of the layer 111 having a vertical surface is slow, the residue of these portions remains on the substrate, forming sidewall spacers 117 and 118 adjacent to the gate electrode 106.

  After the sidewall spacers 117 and 118 are formed, ions of a dopant material are implanted to form the source region 112 and the drain region 113. A schematic cross-sectional view of the field effect transistor after forming the source region 112 and the drain region 113 is shown in FIG.

  Finally, an annealing step may be performed to activate the dopants in the active region 102, extended source region 109, extended drain region 110, source region 112, and drain region 113.

  A problem with the conventional method of forming a field effect transistor is that the gate electrode 106 is exposed to an etching solution when the spacer material layer 111 is etched. This is because the upper surface of the gate electrode 106 in FIG. As schematically shown by the jagged portion, the gate electrode 106 is eroded. Since the shape of the gate electrode 106 changes without being controlled, the gate electrode 106 may be eroded, which may adversely affect the formation stability of the field effect transistor 100.

  In view of this problem, there is a need for a technique capable of manufacturing a field effect transistor that reduces erosion of the gate electrode while forming the sidewall spacer.

  The following provides an overview of the present invention in order to provide a basic understanding of some aspects of the present invention. This summary is not an extensive overview of the invention. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. The purpose here is to provide some concepts of the invention in a simplified form as a prelude to the more detailed description that follows.

  According to an exemplary embodiment of the present invention, a method for forming sidewall spacers includes forming features on a substrate. This feature has a side surface and a top surface. The upper surface is covered with the first protective layer and the covering layer. A second protective layer is formed on the side surface and the substrate. The covering layer is removed. The spacer material layer is uniformly deposited on the side, top, and substrate. The spacer material layer is anisotropically etched.

  According to another exemplary embodiment of the present invention, a method of forming sidewall spacers includes forming features on a substrate. This feature has a side surface and a top surface. The upper surface is covered with a coating layer. A first protective layer is formed on the side surface and the substrate. The covering layer is removed. A second protective layer is formed on the side surface, the top surface, and the substrate. The spacer material layer is uniformly deposited on the side, top, and substrate. The spacer material layer is anisotropically etched.

  The present invention may be understood by reference to the following description taken in conjunction with the accompanying drawings. In the drawings, the same elements are denoted by the same reference numerals.

  While the invention is susceptible to various modifications, and may be practiced in other forms, the specific embodiments described herein are for purposes of illustration and are described in detail below. . It should be understood, however, that the particular embodiments shown are not intended to limit the invention to the particular form disclosed, but rather to fall within the scope of the invention as defined by the appended claims. Covers all improvements, equivalents, and variations to which it belongs.

  Examples of the invention are described below. For simplicity, not all features in the actual implementation are described in this specification. Of course, in the development of such real-world implementations, many specific implementation decisions, such as reconciliation with system and business limitations, are made to achieve specific goals for developers. The They vary depending on each embodiment. Moreover, such development efforts are naturally complex and time consuming, but nevertheless fall within the normal work for those skilled in the art having the benefit of this disclosure.

  The present invention will be described with reference to the accompanying drawings. Various structures of semiconductor devices have very precise and sharp shapes and profiles and are depicted in each drawing, but those skilled in the art will be able to see these regions and structures as accurately as they are actually shown in the drawings. You will recognize that it is not. In addition, the various features depicted in the drawings and the relative size of the doped regions are exaggerated and reduced compared to the features and region sizes of the devices being manufactured. However, the attached drawings are attached for the purpose of explaining and explaining embodiments of the present invention. Terms and phrases used herein should be understood and interpreted to have a meaning consistent with words and phrases understood by those skilled in the relevant art. The consistent use of terms or phrases in this specification means definitions that are different from any particular definition of these terms or phrases, that is, from the ordinary and conventional meanings understood by those of ordinary skill in the art. Not what you want. When a term or phrase is used in a range that has a specific meaning, that is, when used in a different meaning than that understood by those skilled in the art, the specification directly and clearly identifies such words and phrases. Define.

  The present invention allows the manufacture of field effect transistors in the formation of sidewall spacers without substantial erosion of the gate electrode, or at least significantly reducing erosion of the gate electrode. To accomplish this goal, one or more protective layers are formed on both the side and top surfaces of features on the substrate, such as gate electrodes. A spacer material layer is uniformly deposited on the side, top, and substrate. Subsequently, the spacer material layer is anisotropically etched to form sidewall spacers adjacent to the features. In this etching process, one or more protective layers prevent or reduce feature erosion.

  A further exemplary embodiment of the present invention will be described with reference to FIGS. 2a-2d. FIG. 2a shows a schematic cross-sectional view of a field effect transistor in the first stage of the manufacturing process. In the substrate 201, an active region 202 and trench isolations 203 and 204 are formed. Next, a gate insulating layer 205 is formed over the substrate 201. Subsequently, a material layer 219 is deposited on the substrate 201 and the gate insulating layer 205. The material layer 219 can be deposited using a deposition technique such as physical vapor deposition, chemical vapor deposition, and / or plasma enhanced chemical vapor deposition.

  In physical vapor deposition, material is transported from the source to the vapor deposition surface through physical processes such as gas flow and diffusion. Here, there is virtually no chemical modification of the material. The deposition surface may be, for example, the surface of the gate insulating layer 205 or the surface of the layer 219. At the source, the material can be thermally evaporated, producing a vapor of the material. This deposition surface is exposed to steam. The vapor liquefies on the deposition surface, which causes layer 219 to grow. In other forms, sputtering can be applied by physical vapor deposition. A target made from this material is implanted using ions extracted from the plasma. Thereby, atoms are released from the target, and then such atoms are deposited on the deposition surface.

  In chemical vapor deposition, the vapor deposition material is formed as a result of a chemical reaction between gaseous reactants generated on or near the vapor deposition surface. The solid material produced from the reaction is deposited on the deposition surface.

  The plasma enhanced chemical vapor deposition method is a kind of chemical vapor deposition method, and the chemical reaction is generated by plasma that can be generated by glow discharge, for example. Plasma enhanced chemical vapor deposition is advantageous in that materials can be deposited at lower temperatures than conventional chemical vapor deposition.

  In particular embodiments of the present invention, the material of the substrate 201 comprises crystalline silicon, the gate insulating layer 205 comprises silicon dioxide, and the material of the layer 219 comprises polycrystalline silicon. In this embodiment, the layer 219 can be deposited by chemical vapor deposition or a low pressure chemical vapor deposition process, and the reaction gas contains silane (SiH 4).

  After the deposition of the layer 219, a first protective layer 220 is formed on the layer 219. In one embodiment, in forming the first protective layer 220, a portion of the layer 219 can be thermally oxidized. In thermal oxidation, layer 219 is exposed to an oxidizing environment such as oxygen or water at high temperatures. As a result, a chemical reaction occurs between the material of layer 219 and the oxidizing environment, thereby forming an oxide of the material. The thickness of the first protective layer can take a value in the range of about 0.6-5 nm.

  Thermal oxidation may be performed by fast thermal oxidation. In rapid thermal oxidation, the field effect transistor 200 is heated to a high temperature for a short time while exposed to an oxidizing environment. This process can be performed, for example, by irradiating the field effect transistor 200 with radiation from a plurality of lamps.

  In another embodiment, thermal oxidation may be performed by heating the field effect transistor 200 in a furnace while being exposed to an oxidizing environment. The temperature during thermal oxidation in the furnace is lower than the temperature during rapid thermal oxidation. The duration of thermal oxidation in the furnace may be longer than the duration of fast thermal oxidation.

  In the thermal oxidation, a portion close to the surface of the layer 219 is oxidized. As a result, an oxide of the material of layer 219 is formed, which forms the first protective layer 220. Accordingly, the first protective layer 220 is grown at the expense of the layer 219. This material loss of layer 219 can be taken into account by adapting the thickness of layer 219 accordingly. As higher temperatures are applied in the thermal oxidation process, oxidation occurs faster. Accordingly, the thickness of the first protective layer 220 can be controlled by controlling the duration of thermal oxidation and the applied temperature. The longer the duration and the higher the applied temperature, the thicker the first protective layer 220 is.

  Rapid thermal annealing can be performed after the thermal oxidation. In rapid thermal annealing, field effect transistors are heated to high temperatures when there is no oxidizing environment. The temperature applied for rapid thermal annealing may be higher than the temperature applied for thermal oxidation. In the annealing, thermally activated atoms may be rearranged in the first protective layer 220 such that the density of the first protective layer 220 is increased. This has the advantage that the stability of the first protective layer against etching is improved.

  In other embodiments of the present invention, the formation of the first protective layer may include physical vapor deposition, chemical vapor deposition, and / or plasma enhanced chemical vapor deposition. These processes can be followed by rapid thermal annealing to increase the density of the first protective layer 220.

The first protective layer 220 can include an oxide of the material of the layer 219. In embodiments of the invention where the material of layer 219 includes polycrystalline silicon, the material of layer 220 may include silicon dioxide (SiO ₂ ).

  After the formation of the first protective layer 220, a coating layer 207 is deposited on the first protective layer. The coating layer 207 may be deposited by, for example, physical vapor deposition, chemical vapor deposition, or plasma enhanced chemical vapor deposition. The cover layer 207 can include silicon nitride or silicon oxynitride, and the thickness of the cover layer 207 can be about 10-60 nm. Next, the gate insulating layer 205, the layer 219, the first protective layer 220, and the covering layer 207 are patterned. This patterning can be realized by a known lithography or etching process.

  The cover layer 207 may be configured such that adverse effects resulting from interference due to incident light and reflected light from the layer 219 and the first protective layer 220 are substantially avoided in photolithography patterning. For this purpose, the thickness of the coating layer 207 is such that the reflected light from the surface of the coating layer is reflected from the interface between the coating layer 207 and the first protective layer 220 and / or from the interface between the first protective layer 220 and the layer 219. Adapted to interfere destructively with the transmitted light. As a result, the reflectivity of the layer 210 and the first protective layer 220 is effectively reduced.

  In other embodiments of the present invention, interference due to incident and reflected light can be substantially avoided by forming a cover layer 207 made of a material that absorbs incident light that penetrates the photoresist used in photolithography. . This helps to avoid reflection of light by the layer 219 and the first protective layer 220. A combination of forming the cover layer 207 made of a material that absorbs incident light and adapting the thickness of the cover layer 207 so that destructive interference occurs between the incident light and the reflected light. Also good.

  A schematic cross-sectional view of a field effect transistor 200 at a later stage of the manufacturing process is shown in FIG. 2b. In patterning the gate insulating layer 205, the layer 219, the first protective layer 220, and the covering layer 207, a gate electrode 206 is formed on the substrate 201 and the gate insulating layer 205. The gate electrode 206 includes an upper surface 216, and the upper surface is covered with the first protective layer 220 and the covering layer 207. Further, the gate electrode 206 includes side surfaces 214 and 215.

  After the formation of the gate electrode 206, the second protective layer 208 is formed on the substrate 201 and the side surfaces 214 and 215 of the gate electrode 206. In forming the second protective layer 208, the portion of the gate electrode proximate to the side surfaces 214 and 215 and the portion of the substrate 201 proximate to the surface of the substrate 201 can be thermally oxidized. Similar to the thermal oxidation used in the formation of the first protective layer 220 according to one embodiment, the thermal oxidation used to form the second protective layer 208 is performed by fast thermal oxidation or by performing thermal oxidation in a furnace. Followed by rapid thermal annealing.

  In thermal oxidation, the second protective layer 208 is grown at the expense of portions of the gate electrode 206 adjacent to the side surfaces 214 and 215 and the portion of the substrate 201 proximate to the surface of the substrate 201. The loss of the material of these portions can be taken into consideration in advance by adjusting in advance according to the length of the gate electrode 206 and the depth of the active region 202.

  Layer 208 includes an oxide of the material of layer 219 and an oxide of the material of substrate 201. In one embodiment of the invention that includes crystalline silicon as the material of the substrate 201 and polycrystalline silicon as the material of the gate electrode 206, the layer 208 includes silicon dioxide.

  After the formation of the second protective layer 208, the protective layer 207 is removed. In removing the cover layer 207, the cover layer 207 is exposed to an etching solution suitable for selectively removing the material of the cover layer 207. On the other hand, the material of the first protective layer 220 and the material of the second protective layer 208 are not substantially affected by the etching solution. As a result, the first and second protective layers are protected when the covering layer 207 is removed, and protect the gate electrode 206 and the substrate 201 from the influence of the etching solution.

  The step of exposing the covering layer 207 to the etching solution may include wet etching. In a wet etch, the coating layer can be exposed to hot phosphoric acid. In embodiments of the present invention where the coating layer 207 includes silicon nitride, in particular, a step of exposing the coating layer 207 to high temperature phosphoric acid can be used to selectively remove the coating layer 207.

  FIG. 2c shows the field effect transistor 200 in a further stage of the manufacturing process. After removing the covering layer 207, the extended source region 209 and the extended drain region 210 are formed on the substrate 201 adjacent to the gate electrode 206. This treatment can be performed by implanting dopant material ions into the substrate 201. Each portion of the undoped substrate 201 may be covered with a photoresist layer (not shown) that absorbs ions.

  In other embodiments of the present invention, the extended source region 209 and the extended drain region 210 are formed before removing the cover layer 207. Accordingly, in the ion implantation, the covering layer 207 has an advantage of absorbing ions directed to the field effect transistor 200 and, as a result, radiation of energy ions to the gate electrode 206 and the gate insulating layer 205 can be avoided.

  In a further embodiment of the present invention, the extended source region 209 and the extended drain region 210 may be formed before the second protective layer 208 is formed.

  A space material layer 211 is uniformly deposited on the substrate 201, the upper surface 216 and the side surfaces 214 and 215. By this uniform vapor deposition, the thickness of each portion of the upper surface 216, the side surfaces 214 and 215, and the layer 211 on the substrate 201 is substantially equal. The spacer material layer 211 can be uniformly deposited by physical vapor deposition, chemical vapor deposition, or plasma enhanced vapor deposition. In one exemplary embodiment, the spacer material can include silicon nitride.

  A schematic cross-sectional view of the field effect transistor 200 after completion of the manufacturing process is shown in FIG. After the deposition of the spacer material layer 211, this layer is anisotropically etched. The etchant used for anisotropic etching can selectively remove the spacer material, while the first protective layer and the second protective layer are substantially unaffected by the etchant.

  The anisotropic etching of the spacer material layer 211 may include dry etching. Due to the anisotropy of the etching process, each portion of the substantially horizontal spacer material layer 211, such as a portion on the top surface 216 and a portion on the surface of the substrate 201, substantially each portion on the side surfaces 214 and 215. It is removed faster than each part of the spacer material layer 211 perpendicular to. As a result, sidewall spacers 217 and 218 similar to the sidewall spacers 117 and 118 of the field effect transistor 100 are formed adjacent to the gate electrode according to the state of the art.

  Since the first protective layer 220 and the second protective layer 208 are substantially unaffected by the etchant, each protective layer protects the substrate 201 and the gate electrode 206 from being exposed to the etchant. As a result, erosion of the gate electrode 206 is advantageously avoided or reduced.

  After the formation of the sidewall spacers 217 and 218, a source region 212 and a drain region 213 are formed in the substrate 201 by implanting dopant material ions into the substrate 201. In the ion implantation, the sidewall spacer 217 absorbs ions so that the source region 212 is separated from the gate electrode 206. Since the sidewall spacer 218 absorbs ions, the drain region 213 is also separated from the gate electrode 206.

  Finally, an annealing step may be performed to activate the dopant in the active region 202, source region 212, extended source region 209, drain region 213, and extended drain region 210.

  A further embodiment of the present invention will be described with reference to FIGS. 3a-3c. FIG. 3a shows a field effect transistor 300 in the first stage of the manufacturing process according to an embodiment of the invention. In the substrate 301, an active region 302 and trench isolations 303 and 304 are formed. These features can be formed using state-of-the-art ion implantation, vapor deposition, oxidation, and photolithography techniques.

  A gate electrode 306 having side surfaces 314 and 315 and an upper surface 316 and having an upper surface covered with a coating layer 307 is formed over the gate insulating layer 305 and the substrate 301. This gate electrode can be formed as follows. First, a gate insulating layer 305 is deposited on the substrate 301. Next, a gate electrode material layer similar to the layer 219 shown in FIG. 2 a is deposited on the gate insulating layer 305 and the substrate 301. A coating layer 307 is deposited on the gate electrode material layer. Subsequently, the gate insulating layer 305, the gate electrode material layer, and the covering layer 307 are patterned to form the gate electrode 306. This process can be performed by performing lithography and etching techniques. Similar to the cover layer 207 of the embodiments of the present invention described with reference to FIGS. 2a-2d, the cover layer 307 is configured to substantially avoid adverse effects resulting from interference from incident and reflected light in the lithography process. obtain.

  The material of the substrate 301 can include silicon. The gate insulating layer 305 can include silicon dioxide. The material layer may include polycrystalline silicon, and the material of the covering layer 307 may include silicon nitride.

  A first protective layer 320 is formed on the side surfaces 314 and 315 of the gate electrode 306 and the substrate 301. Similar to the first protective layer 220 and the second protective layer 208 of the embodiment of the present invention described with reference to FIGS. 2a to 2d, the gate electrode 306 adjacent to the side surfaces 314 and 315 is formed in the formation of the first protective layer 320. Each portion and the portion of the substrate 301 proximate to the surface of the substrate 301 can be thermally oxidized. This thermal oxidation may be performed in a furnace or by rapid thermal oxidation, followed by rapid thermal annealing.

  In one exemplary embodiment, the material of the first protective layer 320 may include an oxide of the material of the gate electrode 306 and an oxide of the material of the substrate 301. In one embodiment of the invention in which the gate electrode 306 includes polycrystalline silicon and the substrate 301 material includes crystalline silicon, the first protective layer 320 may include silicon dioxide.

  Subsequently, the covering layer 307 is removed. This treatment can be removed by exposure to an etchant suitable for selectively removing the material of the coating layer 307 coating layer 307. On the other hand, the material of the first protective layer is not substantially affected by the etching solution.

  Similar to the removal of the cover layer 207 in the embodiment of the present invention described with reference to FIGS. 2a-2d, the removal of the cover layer 307 may include a wet etch, in which the cover layer 307 may be exposed to phosphoric acid. . Wet etching is advantageous in that it can provide a high degree of selectivity to the material of the coating layer 307. As a result, the gate electrode is substantially not damaged or only slightly damaged.

  After removing the covering layer 307, the first protective layer 320 may be removed. This treatment can be performed by exposing the first protective layer 320 to an etching solution suitable for selectively removing the material of the first protective layer 320. On the other hand, the material of the gate electrode 306 and the material of the substrate 301 are not substantially affected by the etching solution.

  The first protective layer 320 can be removed by wet etching. In an embodiment of the invention in which the first protective layer 320 includes silicon dioxide, this treatment can be performed by immersing the first field effect transistor 300 in an aqueous solution of hydrofluoric acid (HF). Wet etching is particularly advantageous in that it allows for a high degree of selectivity of the etching process, so that the gate electrode is substantially free of damage or the gate electrode is only slightly damaged.

  FIG. 3b shows the field effect transistor 300 in a later stage of the manufacturing process. A second protective layer 308 is formed on the side surfaces 314 and 315 of the gate electrode 306, the upper surface 316 of the gate electrode 306, and the surface of the substrate 301. This treatment can be performed by thermal oxidation or by physical vapor deposition, chemical vapor deposition, and / or plasma enhanced chemical vapor deposition. Following the formation of the second protective layer, rapid thermal annealing may be performed to increase the density of the second protective layer 308. Silicon dioxide can be included as a material for the second protective layer.

  In other embodiments of the present invention, the first protective layer 320 is not removed prior to the formation of the second protective layer 308. Instead, the first protective layer 320 may remain on the surface of the gate electrode 306 and the substrate 301 and may be covered by the second protective layer 308 or may be incorporated into the second protective layer 308. This is advantageous in that the manufacturing cost of the field effect transistor 300 can be reduced because the process of exposing the first protective layer 320 to the etching solution can be omitted.

  An extended source region 309 and an extended drain region 310 are formed in the substrate 301 adjacent to the gate electrode 306. This treatment can be performed by implanting dopant material ions into the substrate 301. Each portion of the substrate 301 outside the undoped field effect transistor 300 may be covered by a photoresist layer (not shown) that absorbs ions.

  In other embodiments of the present invention, the extended source region 309 and the extended drain region 310 are formed before the first protective layer 320 is formed, the first protective layer 320 is removed, or the second protective layer 308 is formed. Can be done.

  Similar to the embodiment of the invention described with reference to FIGS. 2 a-2 c, the spacer material layer 311 is uniformly deposited on the side surfaces 314 and 315 of the gate electrode 316, the top surface 316 of the gate electrode 306, and the substrate 301. . The spacer material layer 311 is anisotropically etched to form sidewall spacers 317 and 318 as shown in FIG. 3c.

  In anisotropic etching of the spacer material layer 311, the spacer material layer 311 can be exposed to an etchant suitable for selectively removing the spacer material. On the other hand, this etching solution does not substantially affect the material of the second protective layer 308. Accordingly, the second protective layer 308 protects the gate electrode 306 and the substrate 301 from exposure to the etchant, resulting in the advantage of avoiding or reducing undesirable erosion of the gate electrode 306 and the substrate 301.

  After the formation of the sidewall spacers 317 and 318, the source region 312 and the drain region 313 are formed on the substrate 301. This treatment can be performed by implanting dopant material ions into the substrate. Since the sidewall spacers 317 and 318 absorb ions, the source region 312 and the drain region 313 are separated from the gate electrode 306.

  Finally, an annealing step is performed and the field effect transistor is performed by performing an annealing step to activate the dopants in the active region 302, the source region 312, the drain region 313, the extended source region 309, and the extended drain region 310. 300 can be completed.

  The present invention is not limited to the formation of field effect transistors. Instead, the present invention is typically applicable to the formation of sidewall spacers adjacent to features on the substrate. For example, the present invention can be applied to the formation of conductive wiring.

  It will be apparent to those skilled in the art who are able to benefit from the present invention that various modifications and implementations are possible within the equivalent scope of the present invention, so that the individual embodiments described above are exemplary. It's just a thing. For example, the execution order of each step in the above-described method can be changed. Further, the details of the configuration or the design described above are not intended to limit the present invention at all, and are limited only to the description of the claims. Thus, it will be apparent that the particular embodiments described above can be varied and modified and such variations are within the spirit and scope of the invention. Accordingly, the protection of the present invention is limited only by the scope of the claims.

1 is a schematic cross-sectional view of a field effect transistor in a manufacturing process stage according to the prior art. 1 is a schematic cross-sectional view of a field effect transistor in a manufacturing process stage according to the prior art. 1 is a schematic cross-sectional view of a field effect transistor in a manufacturing process stage according to the prior art. 1 is a schematic cross-sectional view of a field effect transistor in a manufacturing process stage according to an embodiment of the present invention. 1 is a schematic cross-sectional view of a field effect transistor in a manufacturing process stage according to an embodiment of the present invention. 1 is a schematic cross-sectional view of a field effect transistor in a manufacturing process stage according to an embodiment of the present invention. 1 is a schematic cross-sectional view of a field effect transistor in a manufacturing process stage according to an embodiment of the present invention. FIG. 6 is a schematic cross-sectional view of a field effect transistor in a manufacturing process stage according to another embodiment of the present invention. FIG. 6 is a schematic cross-sectional view of a field effect transistor in a manufacturing process stage according to another embodiment of the invention. FIG. 6 is a schematic cross-sectional view of a field effect transistor in a manufacturing process stage according to another embodiment of the invention.

Claims (15)

Forming a feature including a side surface and an upper surface on the substrate, the upper surface covered with a first protective layer and a covering layer formed on the first protective layer;
Forming a second protective layer on the side surface and the substrate;
Removing the covering layer;
Uniformly depositing a spacer material layer on the substrate, the side surface and the top surface;
Etching the spacer material layer uniformly.
Method for forming sidewall spacer. The step of forming the feature includes:
Depositing a material layer on the substrate;
Forming the first protective layer on the material layer;
Depositing the coating layer on the first protective layer; and
Patterning the material layer, the first protective layer, and the covering layer;
The method of claim 1 comprising:   The method of claim 2, wherein the material layer comprises polycrystalline silicon.   The method of claim 2, wherein forming the first protective layer includes performing a thermal oxidation process on a portion of the material layer.   The method of claim 1, wherein the feature is a gate electrode.   The method of claim 1, wherein at least one of the first protective layer and the second protective layer comprises silicon dioxide.   The method of claim 1, wherein the covering layer comprises silicon nitride.   The method of claim 1, wherein forming the second protective layer includes performing a thermal oxidation process on a portion of the feature and a portion of the substrate. Forming a feature on the substrate including a side surface and a top surface covered by a covering layer;
Forming a first protective layer on the side surface and the substrate;
Removing the covering layer;
Forming a second protective layer on the side surface, the top surface, and the substrate;
Uniformly depositing a spacer material layer on the side surface, the top surface, and the substrate; and
Anisotropically etching the spacer material layer;
A method for forming a sidewall spacer including: Forming the feature comprises:
Depositing a material layer on the substrate;
Depositing the coating layer on the material layer; and
Patterning the material layer and the covering layer,
The method of claim 9.   The method of claim 10, wherein the material comprises polycrystalline silicon.   The method of claim 9, further comprising removing the first protective layer, wherein the first protective layer is removed after removal of the covering layer.   The method of claim 9, wherein the feature comprises a gate electrode.   The method of claim 9, wherein forming the first protective layer includes performing a thermal oxidation process on a portion of the feature and a portion of the substrate.   The method of claim 9, wherein forming the second protective layer includes performing a thermal oxidation process on a portion of the feature and a portion of the substrate.

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