JP2007528593A - High performance and stress enhanced MOSFETs using Si: C and SiGe epitaxially grown sources / drains and fabrication methods - Google Patents

High performance and stress enhanced MOSFETs using Si: C and SiGe epitaxially grown sources / drains and fabrication methods Download PDF

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JP2007528593A
JP2007528593A JP2006536715A JP2006536715A JP2007528593A JP 2007528593 A JP2007528593 A JP 2007528593A JP 2006536715 A JP2006536715 A JP 2006536715A JP 2006536715 A JP2006536715 A JP 2006536715A JP 2007528593 A JP2007528593 A JP 2007528593A
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チダムバーラオ、ドゥレセティ
ドクマシ、オマー
チェン、フアジ
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Abstract

【課題】 半導体デバイスおよび半導体デバイスの製造方法を提供する。
【解決手段】 半導体デバイスはｐＦＥＴおよびｎＦＥＴのためのチャネルを含む。ＳｉＧｅ層はｐＦＥＴチャネルのソースおよびドレイン領域に選択的に成長され、Ｓｉ：Ｃ層はｎＦＥＴチャネルのソースおよびドレイン領域に選択的に成長される。ＳｉＧｅ層およびＳｉ：Ｃ層は、下に位置するＳｉ層の格子ネットワークに一致して応力成分を生成する。１つの実施形態では、これによって、ｐＦＥＴチャネルでは圧縮成分が引き起こされ、ｎＦＥＴでは引張成分が引き起こされる。
【選択図】 図５
PROBLEM TO BE SOLVED: To provide a semiconductor device and a method for manufacturing the semiconductor device.
A semiconductor device includes channels for pFETs and nFETs. A SiGe layer is selectively grown in the source and drain regions of the pFET channel, and a Si: C layer is selectively grown in the source and drain regions of the nFET channel. The SiGe layer and the Si: C layer generate stress components in accordance with the lattice network of the underlying Si layer. In one embodiment, this causes a compressive component in the pFET channel and a tensile component in the nFET.
[Selection] Figure 5

Description

本発明は、一般に半導体デバイスおよび製造方法に関し、より詳細には半導体デバイスおよびデバイス製造中に引張および圧縮応力を課する製造方法に関する。   The present invention relates generally to semiconductor devices and manufacturing methods, and more particularly to semiconductor devices and manufacturing methods that impose tensile and compressive stresses during device manufacturing.

半導体デバイス基板内の機械的応力は、デバイス性能を変化させることができる。すなわち、半導体デバイス内の応力は、半導体デバイス特性を向上させることが知られている。したがって、半導体デバイスの特性を改善するために、引張または圧縮応力あるいはその両方は、ｎ型デバイス（例えば、ＮＦＥＴ）またはｐ型デバイス（例えば、ＰＦＥＴ）あるいはその両方のチャネル内で生成される。しかし、同じ応力成分、引張応力または圧縮応力は、差別的にｎ型デバイスおよびｐ型デバイスの特性に影響する。   Mechanical stress in the semiconductor device substrate can change device performance. That is, it is known that stress in a semiconductor device improves semiconductor device characteristics. Thus, to improve the characteristics of the semiconductor device, tensile and / or compressive stresses are generated in the channel of the n-type device (eg, NFET) and / or the p-type device (eg, PFET). However, the same stress component, tensile stress or compressive stress differentially affects the characteristics of n-type and p-type devices.

例えば、シリコン基板の上に緩和した（relaxed）別のエピタキシャル成長されたＳｉＧｅ層上でエピタキシャル成長されたシリコン層（またはキャップ）上に形成された時、デバイスがより良好な性能特性を示すことが知られている。この系では、シリコン・キャップ（cap）は２軸引張ひずみに直面する。シリコン上にエピタキシャル成長される場合、非緩和ＳｉＧｅ層は、シリコン基板に一致する格子定数を有する。ＳｉＧｅ格子定数は、緩和（例えば、高温プロセスを介して）に基づいてシリコンより大きい固有の格子定数に近づく。完全に緩和したＳｉＧｅ層は、その固有の値に近い格子定数を有する。シリコン層がその上にエピタキシャル成長される場合、シリコン層は、緩和したＳｉＧｅ層のより大きな格子定数に一致し、これは、その上に形成されたシリコン層に物理的な２軸応力（例えば、膨張）を加える。膨張したシリコン層はＮ型デバイスの性能を増大し、ＳｉＧｅ層中のより高いＧｅ濃度がｐ型デバイス性能を向上するので、シリコン層に加えられたこの物理的応力は、その上に形成されたデバイス（例えば、ＣＭＯＳデバイス）に有益である。   For example, devices are known to exhibit better performance characteristics when formed on a silicon layer (or cap) epitaxially grown on another epitaxially grown SiGe layer relaxed on a silicon substrate. ing. In this system, the silicon cap faces a biaxial tensile strain. When epitaxially grown on silicon, the unrelaxed SiGe layer has a lattice constant that matches the silicon substrate. The SiGe lattice constant approaches an intrinsic lattice constant larger than that of silicon based on relaxation (eg, via a high temperature process). A fully relaxed SiGe layer has a lattice constant close to its intrinsic value. When a silicon layer is epitaxially grown thereon, the silicon layer matches the larger lattice constant of the relaxed SiGe layer, which is a physical biaxial stress (eg, expansion) on the silicon layer formed thereon. ). This physical stress applied to the silicon layer was formed on it because the expanded silicon layer increased the performance of the N-type device and the higher Ge concentration in the SiGe layer improved the p-type device performance. Useful for devices (eg, CMOS devices).

シリコン基板上のＳｉＧｅ中の緩和は、不整合転位（misfit dislocation）の形成によって生じる。完全に緩和した基板について、応力を取り除く等間隔の不整合転位の格子（grid）を想像することができる。不整合転位は基板中のシリコンの余分な半平面を提供することにより、ＳｉＧｅ層中の格子定数がその固有値を求めのを促進する。次いで、ＳｉＧｅ／シリコン界面の全体にわたって不整合ひずみがもたらされ、ＳｉＧｅ格子定数はより大きくなることが可能となる。
Ｅｒｎｓｔら、ＶＬＳＩ Ｓｙｍｐ．（２００２年）ｐ．９２ Relaxation in SiGe on a silicon substrate is caused by the formation of misfit dislocations. For a fully relaxed substrate, an equidistant misfit dislocation grid can be imagined that removes stress. Misfit dislocations provide an extra half-plane of silicon in the substrate, facilitating the lattice constant in the SiGe layer to determine its eigenvalue. Then, mismatch strain is introduced across the SiGe / silicon interface, allowing the SiGe lattice constant to be larger.
Ernst et al., VLSI Symp. (2002) p. 92

しかし、この従来のアプローチに関する問題は、ＳｉＧｅ層とシリコン基板層との間の貫通転位（threading dislocation）を避けながら、その表面部分上の不整合転位を達成するために非常に厚い（例えば、約５０００Å〜１５０００Åの厚さ）多層ＳｉＧｅ緩衝層を必要とし、それによって多層ＳｉＧｅ層の表面上に緩和ＳｉＧｅ構造を達成することである。また、このアプローチは、製造時間およびコストを著しく増加させる。さらに、厚い段階的（graded）なＳｉＧｅ緩衝層は、シリコン・オン・インシュレータ（ＳＯＩ）基板に適用するのが容易ではない。これは、シリコン・オン・インシュレータについて、有効なＳＯＩのためにシリコンの厚さが１５００Å以下である必要があるからである。ＳｉＧｅ緩衝層の構造は厚すぎる。   However, the problems with this conventional approach are very thick (e.g., approximately about to achieve misfit dislocations on its surface portion while avoiding threading dislocation between the SiGe layer and the silicon substrate layer). Is required to have a multilayer SiGe buffer layer, thereby achieving a relaxed SiGe structure on the surface of the multilayer SiGe layer. This approach also significantly increases manufacturing time and cost. Furthermore, a thick graded SiGe buffer layer is not easy to apply to a silicon-on-insulator (SOI) substrate. This is because for silicon-on-insulators, the silicon thickness needs to be less than 1500 mm for effective SOI. The structure of the SiGe buffer layer is too thick.

別の問題は、ＳｉＧｅ層とシリコン・エピタキシャル層との間に形成された不整合転位が、ふぞろい（ランダム）で、非常に不均一であり、制御するのが困難な異種核生成（heterogeneous nucleation）により容易にコントロールすることができないということである。また、不整合転位密度は、ある場所と別の場所とでは著しく異なる。このように、不均一の不整合転位に由来する物理的応力は、シリコン・エピタキシャル層で非常に不均一になる傾向があり、この不均一な応力は、より大きな変動性で、性能のための利点が不均一となる。さらに、不整合密度が高い位置では、短絡デバイス端子、および他の重要な漏れ機構（leakage mechanism）を介して欠陥がデバイスの性能を下げる。   Another problem is that the misfit dislocations formed between the SiGe layer and the silicon epitaxial layer are random, very heterogeneous and difficult to control heterogeneous nucleation. It cannot be controlled more easily. Also, the misfit dislocation density is significantly different from one place to another. Thus, the physical stresses resulting from non-uniform misfit dislocations tend to be very non-uniform in the silicon epitaxial layer, and this non-uniform stress has greater variability and is The benefits are non-uniform. In addition, at locations with high mismatch density, defects can degrade device performance through shorted device terminals and other important leakage mechanisms.

また、本質的に引張りであるＳｉ上にＳｉ：Ｃをエピタキシャル成長することが知られている。Ｓｉ：Ｃ／Ｓｉ材料スタック中の１％のＣ含有量は、５００ＭＰａで、Ｓｉ：Ｃ中に引張応力レベルを引き起こす場合がある。これに対して、ＳｉＧｅ／Ｓｉ系では、約６％のＧｅは、５００ＭＰａの圧縮を引き起こす必要がある。この１％のＣのレベルは、ＥｒｎｓｔらのＶＬＳＩ Ｓｙｍｐ（２００２年）、９２頁で示されるように、エピタキシャル成長中にＳｉに組み込むことができる。Ｅｒｎｓｔらでは、ｎＦＥＴのためのＳｉ／Ｓｉ：Ｃ／Ｓｉ階層状チャネルが示される。しかし、Ｅｒｎｓｔらの構造では、Ｓｉ：Ｃは、チャネル内のスタック層として、従来のひずみＳｉアプローチで提供されている。このように、Ｅｒｎｓｔらの構造では、Ｓｉ：Ｃは、チャネルそれ自体の一部として使用される。このアプローチに関する問題は移動度（mobility）が向上されずに、散乱（scattering）からＣ含有量に依存して抑制されることである。   It is also known to epitaxially grow Si: C on Si that is essentially tensile. The 1% C content in the Si: C / Si material stack is 500 MPa and can cause tensile stress levels in Si: C. In contrast, in the SiGe / Si system, about 6% Ge needs to cause a compression of 500 MPa. This 1% C level can be incorporated into Si during epitaxial growth, as shown in Ernst et al., VLSI Symp (2002), page 92. Ernst et al. Show Si / Si: C / Si hierarchical channels for nFETs. However, in the structure of Ernst et al., Si: C is provided with a conventional strained Si approach as a stack layer in the channel. Thus, in the Ernst et al. Structure, Si: C is used as part of the channel itself. The problem with this approach is that the mobility is not improved and is suppressed from scattering depending on the C content.

本発明の第１の態様では、半導体構造を製造する方法は、基板中にｐ型電界効果トランジスタ（ｐＦＥＴ）チャネルおよびｎ型電界効果トランジスタ（ｎＦＥＴ）チャネルを形成するステップを含む。ｐＦＥＴスタックおよびｎＦＥＴスタックは、それぞれのチャネルに関連して基板上に形成される。第１の材料層はｐＦＥＴスタックに隣接して（about）ソース／ドレイン領域に準備される。第１の材料層は基板の基礎（base）格子定数と異なる格子定数を有し、ｐＦＥＴチャネル内で圧縮状態を生成する。第２の材料層はｎＦＥＴスタックに隣接してしてソース／ドレイン領域に準備される。第２の材料層は基板の基礎格子定数と異なる格子定数を有し、ｎＦＥＴチャネルで引張状態を生成する。   In a first aspect of the invention, a method of manufacturing a semiconductor structure includes forming a p-type field effect transistor (pFET) channel and an n-type field effect transistor (nFET) channel in a substrate. A pFET stack and an nFET stack are formed on the substrate in association with each channel. A first material layer is provided in the source / drain region about the pFET stack. The first material layer has a lattice constant that is different from the base lattice constant of the substrate and creates a compressed state in the pFET channel. A second material layer is provided in the source / drain regions adjacent to the nFET stack. The second material layer has a lattice constant that is different from the basic lattice constant of the substrate and creates a tensile state in the nFET channel.

本発明の他の態様では、基板内にｐ型電界効果トランジスタ（ｐＦＥＴ）チャネルおよびｎ型電界効果トランジスタ（ｎＦＥＴ）チャネルを形成するステップを含む半導体構造を製造する方法が提供される。ｐＦＥＴ構造およびｎＦＥＴ構造はｐＦＥＴチャネルおよびｎＦＥＴチャネルに隣接する基板上にそれぞれ形成される。ｐＦＥＴ構造およびｎＦＥＴ構造の領域は、所定深さにエッチングされる。基板（層）の基礎格子定数と異なる格子定数を有する第１の材料はｐＦＥＴ構造のエッチング領域に準備され、ｐＦＥＴチャネル内に圧縮応力を付与する。基板（層）の基礎格子定数と異なる格子定数を有する第２の材料はｎＦＥＴ構造のエッチングされた領域に準備され、ｎＦＥＴチャネル内に引張応力を付与する。ｎＦＥＴおよびｐＦＥＴ構造のドーピングされたソースおよびドレイン領域が準備される。   In another aspect of the present invention, a method of manufacturing a semiconductor structure is provided that includes forming a p-type field effect transistor (pFET) channel and an n-type field effect transistor (nFET) channel in a substrate. A pFET structure and an nFET structure are formed on the substrate adjacent to the pFET channel and the nFET channel, respectively. The regions of the pFET structure and the nFET structure are etched to a predetermined depth. A first material having a lattice constant different from the basic lattice constant of the substrate (layer) is provided in the etched region of the pFET structure and applies compressive stress in the pFET channel. A second material having a lattice constant different from the basic lattice constant of the substrate (layer) is provided in the etched region of the nFET structure and imparts tensile stress in the nFET channel. Doped source and drain regions of nFET and pFET structures are prepared.

また、本発明の他の態様では、半導体構造は半導体基板を含み、ｐＦＥＴおよびｎＦＥＴは基板内のそれぞれのチャネルに形成される。ｐＦＥＴチャネルのソースおよびドレイン領域の第１の材料層は基板の格子定数と異なる格子定数を有する。ｎＦＥＴチャネルのソースおよびドレイン領域の第２の材料層は基板の格子定数と異なる格子定数を有する。   In another aspect of the invention, the semiconductor structure includes a semiconductor substrate, and the pFET and nFET are formed in respective channels in the substrate. The first material layer in the source and drain regions of the pFET channel has a lattice constant different from that of the substrate. The second material layer in the source and drain regions of the nFET channel has a lattice constant that is different from the lattice constant of the substrate.

本発明は、半導体デバイス、およびＣＭＯＳデバイスのｎＦＥＴチャネル付近に引張応力およびｐＦＥＴチャネル付近に圧縮応力を付与する製造方法に関する。本発明の一実施形態では、縦引張応力はｎＦＥＴチャネルに非常に接近してもたらされ、同時に、圧縮応力はｐＦＥＴチャネルに非常に接近してもたらされる。さらに、本発明では、ＳｉＧｅおよびＳｉ：Ｃ材料の両方をＣＭＯＳ技術に統合するため、方法および構造が提供される。   The present invention relates to a semiconductor device and a manufacturing method for applying a tensile stress near an nFET channel and a compressive stress near a pFET channel in a CMOS device. In one embodiment of the invention, the longitudinal tensile stress is brought very close to the nFET channel, while the compressive stress is brought very close to the pFET channel. Furthermore, the present invention provides methods and structures for integrating both SiGe and Si: C materials into CMOS technology.

一例として、高引張りのＳｉ：Ｃ膜がソース／ドレイン（Ｓ／Ｄ）領域でシリコン基板内に準備されて（例えば、埋め込まれる）、ゲート領域下のチャネル内の、ｎＦＥＴ構造上に縦方向に引張りを加える。同様に、高圧縮のＳｉＧｅ膜はＳ／Ｄ領域のシリコン基板内に準備されて（例えば、埋め込まれる）、ゲート領域下のチャネル内のｐＦＥＴ上に縦に圧縮を加える。ＳｉＧｅ層に類似して、Ｓｉ：Ｃ層は比較的薄く（その臨界厚さ以下）、緩和されていない。ｎＦＥＴのトランジスタ・チャネル領域はＳｉ：Ｃ層からの応力によってひずみ、一方、ｐＦＥＴのチャネル領域はＳｉＧｅからの圧縮応力を付与される。   As an example, a high tensile Si: C film is prepared (eg, embedded) in the silicon substrate in the source / drain (S / D) region and vertically on the nFET structure in the channel under the gate region. Apply tension. Similarly, a highly compressed SiGe film is prepared (eg, embedded) in the silicon substrate in the S / D region and vertically compressed on the pFET in the channel under the gate region. Similar to the SiGe layer, the Si: C layer is relatively thin (below its critical thickness) and is not relaxed. The nFET transistor channel region is strained by stress from the Si: C layer, while the pFET channel region is subjected to compressive stress from SiGe.

ＳｉＧｅ層がｐＦＥＴのＳ／Ｄ領域に埋め込まれているので、まだ低抵抗のシリサイド（silicide）を形成することができる。興味深いことに、埋め込まれた（例えば、サブ表面または共面（コプラナー）表面）Ｓｉ：Ｃ膜は膜表面が自由でないので、上記表面Ｓｉ：Ｃ対応物（counterpart）より大きな応力を加えることができる。本発明では、Ｓｉ：Ｃの異なる厚みおよび突出部（protrusion）は埋め込まれるか、表面と共面（同一平面）か、または隆起されるかどうかが検討される。ＳｉＧｅ層内のＧｅ含有量の濃度を調節することによってｐＦＥＴチャネルでの圧縮応力を調節することができることが理解される。同様に、Ｓｉ：Ｃ層内のＣ濃度を調節することにより、ｎＦＥＴチャネルの引張応力を調節することができる。これは、そのような材料の格子定数による。   Since the SiGe layer is embedded in the S / D region of the pFET, a low resistance silicide can still be formed. Interestingly, since embedded (eg, sub-surface or coplanar surface) Si: C films are not free on the film surface, they can be more stressed than the surface Si: C counterpart. . The present invention contemplates whether different Si: C thicknesses and protrusion are embedded, coplanar (coplanar) with the surface, or raised. It is understood that the compressive stress in the pFET channel can be adjusted by adjusting the concentration of Ge content in the SiGe layer. Similarly, the tensile stress of the nFET channel can be adjusted by adjusting the C concentration in the Si: C layer. This is due to the lattice constant of such materials.

本発明では、Ｓｉ：Ｃは、正確な応力を有し、正確なＣ含有量を含み、エピタキシャルにおよび選択的に成長させることができることを示す。また、本発明では、Ｓｉ：Ｃはチャネル下に直接形成された積層としてではなく、張力が働き、それによってチャネル領域に張力をかけるｎＦＥＴ Ｓ／Ｄ領域のための置換材料として使用される。したがって、このＳｉ：Ｃ膜は、ＳｉＧｅがｐＦＥＴチャネルに圧縮応力を加える一方、ｎＦＥＴチャネルに引張応力を加える。   The present invention shows that Si: C has the correct stress, contains the correct C content, and can be grown epitaxially and selectively. Also, in the present invention, Si: C is not used as a stack formed directly under the channel, but as a replacement material for the nFET S / D region where tension acts and thereby tensions the channel region. Thus, this Si: C film applies compressive stress to the pFET channel while SiGe applies tensile stress to the nFET channel.

図１〜図５は、本発明によるデバイスを形成するための製造プロセスを表わす。図１では、シリコン・オン・インシュレータ（ＳＯＩ）２０またはその種の他のものが準備される。層２０は、浅いトレンチ分離（ＳＴＩ：shallow trench isolation）の構造体（ＳＴＩ）２５を形成するために、例えば、パッド酸化、パッド窒化物堆積、リソグラフィーに基づくパターニング、窒化物、酸化物および埋込酸化物にいたるシリコンからなるスタック（積層）の反応性イオンエッチング（ＲＩＥ）、エッジ酸化、ライナー（liner）堆積、充填（fill）堆積および化学機械的研磨の標準的技法を使用して、パターン化される。ＳＴＩ形成プロセスは、本技術分野において公知である。次いで、パッド窒化物を取り除く。例えば、ゲート誘電体およびポリシリコンを含むゲートスタックを任意の公知の方法で基板上に形成して、ｐＦＥＴおよびｎＦＥＴを形成する。ＴＥＯＳキャップ４３、４４は、公知の方法によりｐＰＥＴおよびｎＦＥＴで形成される。   1-5 represent a manufacturing process for forming a device according to the present invention. In FIG. 1, a silicon-on-insulator (SOI) 20 or the like is provided. Layer 20 may be formed, for example, by pad oxidation, pad nitride deposition, lithographic patterning, nitride, oxide and buried to form a shallow trench isolation (STI) structure (STI) 25. Pattern stacks of silicon to oxide using standard techniques of reactive ion etching (RIE), edge oxidation, liner deposition, fill deposition and chemical mechanical polishing Is done. STI formation processes are known in the art. The pad nitride is then removed. For example, a gate stack including a gate dielectric and polysilicon is formed on the substrate by any known method to form pFETs and nFETs. The TEOS caps 43 and 44 are formed of pPET and nFET by a known method.

また、図１を参照すると、スペーサは任意の公知のプロセスを使用して、それぞれｐＦＥＴおよびｎＦＥＴスタック上に形成される。一例として、スペーサ３８はｐＦＥＴスタック４０ａの側壁上に形成され、スペーサ４２はｎＦＥＴスタック４５ａの側壁上で形成される。スペーサは、例えば、酸化物または窒化物のスペーサであってもよい。   Referring also to FIG. 1, the spacers are formed on the pFET and nFET stacks, respectively, using any known process. As an example, spacer 38 is formed on the sidewall of pFET stack 40a and spacer 42 is formed on the sidewall of nFET stack 45a. The spacer may be, for example, an oxide or nitride spacer.

図２で、薄いライナー５０は、例えば、ｐＦＥＴスタック、ｎＦＥＴスタックおよびＳ／Ｄ領域を含む構造を覆って堆積されるブランケット（blanket）である。一実施形態では、薄いライナー５０は、Ｓｉ３Ｎ４ライナーまたはハード・マスクの材料に依存する窒化物または酸化物系材料のいずれかである。薄いライナーの厚みはおよそ５〜２０ｎｍである。薄いライナー５０は保護層の役割をしてもよい。ハード・マスク５１は、次いで、ｎＦＥＴスタック４５ａおよびＳ／Ｄ領域を覆って形成される。 In FIG. 2, the thin liner 50 is a blanket that is deposited over a structure including, for example, a pFET stack, an nFET stack, and an S / D region. In one embodiment, the thin liner 50 is either a Si 3 N 4 liner or a nitride or oxide based material depending on the material of the hard mask. The thickness of the thin liner is approximately 5-20 nm. The thin liner 50 may serve as a protective layer. A hard mask 51 is then formed over the nFET stack 45a and the S / D region.

ｐＦＥＴスタック４０ａに関する領域はライナー５０にエッチングされる。次いで、ライナー５０がエッチングされ、Ｓ／Ｄ領域５２がスタック４０ａに隣接して形成（エッチング）される。Ｓ／Ｄ領域５２の深さは、ＳＯＩ層の厚さに依存し約２０〜１００ｎｍである。高圧縮の選択的エピタキシャルＳｉＧｅ層６０は、図３で示されるように、ｐＦＥＴスタック４０ａの領域５２内において成長され、Ｓ／Ｄエッチング領域５２を完全に充填する。ＳｉＧｅ層６０は約１０〜１００ｎｍの厚みに成長されてもよく、他の厚みも本発明によって検討される。１つの実施形態では、ＳｉＧｅ層はゲート酸化物の表面上にある厚さに成長される。ライナーのハード・マスクおよび残りの部分は、例えば、ウェット化学薬品などの公知のプロセスを使用して取り除かれる。処理ステップにおいて、ハード・マスクを除去する前に、ドーパントがイオン注入され、ｐＦＥＴスタック４０ａに隣接するＳ／Ｄ領域を形成する。   The area for the pFET stack 40a is etched into the liner 50. The liner 50 is then etched, and the S / D region 52 is formed (etched) adjacent to the stack 40a. The depth of the S / D region 52 is approximately 20 to 100 nm depending on the thickness of the SOI layer. A highly compressed selective epitaxial SiGe layer 60 is grown in the region 52 of the pFET stack 40a, as shown in FIG. 3, to completely fill the S / D etched region 52. The SiGe layer 60 may be grown to a thickness of about 10-100 nm, and other thicknesses are contemplated by the present invention. In one embodiment, the SiGe layer is grown to a thickness on the surface of the gate oxide. The liner hard mask and the remainder are removed using known processes such as, for example, wet chemicals. In the processing step, before removing the hard mask, dopant is ion implanted to form the S / D region adjacent to the pFET stack 40a.

ＳｉＧｅは単独で、通常ＳＯＩより大きな格子定数を有する。すなわち、ＳｉＧｅ材料の格子定数はＳｉの格子定数と一致しない。しかし、本発明の構造では、ＳｉＧｅ層の成長によりＳｉＧｅ層の格子構造は下に位置するＳｉの格子構造と一致する傾向がある。これによって、ＳｉＧｅ層およびＳｉＧｅに隣接するチャネル領域が圧縮下となる。一実施形態では、ＳｉＧｅ層のＧｅ含有量はＳｉ含有量に対して０％より多い高い比率であってもよい。   SiGe alone has a larger lattice constant than normal SOI. That is, the lattice constant of the SiGe material does not match the lattice constant of Si. However, in the structure of the present invention, the lattice structure of the SiGe layer tends to coincide with the underlying lattice structure of Si due to the growth of the SiGe layer. As a result, the SiGe layer and the channel region adjacent to the SiGe are under compression. In one embodiment, the Ge content of the SiGe layer may be a high ratio greater than 0% with respect to the Si content.

図４では、本発明の処理を参照して、例えば、薄いライナー５０は、再度ｎＦＥＴ、ｐＦＥＴおよびＳ／Ｄ領域を含む構造を覆って堆積されるブランケットである。薄いライナー５０は、一実施形態において、Ｓｉ３Ｎ４ライナー、またはハード・マスクの材料に依存する窒化物または酸化物材料のいずれかである。薄いライナーの厚みの範囲はおよそ５〜２０ｎｍである。薄いライナー５０は、保護層の役割をしてもよい。 In FIG. 4, referring to the process of the present invention, for example, the thin liner 50 is a blanket that is again deposited over the structure including the nFET, pFET, and S / D regions. The thin liner 50 is in one embodiment either a Si 3 N 4 liner or a nitride or oxide material depending on the hard mask material. The thickness range of the thin liner is approximately 5-20 nm. The thin liner 50 may serve as a protective layer.

次いで、マスク５１はｐＦＥＴスタック４０ａを覆って形成され、ｎＦＥＴスタック４５ａに隣接する領域はライナー５０までエッチングされる。次いで、ライナーはエッチングされ、Ｓ／Ｄ領域５４は、前記スタック４５ａに隣接して形成（エッチング）される。Ｓ／Ｄ領域５４の深さはＳＯＩ層の厚さに依存して約２０〜１００ｎｍである。任意の公知のプロセスが領域５４をエッチングするために使用されてもよい。   A mask 51 is then formed over the pFET stack 40a and the area adjacent to the nFET stack 45a is etched down to the liner 50. The liner is then etched and the S / D region 54 is formed (etched) adjacent to the stack 45a. The depth of the S / D region 54 is about 20 to 100 nm depending on the thickness of the SOI layer. Any known process may be used to etch region 54.

高引張りの選択的エピタキシャルＳｉ：Ｃ層は、図５に示されるように、ｎＦＥＴスタック４５ａの領域５４において約１０〜１００ｎｍの厚さに成長される。Ｓｉ：Ｃ層６２は、本発明によって検討されるように、他の厚さにエピタキシャル成長されてもよいことが理解される。一実施形態では、Ｃ含有量は、Ｓｉ含有量に対する比率で０％を超え４％までであってもよい。薄いライナーのレジストおよび残りの部分は、任意の公知のプロセスの使用、例えば、ウェット化学薬品を使用することにより取り除かれる。   A high tensile selective epitaxial Si: C layer is grown to a thickness of about 10-100 nm in region 54 of nFET stack 45a, as shown in FIG. It will be appreciated that the Si: C layer 62 may be epitaxially grown to other thicknesses as contemplated by the present invention. In one embodiment, the C content may be greater than 0% and up to 4% in proportion to the Si content. The thin liner resist and remaining portions are removed by use of any known process, eg, using wet chemicals.

Ｓｉ：Ｃは単独で、通常下に位置するＳｉより小さな格子定数を有する。すなわち、Ｓｉ：Ｃ材料の格子定数はＳｉの格子定数と一致しない。しかし、本発明の構造では、ｎＦＥＴスタック４５ａのＳ／Ｄ領域内のＳｉ：Ｃ層の成長によって、Ｓｉ：Ｃ層の格子構造は下に位置するＳｉの格子構造と一致する傾向がある。これによって、Ｓｉ：Ｃ層およびＳｉ：Ｃに隣接するチャネル領域が引張応力下となる。   Si: C alone has a smaller lattice constant than Si, which is usually located below. That is, the lattice constant of the Si: C material does not match the lattice constant of Si. However, in the structure of the present invention, due to the growth of the Si: C layer in the S / D region of the nFET stack 45a, the lattice structure of the Si: C layer tends to match the underlying lattice structure of Si. This places the Si: C layer and the channel region adjacent to Si: C under tensile stress.

一実施形態では、Ｓｉ：Ｃ層またはＳｉＧｅ層もしくはその両方は、そのような層に陥凹部を形成するためにプロセスを最適化して、例えばＲＩＥ、ウェットエッチングまたは他のプロセスまたはそれらの組み合わせを行なうことにより、デバイス（基板）内に埋め込まれてもよい。次いで、Ｓｉは、任意の公知のプロセスを使用して領域５２、５４を覆って選択的に成長される。次いで、ソース及びドレインの注入は、任意の公知のプロセスを使用しても行うことができる。デバイスおよび相互接続（interconnect）を構築するためにさらなる処理を行なうことができる。   In one embodiment, the Si: C layer or SiGe layer or both optimize the process to form a recess in such a layer, eg, perform RIE, wet etching or other processes or combinations thereof Thus, it may be embedded in the device (substrate). Si is then selectively grown over regions 52, 54 using any known process. The source and drain implants can then be performed using any known process. Further processing can be performed to build the device and interconnect.

理解されるように、Ｓｉ：ＣおよびＳｉＧｅ層の両方は、デバイス内に埋め込まれてもよく、または共面（同一平面）とすることができ、またはデバイスから隆起させることができる。一実施形態では、Ｓｉ：ＣおよびＳｉＧｅ膜は、１０〜１００ｎｍの厚みに堆積され、ＭＯＳＦＥＴに応力（圧縮または引張）を加えるためによりコスト的に有効な方法をもたらす。隆起された実施の形態では、Ｓｉ：ＣおよびＳｉＧｅ層は約５０ｎｍまでデバイスの表面上に隆起されてもよい。他の厚みも本発明によって検討されることが認識される。   As will be appreciated, both the Si: C and SiGe layers may be embedded within the device, or may be coplanar (coplanar) or raised from the device. In one embodiment, Si: C and SiGe films are deposited to a thickness of 10-100 nm, resulting in a more cost effective way to apply stress (compression or tension) to the MOSFET. In raised embodiments, Si: C and SiGe layers may be raised on the surface of the device to about 50 nm. It will be appreciated that other thicknesses are contemplated by the present invention.

また、Ｐ型ドーピングでＳｉＧｅを、ｎ型ドーピングでＳｉ：Ｃを、そのままドーピングし、ｐＦＥＴおよびｎＦＥＴの所望のソースおよびドレイン領域をそれぞれ形成することも可能である。   It is also possible to form SiGe with P-type doping and Si: C with n-type doping as they are to form desired source and drain regions of pFET and nFET, respectively.

図２および３に示すプロセス工程に先立って、図４および５のプロセス工程が同等に行われても良いことは当業者によって理解される。またさらに、例えば、標準のイオン注入などのプロセス工程を行ってｐＦＥＴおよびｎＦＥＴのＳ／Ｄ領域を形成することができる。イオン注入を通して、このプロセス中にマスクの役割をするｎＦＥＴおよびｐＦＥＴ領域内のゲート酸化物によってＳ／Ｄ領域の形成は自己整合される。   It will be appreciated by those skilled in the art that prior to the process steps shown in FIGS. 2 and 3, the process steps of FIGS. 4 and 5 may be performed equally. Still further, for example, process steps such as standard ion implantation can be performed to form pFET and nFET S / D regions. Through ion implantation, the formation of the S / D region is self-aligned by the gate oxide in the nFET and pFET regions that act as a mask during this process.

図６は、本発明によるｐＦＥＴデバイス中の応力の位置を示す。図６に示すように、圧縮応力は、非緩和ＳｉＧｅの領域を備えたｐＦＥＴの真下に存在する。より詳細には、本発明の構造ではＳｉＧｅ層の格子構造は下に位置するＳｉ絶縁層の格子構造と一致する。これにより、ＳｉＧｅ層および周辺領域が圧縮応力下となる。   FIG. 6 shows the location of stress in a pFET device according to the present invention. As shown in FIG. 6, the compressive stress exists directly under the pFET with the unrelaxed SiGe region. More specifically, in the structure of the present invention, the lattice structure of the SiGe layer coincides with the lattice structure of the underlying Si insulating layer. Thereby, the SiGe layer and the peripheral region are under compressive stress.

図７は、本発明によるｎＦＥＴデバイス中の応力の位置を示す。図７に示されるように、引張応力はｎＦＥＴのチャネル内に存在する。より詳細には、本発明の構造で、Ｓｉ：Ｃ層の格子構造は下に位置するＳｉ絶縁層２０の格子構造と一致し、ｎＦＥＴチャネル中で引張応力成分を形成する。   FIG. 7 shows the location of stress in an nFET device according to the present invention. As shown in FIG. 7, tensile stress is present in the channel of the nFET. More specifically, in the structure of the present invention, the lattice structure of the Si: C layer coincides with the lattice structure of the underlying Si insulating layer 20 and forms a tensile stress component in the nFET channel.

本発明は、実施の形態に関して記述されているが、当業者は、本発明を変形させ、請求項の精神および範囲内で実行することができることがわかるだろう。例えば、本発明は、容易にバルク基板に適用することができる。   While the invention has been described in terms of embodiments, those skilled in the art will recognize that the invention can be modified and practiced within the spirit and scope of the claims. For example, the present invention can be easily applied to a bulk substrate.

本発明によるデバイスを形成するための製造プロセスを示す図である。FIG. 5 shows a manufacturing process for forming a device according to the invention. 本発明によるデバイスを形成するための製造プロセスを示す図である。FIG. 5 shows a manufacturing process for forming a device according to the invention. 本発明によるデバイスを形成するための製造プロセスを示す図である。FIG. 5 shows a manufacturing process for forming a device according to the invention. 本発明によるデバイスを形成するための製造プロセスを示す図である。FIG. 5 shows a manufacturing process for forming a device according to the invention. 本発明によるデバイスを形成するための製造プロセスを示す図である。FIG. 5 shows a manufacturing process for forming a device according to the invention. 本発明によるｐＦＥＴデバイスでの応力の位置を示す図である。FIG. 4 shows the position of stress in a pFET device according to the present invention. 本発明によるｎＦＥＴデバイスでの応力の位置を示す図である。FIG. 4 is a diagram showing the position of stress in an nFET device according to the present invention.

Claims (21)

ｐ型電界効果トランジスタ（ｐＦＥＴ）チャネルおよびｎ型電界効果トランジスタ（ｎＦＥＴ）チャネルを基板内に形成するステップと、
前記ｐＦＥＴチャネルにｐＦＥＴスタックを、前記ｎＦＥＴチャネルにｎＦＥＴスタックを形成するステップと、
前記ｐＦＥＴスタックに関連するソース／ドレイン領域に、前記基板の基礎格子定数と異なる格子定数を有する第１の材料層を準備して、前記ｐＦＥＴチャネル内で圧縮状態を生成するステップと、
前記ｎＦＥＴスタックに関連するソース／ドレイン領域に、前記基板の基礎格子定数と異なる格子定数を有する第２の材料層を準備して、前記ｎＦＥＴチャネルで、引張状態を生成するステップとを含む、半導体構造の製造方法。 forming a p-type field effect transistor (pFET) channel and an n-type field effect transistor (nFET) channel in the substrate;
Forming a pFET stack in the pFET channel and an nFET stack in the nFET channel;
Providing a first material layer having a lattice constant different from a basic lattice constant of the substrate in a source / drain region associated with the pFET stack to generate a compressed state in the pFET channel;
Providing a second material layer having a lattice constant different from a base lattice constant of the substrate in a source / drain region associated with the nFET stack to generate a tensile state in the nFET channel. Structure manufacturing method. 前記第１の材料層は、Ｓｉに対する比率で約０％を超えるＧｅの含有量を有するＳｉＧｅである請求項１に記載の方法。 The method of claim 1, wherein the first material layer is SiGe having a Ge content greater than about 0% as a percentage of Si. 前記第２の材料層は、Ｓｉ：Ｃである、請求項１に記載の方法。 The method of claim 1, wherein the second material layer is Si: C. 前記Ｓｉ：Ｃは、約４％以下のＣ含有量を有する、請求項３に記載の方法。 4. The method of claim 3, wherein the Si: C has a C content of about 4% or less. 前記第１の材料層は、非緩和ＳｉＧｅであり、前記第２の材料層は、非緩和Ｓｉ：Ｃであり、約１０〜１００ｎｍの厚みに形成される、請求項１に記載の方法。 The method of claim 1, wherein the first material layer is non-relaxed SiGe and the second material layer is non-relaxed Si: C and is formed to a thickness of about 10-100 nm. 前記第１の材料層は、前記ｎＦＥＴチャネル上にマスクを配置し、前記ｐＦＥＴスタックの領域をエッチングし、前記ｐＦＥＴチャネルの領域内の前記第１の材料層を選択的に成長させることにより形成され、
前記第２の材料層は、前記ｐＦＥＴチャネル上にマスクを配置し、前記ｎＦＥＴスタックの領域をエッチングし、前記ｎＦＥＴチャネルの領域内の前記第２の材料層を選択的に成長させることによって形成される、請求項１に記載の方法。 The first material layer is formed by placing a mask over the nFET channel, etching a region of the pFET stack, and selectively growing the first material layer in the region of the pFET channel. ,
The second material layer is formed by placing a mask over the pFET channel, etching a region of the nFET stack, and selectively growing the second material layer in the region of the nFET channel. The method of claim 1. 前記ｐＦＥＴスタックの領域のエッチングに先立って、前記マスク下で前記ｐＦＥＴスタックを覆って保護層を準備し、前記第１の材料層を選択的に成長させるステップと、
前記ｐＦＥＴスタックの領域のエッチングに先立って、前記マスク下で前記ｎＦＥＴスタックを覆って保護層を準備し、前記第２の材料層を選択的に成長させるステップとをさらに含む、請求項６に記載の方法。 Prior to etching a region of the pFET stack, providing a protective layer over the pFET stack under the mask and selectively growing the first material layer;
7. The method of claim 6, further comprising: providing a protective layer over the nFET stack under the mask and selectively growing the second material layer prior to etching the region of the pFET stack. the method of. 前記第１の材料層および前記第２の材料層は、厚さ約１０〜１００ｎｍに成長されている、請求項１に記載の方法。 The method of claim 1, wherein the first material layer and the second material layer are grown to a thickness of about 10-100 nm. 前記第１の材料層および前記第２の材料層は、前記基板に埋め込まれている、請求項１に記載の方法。 The method of claim 1, wherein the first material layer and the second material layer are embedded in the substrate. ｐ型電界効果トランジスタ（ｐＦＥＴ）チャネルおよびｎ型電界効果トランジスタ（ｎＦＥＴ）チャネルを基板内に形成するステップと、
前記ｐＦＥＴチャネルおよび前記ｎＦＥＴチャネルのそれぞれに関連して、前記ｐＦＥＴ構造およびｎＦＥＴ構造を基板上に形成するステップと、
前記ｐＦＥＴ構造および前記ｎＦＥＴ構造の領域をエッチングするステップと、
前記ｐＦＥＴ構造の領域内に、前記基板の基礎格子定数と異なる格子定数を有する第１の材料を形成して、前記ｐＦＥＴチャネルに圧縮応力を付与するステップと、
前記ｎＦＥＴ構造の領域内に、前記基板の基礎格子定数と異なる格子定数を有する第２の材料を形成して、前記ｎＦＥＴチャネルに引張応力を付与するステップと、
前記ｎＦＥＴおよびｐＦＥＴ構造のソースおよびドレイン領域をドーピングするステップとを含む、半導体構造の製造方法。 forming a p-type field effect transistor (pFET) channel and an n-type field effect transistor (nFET) channel in the substrate;
Forming the pFET structure and the nFET structure on a substrate in association with each of the pFET channel and the nFET channel;
Etching regions of the pFET structure and the nFET structure;
Forming a first material having a lattice constant different from a basic lattice constant of the substrate in a region of the pFET structure, and applying compressive stress to the pFET channel;
Forming a second material having a lattice constant different from a basic lattice constant of the substrate in a region of the nFET structure, and applying a tensile stress to the nFET channel;
Doping the source and drain regions of the nFET and pFET structures. 前記第１の材料は、ＳｉＧｅであり、前記第２の材料は、Ｓｉ：Ｃである、請求項１０に記載の方法。 The method of claim 10, wherein the first material is SiGe and the second material is Si: C. 前記第１の材料は、前記ｐＦＥＴチャネル内に圧縮応力を生成し、前記第２の材料は、ｎＦＥＴチャネル内に引張応力を生成する、請求項１１に記載の方法。 The method of claim 11, wherein the first material generates a compressive stress in the pFET channel and the second material generates a tensile stress in the nFET channel. 前記第１の材料は、前記ｎＦＥＴ構造および前記ｐＦＥＴ構造を覆って保護層を配置し、前記ｐＦＥＴチャネルのソースおよびドレイン領域内に、前記第１の材料を成長させることにより形成され、
前記第２の材料は、前記ｐＦＥＴ構造および前記ｎＦＥＴ構造のソースおよびドレイン領域を覆って保護層を配置し、前記ｎＦＥＴチャネルのソースおよびドレイン領域内に、前記第２の材料を成長させることにより形成される、請求項１０に記載の方法。 The first material is formed by placing a protective layer over the nFET structure and the pFET structure and growing the first material in the source and drain regions of the pFET channel;
The second material is formed by depositing a protective layer over the source and drain regions of the pFET structure and the nFET structure, and growing the second material in the source and drain regions of the nFET channel. 11. The method of claim 10, wherein: 前記第１の材料および前記第２の材料は、前記基板に埋め込まれている、請求項１０に記載の方法。 The method of claim 10, wherein the first material and the second material are embedded in the substrate. 前記第１の材料および前記第２の材料は、前記基板の表面上に隆起される、請求項１０に記載の方法。 The method of claim 10, wherein the first material and the second material are raised on a surface of the substrate. 前記第１の材料および前記第２の材料は、約１０〜１００ｎｍの厚さである、請求項１０に記載の方法。 The method of claim 10, wherein the first material and the second material are about 10-100 nm thick. 前記第１の材料は、非緩和ＳｉＧｅである、請求項１０に記載の方法。 The method of claim 10, wherein the first material is unrelaxed SiGe. 前記第１の材料をｐ型ドーピングで、前記第２の材料をｎ型ドーピングでそのままでドープして、それぞれｐＦＥＴおよびｎＦＥＴのソースおよびドレイン領域を形成する、請求項１０に記載の方法。 11. The method of claim 10, wherein the first material is doped with p-type doping and the second material is doped with n-type doping as is to form source and drain regions of the pFET and nFET, respectively. 基板内に形成されたｐ型電界効果トランジスタ（ｐＦＥＴ）チャネルと、
前記基板内に形成されたｎ型電界効果トランジスタ（ｎＦＥＴ）チャネルと、
前記基板の格子定数と異なる格子定数を有するｐＦＥＴチャネルのソースおよびドレイン領域内の第１の材料層と、
前記基板の格子定数と異なる格子定数を有するｎＦＥＴチャネルのソースおよびドレイン領域内の第２の材料層とを含む、半導体構造。 A p-type field effect transistor (pFET) channel formed in the substrate;
An n-type field effect transistor (nFET) channel formed in the substrate;
A first material layer in the source and drain regions of the pFET channel having a lattice constant different from the lattice constant of the substrate;
And a second material layer in the source and drain regions of the nFET channel having a lattice constant different from that of the substrate. 前記第１の材料層は、ＳｉＧｅであり、前記第２の材料層は、Ｓｉ：Ｃである、請求項１９に記載の構造。 21. The structure of claim 19, wherein the first material layer is SiGe and the second material layer is Si: C. 前記第１の材料層および前記第２の材料層は、前記ｐＦＥＴチャネルおよび前記ｎＦＥＴチャネルで、異なる種類の応力をそれぞれ生成する、請求項１９に記載の構造。 21. The structure of claim 19, wherein the first material layer and the second material layer generate different types of stresses in the pFET channel and the nFET channel, respectively.
JP2006536715A 2003-10-20 2004-10-19 High performance and stress enhanced MOSFETs using Si: C and SiGe epitaxially grown sources / drains and fabrication methods Pending JP2007528593A (en)

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