KR102484092B1 - Gate structure having high dielectric constant and band gap, and method for manufacturing the same - Google Patents

Abstract

The present invention relates to a gate structure having a high permittivity and a band gap and a method for manufacturing the same, and by controlling the incorporation method and ratio of different high-k dielectrics, a gate structure having a high permittivity and a low leakage current due to trap reduction and band gap expansion It is possible to provide a gate structure having a density and a manufacturing method thereof.

Description

Gate structure having high dielectric constant and band gap, and method for manufacturing the same}

The present invention relates to a gate structure having a high dielectric constant and a band gap and a method for manufacturing the same.

The gate oxide used in the metal-oxide-semiconductor field-effect transistor (MOSFET) serves to block the movement of electrons. Needs to be.

However, when the layer thickness of the gate oxide layer is increased, the transmission capability of the voltage from the gate to the substrate deteriorates. Therefore, the channel under the oxide film to be finally obtained is not formed within a desired time.

It is necessary to reduce the thickness of the gate oxide film due to technological development and demand, and even if the thickness of the gate oxide film is reduced, the basic function or performance of the device must be maintained. Therefore, it is necessary to make the material of the gate oxide film with a high dielectric constant in order to increase the insulating property of the oxide film. there is

However, in the case of conventionally used silicon oxide (SiO ₂ ) and silicon nitride (SiON), the application limit has already been reached due to downscaling of the gate stack.

In order to replace this, a technique of combining a high-k oxide with a III-V channel material has been recently studied, but in order to actually implement a MOS capacitor based on the III-V channel material, the surface of the III-V channel material needs to be vacant. (vacancies) The problem of forming electrically active traps due to unsaturated bonds due to defects and incomplete dimerization must be solved, and in the case of high-k oxides, the development of materials with high permittivity while having an appropriate band gap is required. situation is insufficient.

Therefore, there is a need to develop a gate structure capable of providing high operating speed, excellent reliability, condensed device density, and low power consumption while having a thin thickness suitable for the demand.

Republic of Korea Patent Publication No. 10-2006-0090828

An object of the present invention is to provide a gate structure having a high permittivity and a low leakage current density due to trap reduction and band gap expansion, and a manufacturing method thereof.

The present invention relates to a channel layer based on a group III-V compound; and a gate oxide film formed on the channel layer, wherein the gate oxide film has a structure in which a first metal oxide is incorporated into a second metal oxide, and a metal atom radius of the first metal oxide is a metal of the second metal oxide. We provide a gate structure smaller than the atomic radius.

In one embodiment, the metal of the first metal oxide and the second metal oxide is one selected from the group consisting of Al, Zr, Hf, Ti, Mg, La, Ca, Y, Ta, and Sr, and the first metal The metal of the oxide and the metal of the second metal oxide may be of different types.

As an example, the gate oxide layer may have a thickness of 3 nm to 10 nm.

As an example, the gate oxide layer may have a dielectric constant of 7 to 10 and a band gap of 5 to 8 eV.

As an example, the group III-V compound may be InP, InAs, InSb, AlGaAs or InGaAs.

As an example, the InGaAs may be In _x Ga _1-x As (x>0.5).

As an example, the content of the first metal oxide relative to the gate oxide layer may be 5 to 70% by weight.

In addition, the present invention is a gate oxide film including a first metal oxide and a second metal oxide by atomic layer deposition (ALD) using a first metal precursor, a second metal precursor, and an oxidizer on a channel layer based on a group III-V compound. Including the step of forming, wherein the first metal oxide and the second metal oxide are alternately and repeatedly deposited during the atomic layer deposition, and the metal oxide having a small atomic radius of the metal among the first metal precursor and the second metal precursor First, a method of manufacturing a gate structure to be deposited is provided.

As an example, when the number of cycles of the first metal oxide is x, the number of cycles of the second metal oxide is y, and the total number of cycles is n during the atomic layer deposition, x:y is 1:9 to 7:3 And, n may be 20 or less.

As an example, the first metal precursor may be trimethylaluminum, and the second metal precursor may be tetrakis (ethylmethylamido) hafnium.

As an example, the group III-V compound may be InP, InAs, InSb, AlGaAs or InGaAs.

As an example, the InGaAs may be In _x Ga _1-x As (x>0.5).

The present invention can provide a gate structure having a high permittivity and a low leakage current density due to trap reduction and band gap expansion, and a manufacturing method thereof, by controlling the incorporation method and ratio of different high-k dielectrics.

1 is a schematic diagram (a) of a gate oxide manufacturing process and a schematic diagram (b) showing the structure of a gate structure according to an embodiment of the present invention.
2 is a frequency dependent capacitance voltage (frequency) to which a frequency range of 10 kHz to 1 MHz is applied in Examples 1 (a), 2 (b), 3 (c) and 4 (d) of the present invention. It is a graph showing -dependent capacitance voltage (CV).
3 is a graph showing the effective dielectric constant (keffective) and band flattening voltage (V _FB ) extracted from Examples 1 to 4 of the present invention (a), a graph showing CV hysteresis (b) and a process of forming a pinhole-free film It is a schematic diagram (c) showing.
4(a) to 4(c) are Hf-4f, Al-2p and O-1s XPS spectra of Examples 1 to 4 of the present invention, and FIGS. 4(d) to 4(f) are of the present invention. As-3d, Ga-3d and In-3d spectra of Examples 1 to 4 and FIG. 4(g) are XRD spectra after RTA treatment at 350°C.
Figure 5 is a graph showing the extraction of the valance band offset (ΔE _v ) of the HfAlO film obtained by subtracting the VB spectrum of In0.53Ga0.47As from the spectrum of HfAlO/In0.53Ga0.47As of Examples 1 to 4 of the present invention. (a), a graph showing the energy gap (E _g ) extracted by defining the starting point of inter-band excitation of the REELS spectrum at 1 keV (b), band alignment values (c) and schematic band diagrams of Examples 1 to 4 It is the graph (d) shown.
Figure 6 (a) is a schematic diagram showing the electrical expression of the boundary trap model used in the present invention, Figure 6 (b) and Figure 6 (c) is a 1 -V between measured data and numerical data for capacitance and conductance It is a graph showing the fitting curve in , and FIG. 6 (d) is a graph comparing the extracted boundary trap density (N _bt ) with frequency dispersion and interface trap density (D _it ).
Figure 7 (a) shows the flow chart of the measurement procedure for measuring CV and IV of an E5250A low-leakage switch mainframe, and Figure 7 (b) shows the normalized CV curve of the stressed device and the 100 kHz 7(c) is a graph showing the threshold voltage shift (ΔV _TH ) after 2000 seconds of CVS at 1.5V for Examples 1 to 4.
8(a) is a graph showing the current-voltage characteristics measured at the positive bias voltage applied to the present invention, the calculated breakdown electric field of the HfAlO sample, and the leakage current density at the band flattening voltage, and FIG. It is a graph showing breakdown voltage and leakage current of Examples 1 to 4 of the invention.

Since the present invention can make various changes and have various embodiments, specific embodiments will be illustrated in the drawings and described in detail in the detailed description.

However, this is not intended to limit the present invention to specific embodiments, and should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention.

In the present invention, the term "comprises" or "has" is intended to designate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, but one or more other features It should be understood that the presence or addition of numbers, steps, operations, components, parts, or combinations thereof is not precluded.

Therefore, since the configurations shown in the embodiments described in this specification are only one of the most preferred embodiments of the present invention and do not represent all of the technical ideas of the present invention, various equivalents that can replace them at the time of this application and variations may exist.

The present invention relates to a channel layer based on a group III-V compound; and a gate oxide film formed on the channel layer, wherein the gate oxide film has a structure in which a first metal oxide is incorporated into a second metal oxide, and a metal atom radius of the first metal oxide is a metal of the second metal oxide. We provide a gate structure smaller than the atomic radius.

In the channel layer, the group III-V compound may be InP, InAs, InSb, AlGaAs, or InGaAs. The group III-V compound as described above may have a high electron mobility and injection rate due to a lower effective mass than conventionally used Si. By increasing the average carrier velocity due to the high mobility as described above, it is possible to have a high operative drive current and a high switching speed.

For example, the group III-V compound may be InGaAs, specifically In _x Ga _1-x As (x>0.5). In particular, In _0.53 Ga _0.47 As where x is 53 may have an electron mobility 8 times higher than that of Si.

The channel layer using InGaAs can provide a large band offset to the gate oxide film and provide a high level of separation between the low-mass gamma valley and the high-mass L- and X-valleys.

In the gate oxide film, the metal of the first metal oxide and the second metal oxide may be one selected from the group consisting of Al, Zr, Hf, Ti, Mg, La, Ca, Y, Ta, and Sr. For example, The metal of the first metal oxide may be Al, the first metal oxide may be Al ₂ O ₃ , the metal of the second metal oxide may be Hf, and the second metal oxide may be HfO ₂ .

In addition, the metal of the first metal oxide and the metal of the second metal oxide are preferably of different types, and the metal of the first metal oxide and the metal of the second metal oxide are of different types, so that the permittivity of each metal is different. And bandgap characteristics may be mutually supplemented.

The first metal oxide has a structure incorporated into the second metal oxide, and at this time, it is preferable that the metal atom radius of the first metal oxide is smaller than the metal atom radius of the second metal oxide.

Specifically, the structure in which the first metal oxide is mixed into the second metal oxide may be achieved by performing atomic layer deposition by alternately repeating the first metal oxide and the second metal oxide on the channel layer. At this time, by first depositing a first metal oxide having a small metal radius on the channel layer, the first metal oxide may be incorporated into the second metal oxide due to the small size of the first metal oxide after the subsequent deposition of the second metal oxide. can

At this time, in the atomic layer deposition, when the number of cycles of the first metal oxide is x, the number of cycles of the second metal oxide is y, and the total number of cycles is n, x: y is 1: 9 to 7: 3, and n can be performed below 20.

When atomic layer deposition is performed by the above method, the content of the first metal oxide with respect to the entire gate oxide layer may be 5 to 70% by weight, for example, 10 to 50% by weight, 20 to 50% by weight, or 30 to 50% by weight. 50% by weight or 40 to 50% by weight.

In addition, the atomic radius of the metal may be 125 pm for Al, 155 pm for Zr, 155 pm for Hf, 140 pm for Ti, and 195 pm for La.

As described above, when the first metal oxide is incorporated into the second metal oxide, the influence of interface traps and border traps may be minimized.

The interfacial trap causes an insufficient Fermi level response, weakens the charge carrier control of the channel, and lowers the driving current, and the boundary trap prevents the formation of sufficient carriers in the channel, increases phonon scattering, and reduces the threshold voltage. ) instability and transconductance degradation and hysteresis, reducing the performance of the device.

In addition, the dielectric constant, band gap, and characteristics thereof of the gate oxide layer may be controlled by incorporation of the first metal oxide and the second metal oxide.

Specifically, when the first metal oxide is Al ₂ O ₃ , it has a relatively large band gap (~8.8 eV), interface boundary self-cleaning effect, high thermal stability, and few active electrical defects, but Al ₂ O ₃ has an unsatisfactory dielectric constant (k = 6 to 9).

On the other hand, when the second metal oxide is HfO ₂ , HfO ₂ has a high dielectric constant (k = 20 to 25) and a moderate band gap (5.7 eV), but has low thermal and interfacial stability, large hysteresis, and leakage. tends to be high, and has the disadvantage that electrical traps are activated.

In the case of the gate oxide film and gate structure according to the present invention, the permittivity, band gap, and characteristics of the gate oxide film and the gate structure are properly adjusted by incorporating the first metal oxide and the second metal oxide and adjusting the ratio thereof. can be adjusted

Specifically, the gate oxide film according to the present invention may have a dielectric constant of 7 to 10 and a band gap of 5 to 8 eV.

For example, the dielectric constant of the gate oxide film according to the present invention may be 8 to 10 or 9 to 10, and the band gap of the gate oxide film according to the present invention may be 5 to 7 eV or 6 to 7 eV.

That is, the present invention can simultaneously achieve the above dielectric constant value and band gap.

Also, the thickness of the gate oxide layer may be 3 to 10 nm, and for example, the thickness of the gate oxide layer may be 4 to 8 nm or 4.5 to 6 nm. In the case of having the thickness as described above, it is possible to minimize interfaces and boundary traps and increase permittivity.

In addition, the present invention is a gate oxide film including a first metal oxide and a second metal oxide by atomic layer deposition (ALD) using a first metal precursor, a second metal precursor, and an oxidizer on a channel layer based on a group III-V compound. Including the step of forming, wherein the first metal oxide and the second metal oxide are alternately and repeatedly deposited during the atomic layer deposition, and the metal oxide having a small atomic radius of the metal among the first metal precursor and the second metal precursor First, a method of manufacturing a gate structure to be deposited is provided.

Among the first metal precursor and the second metal precursor, by first depositing a metal oxide having a small atomic radius, the small metal oxide may be incorporated into the large metal oxide.

At this time, in the atomic layer deposition, when the number of cycles of the first metal oxide is x, the number of cycles of the second metal oxide is y, and the total number of cycles is n, x: y is 1: 9 to 7: 3, and n can be performed below 20.

For example, x:y may be 1:5 to 6:4, 1:4 to 6:4, or 1:3 to 6:4, and n may be 15 or less, 12 or less, 11 or less, or 9 or less. or 8 or less.

In this case, the first metal precursor may be trimethylaluminum, and the second metal precursor may be tetrakis (ethylmethylamido) hafnium.

In the channel layer, the group III-V compound may be InP, InAs, InSb, AlGaAs, or InGaAs. The group III-V compound as described above may have a high electron mobility and injection rate due to a lower effective mass than conventionally used Si. By increasing the average carrier velocity due to the high mobility as described above, it is possible to have a high operative drive current and a high switching speed.

For example, the group III-V compound may be InGaAs, specifically In _x Ga _1-x As (x>0.5). In particular, In _0.53 Ga _0.47 As where x is 53 may have an electron mobility 8 times higher than that of Si.

The atomic layer deposition may be performed at 200 to 300 °C, for example, 220 to 280 °C or 240 to 260 °C.

Example

After epitaxially growing In0.53Ga0.47As on an InP substrate having a doping concentration of 5.7x10 ¹⁸ cm ^-3 (Si-doping), a temperature condition of 250°C on the In _0.53 Ga _0.47 As substrate A HfAlO film was deposited by the ALD method.

Trimethylaluminum (TMA) was used as a metal precursor for Al ₂ O ₃ and tetrakis(ethylmethylamido)hafnium(IV), TEMAH) was used as a precursor for HfO2.

H2O was used as an oxidizing agent and N2 was used as _a purge gas and carrier flow. Prior to ALD deposition, the substrate was cleaned with acetone and isopropyl alcohol for 5 minutes, followed by a 1:10 ratio hydrochloric acid (HCl) and deionized water (DI) solution for 30 seconds at room temperature to remove oxides and Surface contamination was removed. After acid cleaning, the substrates were rinsed in deionized water for 2 min and dried in a nitrogen (N2) environment to prevent water mask formation, and then transferred to the ALD chamber.

The HfAlO films of Examples 1-4 were prepared using the supercycle concept. At this time, the supercycle started with Al ₂ O ₃ , and the formula of (xAl ₂ O ₃ + yHfO ₂ )n was maintained. where x is the number of cycles of Al ₂ O ₃ , y is the number of cycles of HfO ₂ and n is the total number of supercycles.

The ratio of Al ₂ O ₃ to HfO ₂ in the supercycle was such that the ratio of Al ₂ O ₃ in the film was 10 to 50%. The number of super cycles was designed so that the total film thickness was about 5 nm in consideration of the growth per cycle (GPC) of Al ₂ O ₃ and HfO ₂ .

The overall schematic diagram of film deposition is shown in FIG. 1(a). For comparison, a single Al ₂ O ₃ (50 cycles) was used in Comparative Example 1, a single HfO ₂ (50 cycles) was used in Comparative Example 2, and a double layer structure of Al ₂ O ₃ /HfO ₂ (6/50 cycles) was used in Comparative Example 3. was prepared, and their thickness was the same as in the Example.

The thickness of the deposited film was quantified with an ellipsometer at an angle of incidence of 70°. The supercycle design and thickness are summarized in Table 1 below.

Classification (x,y) Al ₂ O ₃ (x) HfO ₂ (y) number of supercycles (n) thickness [nm] Example 1 [3,3] 3 3 9 5.95±0.05 Example 2 [2,6] 2 6 7 5.69±0.05 Example 3 [1,4] One 4 10 5.36±0.05 Example 4 [1,9] One 9 5 5.11±0.05 Comparative Example 1 [1, 0] One 0 50 5.51±0.05 Comparative Example 2 [0, 1] 0 One 50 4.95±0.05 Comparative Example 3 - - 6/50 5.58±0.05

)의 금속층을 전면 전극에 증착하였다. 또한, 동일한 금속층을 후면 접촉을 위해 증착하였다. SF6/Ar (30/10 sccm) 가스 기반 반응성 이온 에칭(reactive-ion etching, RIE)을 사용하여 TiN 층을 에칭하였다.Referring to FIG. 1(b), a 5 nm ALD TiN metal layer was deposited on the dielectric to form a MOSCAP (Metal Oxide Semiconductor Capacitor) for electrical analysis. Then, Ti/Au (200/2000

) was deposited on the front electrode. Also, the same metal layer was deposited for the back contact. The TiN layer was etched using SF6/Ar (30/10 sccm) gas-based reactive-ion etching (RIE).

The fabricated device was subjected to post-metal annealing (PMA) using rapid thermal annealing (RTA) at 350 °C for 90 seconds in an N ₂ environment to reduce defects due to metal deposition in the oxide/semiconductor gate stack. performed. The heat treatment is useful for densification of the film and passivation of the high-k/In _0.53 Ga _0.47 As interface and electrically active defects in the oxide itself, thereby achieving low interfacial trap density (D _it ) and boundary trap density (N _bt ). Could.

Capacitance-voltage and current-voltage responses were measured with a Keithley 4200A-SCS parameter analyzer at room temperature in a dark environment. In addition, X-ray photoelectron spectroscopy (XPS) and reflected electron energy loss spectrum (REELS) were performed to characterize the microstructure and measure the band gap of the HfAlO film.

Experimental example

Since Al ₂ O ₃ has a higher growth per cycle (GPC) than HfO ₂ , the film thickness increased as the number of Al ₂ O ₃ cycles increased in the supercycle. As a result, Example 1 had the highest thickness and Example 4 had the lowest thickness. In addition, since the super cycle consists of repeating cycles of Al ₂ O ₃ and HfO ₂ , the entire cycle was completed with priority given to avoiding partial deposition rather than matching a precise thickness of 5 nm. The thicknesses of Comparative Example 1, Comparative Example 2, and Comparative Example 3 were 5.51 nm, 4.95 nm, and 5.58 nm, respectively.

2 shows the frequency-dependent capacitance voltage (C-V) of the HfAlO films of Examples 1 to 4 in which a frequency range of 10 kHz to 1 MHz was applied at a gate voltage of -1 to + 1 V.

Referring to FIG. 2 , the accumulation dispersion of Example 1 to Example 4 increased as the Hf content of the film increased. This trend implies that the boundary trap response is significantly higher in Hf-rich films. In addition, the dispersion of the depletion region decreases as the concentration of Al atoms increases, suggesting that effective defect passivation can be obtained as the incorporation of Al increases.

As in Example 4, the accumulation capacitance increased as the Hf concentration increased, and the band flattening voltage (V _FB ) exhibited a positive shift as the Al ₂ O ₃ ratio increased.

3(a) shows the effective dielectric constant (keffective) and band flattening voltage (VFB) extracted in Examples 1 to 4. The dielectric constant was calculated from the C-V data measured in the accumulation region using Equation 1 below.

[Equation 1]

where C _max is the maximum stored capacitance at 10 kHz, t _ox is the measured thickness, and ε ₀ is the permittivity of free space. Since HfO ₂ has a higher k value, it was observed that the effective dielectric constant (k _effective ) increases as Hf increases. Specifically, Example 4 exhibited the highest effective dielectric constant of 9.83, and Examples 1 to 3 exhibited effective dielectric constants of 7.62, 8.6, and 8.76, respectively.

The EOT calculated based on the effective dielectric constant (k _effective ) was 3.05 nm, 2.58 nm, 2.39 nm, and 2.03 nm in Examples 1 to 4, respectively. The band flattening voltage (V _FB ) was extracted by the inflection point method by calculating the second derivative of the normalized CV data at the highest frequency that is least affected by traps.

Fig. 3(a) shows that V _FB shifts in a more positive direction with Al incorporation. This is because the incorporation of Al helps create oxygen deficiency by generating negatively charged dipoles after annealing.

The band flattening voltage by the inflection point method was 296.2 mV and 289 mV, respectively, with Examples 1 and 2 exhibiting almost the same level. The band flattening voltages of Example 3 and Example 4 were also similar, 172.7 mV and 171 mV, respectively. At this time, all band flattening voltage values were extracted with an error range of ± 0.1 mV.

A comparison of the CV hysteresis for the HfAlO film is shown in Fig. 3(b). For the hysteresis measurement, the CV sweep begins to move from inversion to accumulation and back to inversion without delay at the applied voltage from -1V to +1V in voltage steps of 0.02V at a frequency of 1MHz to avoid a trap response. Inverted.

As shown in FIG. 3(b), the hysteresis of Example 1 in which more Al ₂ O ₃ was incorporated into the HfO ₂ film was the lowest at 40 mV, and the hysteresis of Example 4 at 70 mV was the highest. However, all examples showed lower hysteresis than Comparative Example 2 (single HfO ₂ ), which was 90 mV.

]에 비하여 TMA의 높은 반응성과 낮은 미세 분자 반경 [0.39

]으로 설명할 수 있다.Since the hysteresis is mainly caused by trapping in the bulk dielectric as well as at the interface, this reduction in hysteresis is due to TEMAH [0.76

], the higher reactivity of TMA and the lower fine molecular radius [0.39

] can be explained.

That is, due to the above factors, TMA atoms can easily penetrate the HfO2 film during ALD deposition, thereby providing a compact Al ₂ O ₃ doped HfO ₂ film without pinholes.

3(c) shows the formation process of a pinhole-free film by TMA atoms. In addition, the Al-doped HfO ₂ film can passivate a better semiconductor/dielectric interface than HfO ₂ like Comparative Example 2.

XPS analysis was performed using a monochromatic Al Kα source with a photon energy of 1486 eV to understand the bonding structure and film stoichiometry of the deposited film.

4(a), (b) and (c) show Hf-4f, Al-2p and O-1s core level spectra for HfAlO films. 4(d), (e) and (f) show As-3d, Ga-3d and In-3d spectra for characterizing the interface.

In the case of Example 1 in FIG. 4(a), the Hf-4f spectrum is deconvoluted into two individual peaks of 4f _7/2 (17.48eV) and 4f _5/2 (18.98eV) corresponding to the Hf-O bond ( deconvolute was observed. The shift of the Hf-4f peak to higher binding energies compared to the pure sample is due to the Hf-Al-O bond formation, which is due to the Pauling electronegativity between Hf (1.3), Al (1.6) and O (3.44). Due to the degree difference, it increases the electron density contribution to the Al-O bond.

The Al-2p spectrum for Example 1 in FIG. 4(b) was deconvoluted at two peaks corresponding to Hf-Al-O (74.45 eV) and Al-O (74.9 eV) bonds. The O-1s spectrum for Example 1 in FIG. 4(c) was deconvoluted into two peaks at 530.84 eV and 532.18 eV. The lower peak represents the formation of Hf-Al-O, and the higher energy peak is due to hydrocarbons adsorbed on the surface.

Similar results were found for Examples 2 to 4 although there was a negative shift in the binding energy due to the low content of Al ₂ O ₃ depending on the deposition cycle design.

In addition, referring to FIG. 4(d), (e) and (f), the oxides (AsO _x , GaO _x and InO _x ) of the In _0.53 Ga _0.47 As film introduced with As are in the deposited HfAlO film due to ligand exchange. decreased, and this reduction was more dominant in the Al ₂ O ₃ -rich film. However, it was observed in FIG. 4(e) that Ga oxide, which creates traps, is always present in the film, which may be one of the causes of the high interfacial trap density.

After performing X-ray diffraction (XRD) analysis to analyze the crystallinity of the film deposited at a PMA temperature of 350 ° C., the spectrum is shown in FIG. 4 (g). Referring to FIG. 4(g), no other peak was detected except for HfO ₂ (002), which means that the film maintains an amorphous structure.

5 shows energy band parameters including conduction band offset (ΔE _c ), valance band offset (ΔE _v ) and energy gap (E _g ) and schematic band diagrams of Examples 1 to 4; indicate This energy band alignment between oxide and semiconductor can be calculated from a combination of the balance band (VB) spectrum obtained from XPS analysis and the energy loss spectrum obtained from reflected electron energy loss spectroscopy (REELS).

Figure 5 (a) shows the ΔE _v extraction of the HfAlO film obtained by subtracting the VB spectrum of In _0.53 Ga _0.47 As from the spectrum of HfAlO / In _0.53 Ga _0.47 As of Examples 1 to 4. The extracted ΔE _v values were 3.25 eV or less, 3.15 eV or less, 2.87 eV or less, and 2.72 eV or less for Examples 1 to 4, respectively, and the error range was ± 0.1 eV.

E _g extracted by defining the starting point of inter-band excitation of the REELS spectrum at 1 keV is shown in FIG. 5(b). The extracted band gap values were 6.39 eV or less, 6.26 eV or less, 5.92 eV or less, and 5.73 eV or less for Examples 1 to 4, respectively.

The effective electron barrier height (ΔEc) is the valance band offset (ΔEv) calculated from the oxide band gap (E _g ) calculated according to Equation 2 below and In _0.53 Ga _0.47 As (0.75 eV) It was calculated by subtracting the band gap of

[Equation 2]

The calculated ΔE _c value also showed the same trend as E _g and ΔE _v . The band alignment values for all cases are shown in FIG. 5(c), where the transitions of ΔEc, ΔEv, and Eg show lower values from Example 1 to Example 4. This shows that as more Al is incorporated into the HfO ₂ film, it not only provides a higher band alignment between the oxide film and the semiconductor, but also has a linear dependence on the amount of Al. A schematic band diagram of Examples 1 to 4 using all extracted values is shown in FIG. 5(d).

Among the models for the characterization of the accumulated dispersion, the distributed boundary trap model has a feature of analyzing the dispersion of the accumulated frequency at a specific voltage for the boundary trap density. Here, the total oxide is divided into several layers of thin thickness, and each single layer shows a contribution to the total oxide capacitance associated in parallel with an admittance proportional to N _bt . The parallel combination is connected in series with the semiconductor capacitance.

The admittance consists of trap capacitance and conductance, and is due to charge storage and energy loss for electron tunneling from the semiconductor to the boundary trap located inside the dielectric. After that, N _bt was extracted by applying a suitable condition between the calculated capacitance derived from this model and the measured value.

Fig. 6(a) shows the electrical expression of the boundary trap model, and the entire model is described according to the differential equation of Equation 3 below.

[Equation 3]

At the boundary condition Y = jωCs, Y is the total admittance, which is the combination of trap capacitance and conductance at a distance x from the dielectric-semiconductor interface, ω = 2πf is the ac frequency, and Cs is the capacitance of the semiconductor. εr is the relative permittivity, τ is the average time for electron trapping, and _Nbt is the boundary _trap density at all energy levels.

The boundary trap density was extracted by creating an optimal condition between the measured capacitance and the conductance data using the data extracted from Equation 2 above. The semiconductor capacitance, Cs, was extracted by a one-dimensional Poisson-Schrodinger solver simulation tool (Nextnano) from the extracted voltage of the boundary trap. The effective barrier height between the oxide and the semiconductor was calculated by the electron affinity rule and the effective electron mass was 0.23 m ₀ , 0.22 m ₀ and 0.18 m ₀ for the Al ₂ O ₃ , HfO ₂ and HfAlO films, respectively, where m ₀ is the electron is the rest mass.

6(b) and (c) show fitting curves at 1-V between measured data and numerical data for capacitance and conductance. However, there is a small deviation between the experimental data and equations in the fitting curve, which may be due to the high density of boundary traps.

The extracted boundary trap density (N _bt ), frequency dispersion, and interface trap density (D _it ) were compared and shown in FIG. 6(d). At this time, for comparison, the corresponding values of Comparative Examples 1 to 3 are shown together. Referring to FIG. 6(d), Comparative Example 1 has the lowest Nbt of 4.67×10 ¹⁹ cm ^-3 eV ^-1 , whereas Comparative Example 2 has the highest _Nbt (3.25×10 ²⁰ cm ^-3 eV ^-1 ) showed

This means that the larger the amount of Hf in the HfAlO film, the wider the trap, and the HfO ₂ film incorporating Al can reduce these traps. The Nbt values extracted for the HfAlO films were 4.82×10 ¹⁹ cm ^-3 eV ^-1 , 5.32×10 ¹⁹ cm ^-3 eV ^-1 , 5.81×10 ¹⁹ cm ^-3 eV ^-1 and 1.4 in Examples 1 to 4, respectively. ×10 ²⁰ cm ^-3 eV ^-1 , and in the case of Comparative Example 3, it was 1.28 × 10 ²⁰ cm ^-3 eV ^-1 .

As described above, the trap reduction by Al incorporation is because continuous and compact films can be produced by Al ₂ O ₃ infiltration.

Since it has been demonstrated that the accumulation frequency dispersion is related to the boundary trap density, the same behavior is observed in the calculation of the frequency dispersion at 1 V according to Equation 4 below.

[Equation 4]

Here, C _high and C _low are the corresponding capacitance values at ω _high (1 MHz) and ω _low (10 kHz). In addition, the parallel conductance was measured considering the series resistance correction, and the interfacial defect state (D _it ) was calculated according to the conductance method. Equivalent parallel conductance G _p was calculated by Equation 5 below.

[Equation 5]

where ω is the angular frequency (2πf), C _ox is the gate oxide capacitance, G _m is the measured conductance, and C _m is the measured capacitance. The interfacial trap density (D _it ) was calculated from the normalized parallel conductance peak (G _p /ω _max ).

[Equation 6]

Here, A is the electrode area, and referring to FIG. 6(d), the D _it value increases as the Hf content in the HfAlO film increases, and the interfacial trap density of Comparative Example 1 is 1.66×10 ¹¹ cm ^-2 eV ^{- 1} was the lowest and Comparative Example 2 was the highest at 3.38×10 ¹² cm ^-2 eV ^-1 .

This decrease in Dit can be attributed to the remote selective oxygen scavenging phenomenon of Al ₂ O ₃ . During ALD deposition of Al ₂ O ₃ , after removal of surface hydroxyl groups from nanolaminate films, TMA precursors are present in excess and reduce additional species that diffuse outward through HfO ₂ or are generated remotely from the deposition surface.

Constant-voltage-stress (CVS) measurements were performed on Examples 1 to 4 using a B1500A semiconductor device parameter analyzer to confirm the reliability of the deposited films.

The threshold voltage shift according to the measurement procedure and the stress time is shown in FIG. 7 . In the CVS measurement, the stress is stopped after a certain time interval, allowing the degradation of the device to be tracked through the calculation of the threshold voltage shift (ΔVTH) in the C-V measurement.

7(a) shows a flow chart of a measurement procedure for measuring C-V and I-V of an E5250A low-leakage switch mainframe.

The normalized CV curves of the stressed device and the new case at 100 kHz are plotted in Fig. 7(b), and the threshold voltage shift (ΔV _TH ) was calculated from the CV curves of the stressed device and the new device.

A positive shift was observed in all cases, indicating increased negative charge trapping at the oxide and/or oxide/semiconductor interface.

The threshold voltage shift (ΔV _TH ) after 2000 seconds of CVS at 1.5V for Examples 1 to 4 is shown in FIG. 7(c). where ΔV _TH is the difference between the threshold voltage of the new device and the stressed device.

A positive shift in the threshold voltage at forward bias stress indicates electron capture from the semiconductor to the oxide and passivation of positive charges.

Referring to Fig. 7(c), Example 1 has the lowest shift of 86.2 mV while Example 4 has the highest (282.5 eV) shift. Thus, this stress-induced charge trapping maintains linearity with the Hf content, and a larger amount of charge is trapped with increasing Hf.

The measured current-voltage characteristics at the applied positive bias voltage and the calculated breakdown electric field of the HfAlO sample and the leakage current density at the band flattening voltage are shown in FIG. 8 .

Referring to FIG. 8(a) , as the Al content in the deposited film increases, the leakage current decreases and the breakdown voltage increases. The breakdown field was calculated by dividing the breakdown voltage by the measured thickness. Referring to FIG. 8B, Example 1 had the highest breakdown field (5.71 MV/cm) and the lowest leakage current (1.14×10 ^-7 A/cm). cm ² )), and Example 4 showed the lowest breakdown voltage (4.73 MV/cm) and the highest leakage current (1.19×10 ^-4 A/cm ² ).

The increase in breakdown field and decrease in leakage current with increasing Al incorporation can be attributed to the increase in band gap as the Al incorporation increases, as well as the increase in defects at the oxide and interface, respectively, and the passivation effect dependent on it.

The Hf-dominant HfAlO film exhibited a high dielectric constant due to the high relative permittivity of HfO ₂ , whereas larger Al incorporation induced more positive band flattening voltage due to dipole formation.

In the gate oxide film according to the present invention, it was found that the band gap and the conduction and balance band edges increased when Al was incorporated into the HfO ₂ film through extraction of electric band parameters.

Al fusion can also minimize traps inside HfO ₂ by chemical activity and penetration, which provided low hysteresis and accumulation dispersion as well as low boundary trap density.

Claims (12)

a channel layer based on a group III-V compound; and
A gate oxide film formed on the channel layer;
The gate oxide film has a structure in which a first metal oxide is incorporated into a second metal oxide,
The metal atomic radius of the first metal oxide is smaller than the metal atomic radius of the second metal oxide;
The first metal oxide and the second metal oxide are alternately and repeatedly deposited,
The content of the first metal oxide relative to the gate oxide layer is 5 to 70% by weight,
The atomic layer deposition of the first metal oxide and the second metal oxide is such that x:y is 1:9 when the number of cycles of the first metal oxide is x, the number of cycles of the second metal oxide is y, and the total number of cycles is n. to 7:3, with n being less than or equal to 20;
The thickness of the gate oxide film is 3 to 10 nm,
A gate structure having a dielectric constant of 7 to 10 and a band gap of 5 to 8 eV.
According to claim 1,
The metal of the first metal oxide and the second metal oxide is one selected from the group consisting of Al, Zr, Hf, Ti, Mg, La, Ca, Y, Ta and Sr,
The metal of the first metal oxide and the metal of the second metal oxide are different types of gate structure.
delete delete According to claim 1,
The III-V compound is InP, InAs, InSb, AlGaAs or InGaAs gate structure. According to claim 5,
The InGaAs gate structure of In _x Ga _1-x As (x>0.5).
delete Forming a gate oxide film including a first metal oxide and a second metal oxide by atomic layer deposition (ALD) using a first metal precursor, a second metal precursor, and an oxidizer on a channel layer based on a group III-V compound include,
During the atomic layer deposition, the first metal oxide and the second metal oxide are alternately and repeatedly deposited,
The metal atomic radius of the first metal oxide is smaller than the metal atomic radius of the second metal oxide;
By first depositing a first metal oxide having a small metal radius on the channel layer, the first metal oxide may be incorporated into the second metal oxide due to the small size of the first metal oxide after subsequent deposition of the second metal oxide, ,
The method of manufacturing the gate structure of claim 1, wherein the content of the first metal oxide relative to the gate oxide layer is 5 to 70% by weight.
delete According to claim 8,
The first metal precursor is trimethylaluminum,
The method of manufacturing a gate structure in which the second metal precursor is tetrakis (ethylmethylamido) hafnium.
According to claim 8,
The III-V compound is a method of manufacturing a gate structure of InP, InAs, InSb, AlGaAs or InGaAs.

According to claim 11,
The InGaAs is In _x Ga _1-x As (x> 0.5) method of manufacturing a gate structure.

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